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  1. /*
  2.  * Copyright © 2010 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the
  6.  * "Software"), to deal in the Software without restriction, including
  7.  * without limitation the rights to use, copy, modify, merge, publish,
  8.  * distribute, sub license, and/or sell copies of the Software, and to
  9.  * permit persons to whom the Software is furnished to do so, subject to
  10.  * the following conditions:
  11.  *
  12.  * The above copyright notice and this permission notice (including the
  13.  * next paragraph) shall be included in all copies or substantial portions
  14.  * of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19.  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors:
  25.  *    Zhou Chang <chang.zhou@intel.com>
  26.  *
  27.  */
  28.  
  29. #ifndef _GEN6_MFC_H_
  30. #define _GEN6_MFC_H_
  31.  
  32. #include <drm.h>
  33. #include <i915_drm.h>
  34. #include <intel_bufmgr.h>
  35.  
  36. #include "i965_gpe_utils.h"
  37.  
  38. struct encode_state;
  39.  
  40. #define MAX_MFC_REFERENCE_SURFACES      16
  41. #define NUM_MFC_DMV_BUFFERS             34
  42.  
  43. #define INTRA_MB_FLAG_MASK              0x00002000
  44.  
  45. /* The space required for slice header SLICE_STATE + header.
  46.  * Is it enough? */
  47. #define SLICE_HEADER                    80
  48.  
  49. /* the space required for slice tail. */
  50. #define SLICE_TAIL                      16
  51.  
  52. #define __SOFTWARE__    0
  53.  
  54. #define MFC_BATCHBUFFER_AVC_INTRA       0
  55. #define MFC_BATCHBUFFER_AVC_INTER       1
  56. #define NUM_MFC_KERNEL                  2
  57.  
  58. #define BIND_IDX_VME_OUTPUT             0
  59. #define BIND_IDX_MFC_SLICE_HEADER       1
  60. #define BIND_IDX_MFC_BATCHBUFFER        2
  61.  
  62. #define CMD_LEN_IN_OWORD        4
  63.  
  64.  
  65. typedef enum _gen6_brc_status
  66. {
  67.     BRC_NO_HRD_VIOLATION = 0,
  68.     BRC_UNDERFLOW = 1,
  69.     BRC_OVERFLOW = 2,
  70.     BRC_UNDERFLOW_WITH_MAX_QP = 3,
  71.     BRC_OVERFLOW_WITH_MIN_QP = 4,
  72. } gen6_brc_status;
  73.  
  74. struct gen6_mfc_avc_surface_aux
  75. {
  76.     dri_bo *dmv_top;
  77.     dri_bo *dmv_bottom;
  78. };
  79.  
  80. struct gen6_mfc_context
  81. {
  82.     struct {
  83.         unsigned int width;
  84.         unsigned int height;
  85.         unsigned int w_pitch;
  86.         unsigned int h_pitch;
  87.     } surface_state;
  88.  
  89.     //MFX_PIPE_BUF_ADDR_STATE
  90.     struct {
  91.         dri_bo *bo;                            
  92.     } post_deblocking_output;           //OUTPUT: reconstructed picture                          
  93.    
  94.     struct {  
  95.         dri_bo *bo;                                                            
  96.     } pre_deblocking_output;            //OUTPUT: reconstructed picture with deblocked                          
  97.  
  98.     struct {
  99.         dri_bo *bo;
  100.     } uncompressed_picture_source;      //INPUT: original compressed image
  101.  
  102.     struct {
  103.         dri_bo *bo;                                                            
  104.     } intra_row_store_scratch_buffer;   //INTERNAL:
  105.  
  106.     struct {
  107.         dri_bo *bo;
  108.     } macroblock_status_buffer;         //INTERNAL:
  109.  
  110.     struct {
  111.         dri_bo *bo;                                                            
  112.     } deblocking_filter_row_store_scratch_buffer;       //INTERNAL:
  113.  
  114.     struct {                                    
  115.         dri_bo *bo;
  116.     } reference_surfaces[MAX_MFC_REFERENCE_SURFACES];   //INTERNAL: refrence surfaces
  117.  
  118.     //MFX_IND_OBJ_BASE_ADDR_STATE
  119.     struct{
  120.         dri_bo *bo;
  121.     } mfc_indirect_mv_object;           //INPUT: the blocks' mv info
  122.  
  123.     struct {
  124.         dri_bo *bo;
  125.         int offset;
  126.         int end_offset;
  127.     } mfc_indirect_pak_bse_object;      //OUTPUT: the compressed bitstream
  128.  
  129.     //MFX_BSP_BUF_BASE_ADDR_STATE
  130.     struct {
  131.         dri_bo *bo;
  132.     } bsd_mpc_row_store_scratch_buffer; //INTERNAL:
  133.        
  134.     //MFX_AVC_DIRECTMODE_STATE
  135.     struct {
  136.         dri_bo *bo;
  137.     } direct_mv_buffers[NUM_MFC_DMV_BUFFERS];   //INTERNAL: 0-31 as input,32 and 33 as output
  138.  
  139.     //Bit rate tracking context
  140.     struct {
  141.         unsigned int QpPrimeY;
  142.         unsigned int MaxQpNegModifier;
  143.         unsigned int MaxQpPosModifier;
  144.         unsigned char MaxSizeInWord;
  145.         unsigned char TargetSizeInWord;
  146.         unsigned char Correct[6];
  147.         unsigned char GrowInit;
  148.         unsigned char GrowResistance;
  149.         unsigned char ShrinkInit;
  150.         unsigned char ShrinkResistance;
  151.  
  152.         unsigned int target_mb_size;
  153.         unsigned int target_frame_size;
  154.     } bit_rate_control_context[3];      //INTERNAL: for I, P, B frames
  155.  
  156.     struct {
  157.         int mode;
  158.         int gop_nums[3];
  159.         int target_frame_size[3]; // I,P,B
  160.         double bits_per_frame;
  161.         double qpf_rounding_accumulator;
  162.  
  163.         double saved_bps;
  164.         double saved_fps;
  165.         int saved_intra_period;
  166.         int saved_ip_period;
  167.         int saved_idr_period;
  168.     } brc;
  169.  
  170.     struct {
  171.         double current_buffer_fullness;
  172.         double target_buffer_fullness;
  173.         double buffer_capacity;
  174.         unsigned int buffer_size;
  175.         unsigned int violation_noted;
  176.     } hrd;
  177.  
  178.     //HRD control context
  179.     struct {
  180.         int i_bit_rate_value;
  181.         int i_cpb_size_value;
  182.  
  183.         int i_initial_cpb_removal_delay;
  184.         int i_cpb_removal_delay;
  185.  
  186.         int i_frame_number;
  187.  
  188.         int i_initial_cpb_removal_delay_length;
  189.         int i_cpb_removal_delay_length;
  190.         int i_dpb_output_delay_length;
  191.     }vui_hrd;
  192.  
  193.     struct i965_gpe_context gpe_context;
  194.     struct i965_buffer_surface mfc_batchbuffer_surface;
  195.     struct intel_batchbuffer *aux_batchbuffer;
  196.     struct i965_buffer_surface aux_batchbuffer_surface;
  197.  
  198.     void (*pipe_mode_select)(VADriverContextP ctx,
  199.                              int standard_select,
  200.                              struct intel_encoder_context *encoder_context);
  201.     void (*set_surface_state)(VADriverContextP ctx,
  202.                               struct intel_encoder_context *encoder_context);
  203.     void (*ind_obj_base_addr_state)(VADriverContextP ctx,
  204.                                     struct intel_encoder_context *encoder_context);
  205.     void (*avc_img_state)(VADriverContextP ctx,
  206.                           struct encode_state *encode_state,
  207.                           struct intel_encoder_context *encoder_context);
  208.     void (*avc_qm_state)(VADriverContextP ctx,
  209.                          struct intel_encoder_context *encoder_context);
  210.     void (*avc_fqm_state)(VADriverContextP ctx,
  211.                           struct intel_encoder_context *encoder_context);
  212.     void (*insert_object)(VADriverContextP ctx,
  213.                           struct intel_encoder_context *encoder_context,
  214.                           unsigned int *insert_data,
  215.                           int lenght_in_dws, int data_bits_in_last_dw,
  216.                           int skip_emul_byte_count,
  217.                           int is_last_header, int is_end_of_slice,
  218.                           int emulation_flag,
  219.                           struct intel_batchbuffer *batch);
  220.     void (*buffer_suface_setup)(VADriverContextP ctx,
  221.                                 struct i965_gpe_context *gpe_context,
  222.                                 struct i965_buffer_surface *buffer_surface,
  223.                                 unsigned long binding_table_offset,
  224.                                 unsigned long surface_state_offset);
  225. };
  226.  
  227. VAStatus gen6_mfc_pipeline(VADriverContextP ctx,
  228.                            VAProfile profile,
  229.                            struct encode_state *encode_state,
  230.                            struct intel_encoder_context *encoder_context);
  231. void gen6_mfc_context_destroy(void *context);
  232.  
  233. extern
  234. Bool gen75_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
  235.  
  236.  
  237. extern int intel_mfc_update_hrd(struct encode_state *encode_state,
  238.                                 struct gen6_mfc_context *mfc_context,
  239.                                 int frame_bits);
  240.  
  241. extern int intel_mfc_brc_postpack(struct encode_state *encode_state,
  242.                                   struct gen6_mfc_context *mfc_context,
  243.                                   int frame_bits);
  244.  
  245. extern void intel_mfc_hrd_context_update(struct encode_state *encode_state,
  246.                                          struct gen6_mfc_context *mfc_context);
  247.  
  248. extern int intel_mfc_interlace_check(VADriverContextP ctx,
  249.                                      struct encode_state *encode_state,
  250.                                      struct intel_encoder_context *encoder_context);
  251.  
  252. extern void intel_mfc_brc_prepare(struct encode_state *encode_state,
  253.                                   struct intel_encoder_context *encoder_context);
  254.  
  255. extern void intel_mfc_avc_pipeline_header_programing(VADriverContextP ctx,
  256.                                                      struct encode_state *encode_state,
  257.                                                      struct intel_encoder_context *encoder_context,
  258.                                                      struct intel_batchbuffer *slice_batch);
  259.  
  260. extern VAStatus intel_mfc_avc_prepare(VADriverContextP ctx,
  261.                                       struct encode_state *encode_state,
  262.                                       struct intel_encoder_context *encoder_context);
  263.  
  264. extern int intel_avc_enc_slice_type_fixup(int type);
  265.  
  266. extern void
  267. intel_mfc_avc_ref_idx_state(VADriverContextP ctx,
  268.                             struct encode_state *encode_state,
  269.                             struct intel_encoder_context *encoder_context);
  270.  
  271. extern
  272. Bool gen8_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
  273.  
  274. extern void
  275. intel_avc_slice_insert_packed_data(VADriverContextP ctx,
  276.                              struct encode_state *encode_state,
  277.                              struct intel_encoder_context *encoder_context,
  278.                              int slice_index,
  279.                              struct intel_batchbuffer *slice_batch);
  280.  
  281. #endif  /* _GEN6_MFC_BCS_H_ */
  282.