Subversion Repositories Kolibri OS

Rev

Rev 4363 | Go to most recent revision | Blame | Compare with Previous | Last modification | View Log | RSS feed

  1. /*
  2.  * Copyright ะน 2007 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21.  * IN THE SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *    Eric Anholt <eric@anholt.net>
  25.  *
  26.  */
  27.  
  28. #ifdef HAVE_CONFIG_H
  29. #include "config.h"
  30. #endif
  31.  
  32. #include <string.h>
  33. #include <stdlib.h>
  34. #include <stdint.h>
  35. #include <assert.h>
  36. #include <errno.h>
  37. #include <drm.h>
  38. #include <i915_drm.h>
  39. //#include <pciaccess.h>
  40. #include "intel_bufmgr.h"
  41. #include "intel_bufmgr_priv.h"
  42. #include "xf86drm.h"
  43.  
  44. /** @file intel_bufmgr.c
  45.  *
  46.  * Convenience functions for buffer management methods.
  47.  */
  48.  
  49. drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
  50.                                  unsigned long size, unsigned int alignment)
  51. {
  52.         return bufmgr->bo_alloc(bufmgr, name, size, alignment);
  53. }
  54.  
  55. drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
  56.                                             const char *name,
  57.                                             unsigned long size,
  58.                                             unsigned int alignment)
  59. {
  60.         return bufmgr->bo_alloc_for_render(bufmgr, name, size, alignment);
  61. }
  62.  
  63. drm_intel_bo *
  64. drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
  65.                         int x, int y, int cpp, uint32_t *tiling_mode,
  66.                         unsigned long *pitch, unsigned long flags)
  67. {
  68.         return bufmgr->bo_alloc_tiled(bufmgr, name, x, y, cpp,
  69.                                       tiling_mode, pitch, flags);
  70. }
  71.  
  72. void drm_intel_bo_reference(drm_intel_bo *bo)
  73. {
  74.         bo->bufmgr->bo_reference(bo);
  75. }
  76.  
  77. void drm_intel_bo_unreference(drm_intel_bo *bo)
  78. {
  79.         if (bo == NULL)
  80.                 return;
  81.  
  82.         bo->bufmgr->bo_unreference(bo);
  83. }
  84.  
  85. int drm_intel_bo_map(drm_intel_bo *buf, int write_enable)
  86. {
  87.         return buf->bufmgr->bo_map(buf, write_enable);
  88. }
  89.  
  90. int drm_intel_bo_unmap(drm_intel_bo *buf)
  91. {
  92.         return buf->bufmgr->bo_unmap(buf);
  93. }
  94.  
  95. int
  96. drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
  97.                      unsigned long size, const void *data)
  98. {
  99.         return bo->bufmgr->bo_subdata(bo, offset, size, data);
  100. }
  101.  
  102. int
  103. drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
  104.                          unsigned long size, void *data)
  105. {
  106.         int ret;
  107. //      if (bo->bufmgr->bo_get_subdata)
  108. //              return bo->bufmgr->bo_get_subdata(bo, offset, size, data);
  109.  
  110.         if (size == 0 || data == NULL)
  111.                 return 0;
  112.  
  113.         ret = drm_intel_bo_map(bo, 0);
  114.         if (ret)
  115.                 return ret;
  116.         memcpy(data, (unsigned char *)bo->virtual + offset, size);
  117.         drm_intel_bo_unmap(bo);
  118.         return 0;
  119. }
  120.  
  121. void drm_intel_bo_wait_rendering(drm_intel_bo *bo)
  122. {
  123.         bo->bufmgr->bo_wait_rendering(bo);
  124. }
  125.  
  126. void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr)
  127. {
  128.         bufmgr->destroy(bufmgr);
  129. }
  130.  
  131. int
  132. drm_intel_bo_exec(drm_intel_bo *bo, int used,
  133.                   drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
  134. {
  135.         return bo->bufmgr->bo_exec(bo, used, cliprects, num_cliprects, DR4);
  136. }
  137.  
  138. int
  139. drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
  140.                 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
  141.                 unsigned int rings)
  142. {
  143.         if (bo->bufmgr->bo_mrb_exec)
  144.                 return bo->bufmgr->bo_mrb_exec(bo, used,
  145.                                         cliprects, num_cliprects, DR4,
  146.                                         rings);
  147.  
  148.         switch (rings) {
  149.         case I915_EXEC_DEFAULT:
  150.         case I915_EXEC_RENDER:
  151.                 return bo->bufmgr->bo_exec(bo, used,
  152.                                            cliprects, num_cliprects, DR4);
  153.         default:
  154.                 return -ENODEV;
  155.         }
  156. }
  157.  
  158. void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug)
  159. {
  160.         bufmgr->debug = enable_debug;
  161. }
  162.  
  163. int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count)
  164. {
  165.         return bo_array[0]->bufmgr->check_aperture_space(bo_array, count);
  166. }
  167.  
  168. int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name)
  169. {
  170.         if (bo->bufmgr->bo_flink)
  171.                 return bo->bufmgr->bo_flink(bo, name);
  172.  
  173.         return -ENODEV;
  174. }
  175.  
  176. int
  177. drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
  178.                         drm_intel_bo *target_bo, uint32_t target_offset,
  179.                         uint32_t read_domains, uint32_t write_domain)
  180. {
  181.         return bo->bufmgr->bo_emit_reloc(bo, offset,
  182.                                          target_bo, target_offset,
  183.                                          read_domains, write_domain);
  184. }
  185.  
  186. /* For fence registers, not GL fences */
  187. int
  188. drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
  189.                               drm_intel_bo *target_bo, uint32_t target_offset,
  190.                               uint32_t read_domains, uint32_t write_domain)
  191. {
  192.         return bo->bufmgr->bo_emit_reloc_fence(bo, offset,
  193.                                                target_bo, target_offset,
  194.                                                read_domains, write_domain);
  195. }
  196.  
  197.  
  198. int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment)
  199. {
  200.         if (bo->bufmgr->bo_pin)
  201.                 return bo->bufmgr->bo_pin(bo, alignment);
  202.  
  203.         return -ENODEV;
  204. }
  205.  
  206. int drm_intel_bo_unpin(drm_intel_bo *bo)
  207. {
  208.         if (bo->bufmgr->bo_unpin)
  209.                 return bo->bufmgr->bo_unpin(bo);
  210.  
  211.         return -ENODEV;
  212. }
  213.  
  214. int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
  215.                             uint32_t stride)
  216. {
  217.         if (bo->bufmgr->bo_set_tiling)
  218.                 return bo->bufmgr->bo_set_tiling(bo, tiling_mode, stride);
  219.  
  220.         *tiling_mode = I915_TILING_NONE;
  221.         return 0;
  222. }
  223.  
  224. int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
  225.                             uint32_t * swizzle_mode)
  226. {
  227.         if (bo->bufmgr->bo_get_tiling)
  228.                 return bo->bufmgr->bo_get_tiling(bo, tiling_mode, swizzle_mode);
  229.  
  230.         *tiling_mode = I915_TILING_NONE;
  231.         *swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
  232.         return 0;
  233. }
  234.  
  235. int drm_intel_bo_disable_reuse(drm_intel_bo *bo)
  236. {
  237.         if (bo->bufmgr->bo_disable_reuse)
  238.                 return bo->bufmgr->bo_disable_reuse(bo);
  239.         return 0;
  240. }
  241.  
  242. int drm_intel_bo_is_reusable(drm_intel_bo *bo)
  243. {
  244.         if (bo->bufmgr->bo_is_reusable)
  245.                 return bo->bufmgr->bo_is_reusable(bo);
  246.         return 0;
  247. }
  248.  
  249. int drm_intel_bo_busy(drm_intel_bo *bo)
  250. {
  251.         if (bo->bufmgr->bo_busy)
  252.                 return bo->bufmgr->bo_busy(bo);
  253.         return 0;
  254. }
  255.  
  256. int drm_intel_bo_madvise(drm_intel_bo *bo, int madv)
  257. {
  258.         if (bo->bufmgr->bo_madvise)
  259.                 return bo->bufmgr->bo_madvise(bo, madv);
  260.         return -1;
  261. }
  262.  
  263. int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
  264. {
  265.         return bo->bufmgr->bo_references(bo, target_bo);
  266. }
  267.  
  268.  
  269.  
  270. #if 0
  271. static size_t
  272. drm_intel_probe_agp_aperture_size(int fd)
  273. {
  274.         struct pci_device *pci_dev;
  275.         size_t size = 0;
  276.         int ret;
  277.  
  278.         ret = pci_system_init();
  279.         if (ret)
  280.                 goto err;
  281.  
  282.         /* XXX handle multiple adaptors? */
  283.         pci_dev = pci_device_find_by_slot(0, 0, 2, 0);
  284.         if (pci_dev == NULL)
  285.                 goto err;
  286.  
  287.         ret = pci_device_probe(pci_dev);
  288.         if (ret)
  289.                 goto err;
  290.  
  291.         size = pci_dev->regions[2].size;
  292. err:
  293.         pci_system_cleanup ();
  294.         return size;
  295. }
  296. #endif
  297.  
  298. int drm_intel_get_aperture_sizes(int fd,
  299.                                  size_t *mappable,
  300.                                  size_t *total)
  301. {
  302.  
  303.         struct drm_i915_gem_get_aperture aperture;
  304.         int ret;
  305.  
  306.         ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
  307.         if (ret)
  308.                 return ret;
  309.  
  310.         /* XXX add a query for the kernel value? */
  311.     *mappable = 512 * 1024 * 1024; /* minimum possible value */
  312.         *total = aperture.aper_size;
  313.         return 0;
  314. }
  315.