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  1. /*
  2.  * Copyright © 2011 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21.  * IN THE SOFTWARE.
  22.  */
  23.  
  24. #include "intel_batchbuffer.h"
  25. #include "intel_mipmap_tree.h"
  26. #include "intel_regions.h"
  27. #include "intel_fbo.h"
  28. #include "brw_context.h"
  29. #include "brw_state.h"
  30. #include "brw_defines.h"
  31.  
  32. void
  33. gen7_emit_depth_stencil_hiz(struct brw_context *brw,
  34.                             struct intel_mipmap_tree *depth_mt,
  35.                             uint32_t depth_offset, uint32_t depthbuffer_format,
  36.                             uint32_t depth_surface_type,
  37.                             struct intel_mipmap_tree *stencil_mt,
  38.                             bool hiz, bool separate_stencil,
  39.                             uint32_t width, uint32_t height,
  40.                             uint32_t tile_x, uint32_t tile_y)
  41. {
  42.    struct gl_context *ctx = &brw->ctx;
  43.    uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
  44.  
  45.    intel_emit_depth_stall_flushes(brw);
  46.  
  47.    /* _NEW_DEPTH, _NEW_STENCIL, _NEW_BUFFERS */
  48.    BEGIN_BATCH(7);
  49.    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
  50.    OUT_BATCH((depth_mt ? depth_mt->region->pitch - 1 : 0) |
  51.              (depthbuffer_format << 18) |
  52.              ((hiz ? 1 : 0) << 22) |
  53.              ((stencil_mt != NULL && ctx->Stencil._WriteEnabled) << 27) |
  54.              ((ctx->Depth.Mask != 0) << 28) |
  55.              (depth_surface_type << 29));
  56.  
  57.    if (depth_mt) {
  58.       OUT_RELOC(depth_mt->region->bo,
  59.                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  60.                 depth_offset);
  61.    } else {
  62.       OUT_BATCH(0);
  63.    }
  64.  
  65.    OUT_BATCH(((width + tile_x - 1) << 4) |
  66.              ((height + tile_y - 1) << 18));
  67.    OUT_BATCH(mocs);
  68.    OUT_BATCH(tile_x | (tile_y << 16));
  69.    OUT_BATCH(0);
  70.    ADVANCE_BATCH();
  71.  
  72.    if (!hiz) {
  73.       BEGIN_BATCH(3);
  74.       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
  75.       OUT_BATCH(0);
  76.       OUT_BATCH(0);
  77.       ADVANCE_BATCH();
  78.    } else {
  79.       struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_mt;
  80.       BEGIN_BATCH(3);
  81.       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
  82.       OUT_BATCH((mocs << 25) |
  83.                 (hiz_mt->region->pitch - 1));
  84.       OUT_RELOC(hiz_mt->region->bo,
  85.                 I915_GEM_DOMAIN_RENDER,
  86.                 I915_GEM_DOMAIN_RENDER,
  87.                 brw->depthstencil.hiz_offset);
  88.       ADVANCE_BATCH();
  89.    }
  90.  
  91.    if (stencil_mt == NULL) {
  92.       BEGIN_BATCH(3);
  93.       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
  94.       OUT_BATCH(0);
  95.       OUT_BATCH(0);
  96.       ADVANCE_BATCH();
  97.    } else {
  98.       const int enabled = brw->is_haswell ? HSW_STENCIL_ENABLED : 0;
  99.  
  100.       BEGIN_BATCH(3);
  101.       OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
  102.       /* The stencil buffer has quirky pitch requirements.  From the
  103.        * Sandybridge PRM, Volume 2 Part 1, page 329 (3DSTATE_STENCIL_BUFFER
  104.        * dword 1 bits 16:0 - Surface Pitch):
  105.        *
  106.        *    The pitch must be set to 2x the value computed based on width, as
  107.        *    the stencil buffer is stored with two rows interleaved.
  108.        *
  109.        * While the Ivybridge PRM lacks this comment, the BSpec contains the
  110.        * same text, and experiments indicate that this is necessary.
  111.        */
  112.       OUT_BATCH(enabled |
  113.                 mocs << 25 |
  114.                 (2 * stencil_mt->region->pitch - 1));
  115.       OUT_RELOC(stencil_mt->region->bo,
  116.                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  117.                 brw->depthstencil.stencil_offset);
  118.       ADVANCE_BATCH();
  119.    }
  120.  
  121.    BEGIN_BATCH(3);
  122.    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
  123.    OUT_BATCH(depth_mt ? depth_mt->depth_clear_value : 0);
  124.    OUT_BATCH(1);
  125.    ADVANCE_BATCH();
  126. }
  127.  
  128. /**
  129.  * \see brw_context.state.depth_region
  130.  */
  131. const struct brw_tracked_state gen7_depthbuffer = {
  132.    .dirty = {
  133.       .mesa = (_NEW_BUFFERS | _NEW_DEPTH | _NEW_STENCIL),
  134.       .brw = BRW_NEW_BATCH,
  135.       .cache = 0,
  136.    },
  137.    .emit = brw_emit_depthbuffer,
  138. };
  139.