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  1. /**************************************************************************
  2.  *
  3.  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  4.  * All Rights Reserved.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the
  8.  * "Software"), to deal in the Software without restriction, including
  9.  * without limitation the rights to use, copy, modify, merge, publish,
  10.  * distribute, sub license, and/or sell copies of the Software, and to
  11.  * permit persons to whom the Software is furnished to do so, subject to
  12.  * the following conditions:
  13.  *
  14.  * The above copyright notice and this permission notice (including the
  15.  * next paragraph) shall be included in all copies or substantial portions
  16.  * of the Software.
  17.  *
  18.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21.  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25.  *
  26.  **************************************************************************/
  27.  
  28.  
  29.  
  30. #include "main/glheader.h"
  31. #include "main/mtypes.h"
  32. #include "main/imports.h"
  33. #include "main/macros.h"
  34. #include "main/colormac.h"
  35. #include "main/renderbuffer.h"
  36. #include "main/framebuffer.h"
  37.  
  38. #include "tnl/tnl.h"
  39. #include "tnl/t_context.h"
  40. #include "tnl/t_vertex.h"
  41. #include "swrast_setup/swrast_setup.h"
  42.  
  43. #include "intel_batchbuffer.h"
  44. #include "intel_mipmap_tree.h"
  45. #include "intel_regions.h"
  46. #include "intel_tris.h"
  47. #include "intel_fbo.h"
  48. #include "intel_buffers.h"
  49.  
  50. #include "i915_reg.h"
  51. #include "i915_context.h"
  52.  
  53. static void
  54. i915_render_prevalidate(struct intel_context *intel)
  55. {
  56.    struct i915_context *i915 = i915_context(&intel->ctx);
  57.  
  58.    i915ValidateFragmentProgram(i915);
  59. }
  60.  
  61. static void
  62. i915_render_start(struct intel_context *intel)
  63. {
  64.    intel_prepare_render(intel);
  65. }
  66.  
  67.  
  68. static void
  69. i915_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
  70. {
  71.    struct i915_context *i915 = i915_context(&intel->ctx);
  72.    GLuint st1 = i915->state.Stipple[I915_STPREG_ST1];
  73.  
  74.    st1 &= ~ST1_ENABLE;
  75.  
  76.    switch (rprim) {
  77.    case GL_QUADS: /* from RASTERIZE(GL_QUADS) in t_dd_tritemp.h */
  78.    case GL_TRIANGLES:
  79.       if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
  80.          st1 |= ST1_ENABLE;
  81.       break;
  82.    case GL_LINES:
  83.    case GL_POINTS:
  84.    default:
  85.       break;
  86.    }
  87.  
  88.    i915->intel.reduced_primitive = rprim;
  89.  
  90.    if (st1 != i915->state.Stipple[I915_STPREG_ST1]) {
  91.       INTEL_FIREVERTICES(intel);
  92.  
  93.       I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
  94.       i915->state.Stipple[I915_STPREG_ST1] = st1;
  95.    }
  96. }
  97.  
  98.  
  99. /* Pull apart the vertex format registers and figure out how large a
  100.  * vertex is supposed to be.
  101.  */
  102. static bool
  103. i915_check_vertex_size(struct intel_context *intel, GLuint expected)
  104. {
  105.    struct i915_context *i915 = i915_context(&intel->ctx);
  106.    int lis2 = i915->state.Ctx[I915_CTXREG_LIS2];
  107.    int lis4 = i915->state.Ctx[I915_CTXREG_LIS4];
  108.    int i, sz = 0;
  109.  
  110.    switch (lis4 & S4_VFMT_XYZW_MASK) {
  111.    case S4_VFMT_XY:
  112.       sz = 2;
  113.       break;
  114.    case S4_VFMT_XYZ:
  115.       sz = 3;
  116.       break;
  117.    case S4_VFMT_XYW:
  118.       sz = 3;
  119.       break;
  120.    case S4_VFMT_XYZW:
  121.       sz = 4;
  122.       break;
  123.    default:
  124.       fprintf(stderr, "no xyzw specified\n");
  125.       return 0;
  126.    }
  127.  
  128.    if (lis4 & S4_VFMT_SPEC_FOG)
  129.       sz++;
  130.    if (lis4 & S4_VFMT_COLOR)
  131.       sz++;
  132.    if (lis4 & S4_VFMT_DEPTH_OFFSET)
  133.       sz++;
  134.    if (lis4 & S4_VFMT_POINT_WIDTH)
  135.       sz++;
  136.    if (lis4 & S4_VFMT_FOG_PARAM)
  137.       sz++;
  138.  
  139.    for (i = 0; i < 8; i++) {
  140.       switch (lis2 & S2_TEXCOORD_FMT0_MASK) {
  141.       case TEXCOORDFMT_2D:
  142.          sz += 2;
  143.          break;
  144.       case TEXCOORDFMT_3D:
  145.          sz += 3;
  146.          break;
  147.       case TEXCOORDFMT_4D:
  148.          sz += 4;
  149.          break;
  150.       case TEXCOORDFMT_1D:
  151.          sz += 1;
  152.          break;
  153.       case TEXCOORDFMT_2D_16:
  154.          sz += 1;
  155.          break;
  156.       case TEXCOORDFMT_4D_16:
  157.          sz += 2;
  158.          break;
  159.       case TEXCOORDFMT_NOT_PRESENT:
  160.          break;
  161.       default:
  162.          fprintf(stderr, "bad texcoord fmt %d\n", i);
  163.          return false;
  164.       }
  165.       lis2 >>= S2_TEXCOORD_FMT1_SHIFT;
  166.    }
  167.  
  168.    if (sz != expected)
  169.       fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
  170.  
  171.    return sz == expected;
  172. }
  173.  
  174.  
  175. static void
  176. i915_emit_invarient_state(struct intel_context *intel)
  177. {
  178.    BATCH_LOCALS;
  179.  
  180.    BEGIN_BATCH(17);
  181.  
  182.    OUT_BATCH(_3DSTATE_AA_CMD |
  183.              AA_LINE_ECAAR_WIDTH_ENABLE |
  184.              AA_LINE_ECAAR_WIDTH_1_0 |
  185.              AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
  186.  
  187.    OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
  188.    OUT_BATCH(0);
  189.  
  190.    OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
  191.    OUT_BATCH(0);
  192.  
  193.    OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
  194.    OUT_BATCH(0);
  195.  
  196.    /* Don't support texture crossbar yet */
  197.    OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
  198.              CSB_TCB(0, 0) |
  199.              CSB_TCB(1, 1) |
  200.              CSB_TCB(2, 2) |
  201.              CSB_TCB(3, 3) |
  202.              CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
  203.  
  204.    /* Need to initialize this to zero.
  205.     */
  206.    OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0));
  207.    OUT_BATCH(0);
  208.  
  209.    /* XXX: Use this */
  210.    OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
  211.  
  212.    OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
  213.    OUT_BATCH(0);
  214.    OUT_BATCH(0);
  215.  
  216.    OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
  217.  
  218.    OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0);       /* disable indirect state */
  219.    OUT_BATCH(0);
  220.  
  221.    ADVANCE_BATCH();
  222. }
  223.  
  224.  
  225. #define emit(intel, state, size )                    \
  226.    intel_batchbuffer_data(intel, state, size)
  227.  
  228. static GLuint
  229. get_dirty(struct i915_hw_state *state)
  230. {
  231.    GLuint dirty;
  232.  
  233.    /* Workaround the multitex hang - if one texture unit state is
  234.     * modified, emit all texture units.
  235.     */
  236.    dirty = state->active & ~state->emitted;
  237.    if (dirty & I915_UPLOAD_TEX_ALL)
  238.       state->emitted &= ~I915_UPLOAD_TEX_ALL;
  239.    dirty = state->active & ~state->emitted;
  240.    return dirty;
  241. }
  242.  
  243.  
  244. static GLuint
  245. get_state_size(struct i915_hw_state *state)
  246. {
  247.    GLuint dirty = get_dirty(state);
  248.    GLuint i;
  249.    GLuint sz = 0;
  250.  
  251.    if (dirty & I915_UPLOAD_INVARIENT)
  252.       sz += 30 * 4;
  253.  
  254.    if (dirty & I915_UPLOAD_RASTER_RULES)
  255.       sz += sizeof(state->RasterRules);
  256.  
  257.    if (dirty & I915_UPLOAD_CTX)
  258.       sz += sizeof(state->Ctx);
  259.  
  260.    if (dirty & I915_UPLOAD_BLEND)
  261.       sz += sizeof(state->Blend);
  262.  
  263.    if (dirty & I915_UPLOAD_BUFFERS)
  264.       sz += sizeof(state->Buffer);
  265.  
  266.    if (dirty & I915_UPLOAD_STIPPLE)
  267.       sz += sizeof(state->Stipple);
  268.  
  269.    if (dirty & I915_UPLOAD_TEX_ALL) {
  270.       int nr = 0;
  271.       for (i = 0; i < I915_TEX_UNITS; i++)
  272.          if (dirty & I915_UPLOAD_TEX(i))
  273.             nr++;
  274.  
  275.       sz += (2 + nr * 3) * sizeof(GLuint) * 2;
  276.    }
  277.  
  278.    if (dirty & I915_UPLOAD_CONSTANTS)
  279.       sz += state->ConstantSize * sizeof(GLuint);
  280.  
  281.    if (dirty & I915_UPLOAD_PROGRAM)
  282.       sz += state->ProgramSize * sizeof(GLuint);
  283.  
  284.    return sz;
  285. }
  286.  
  287. /* Push the state into the sarea and/or texture memory.
  288.  */
  289. static void
  290. i915_emit_state(struct intel_context *intel)
  291. {
  292.    struct i915_context *i915 = i915_context(&intel->ctx);
  293.    struct i915_hw_state *state = &i915->state;
  294.    int i, count, aper_count;
  295.    GLuint dirty;
  296.    drm_intel_bo *aper_array[3 + I915_TEX_UNITS];
  297.    GET_CURRENT_CONTEXT(ctx);
  298.    BATCH_LOCALS;
  299.  
  300.    /* We don't hold the lock at this point, so want to make sure that
  301.     * there won't be a buffer wrap between the state emits and the primitive
  302.     * emit header.
  303.     *
  304.     * It might be better to talk about explicit places where
  305.     * scheduling is allowed, rather than assume that it is whenever a
  306.     * batchbuffer fills up.
  307.     */
  308.    intel_batchbuffer_require_space(intel,
  309.                                    get_state_size(state) +
  310.                                    INTEL_PRIM_EMIT_SIZE);
  311.    count = 0;
  312.  again:
  313.    if (intel->batch.bo == NULL) {
  314.       _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
  315.       assert(0);
  316.    }
  317.    aper_count = 0;
  318.    dirty = get_dirty(state);
  319.  
  320.    aper_array[aper_count++] = intel->batch.bo;
  321.    if (dirty & I915_UPLOAD_BUFFERS) {
  322.       if (state->draw_region)
  323.          aper_array[aper_count++] = state->draw_region->bo;
  324.       if (state->depth_region)
  325.          aper_array[aper_count++] = state->depth_region->bo;
  326.    }
  327.  
  328.    if (dirty & I915_UPLOAD_TEX_ALL) {
  329.       for (i = 0; i < I915_TEX_UNITS; i++) {
  330.          if (dirty & I915_UPLOAD_TEX(i)) {
  331.             if (state->tex_buffer[i]) {
  332.                aper_array[aper_count++] = state->tex_buffer[i];
  333.             }
  334.          }
  335.       }
  336.    }
  337.  
  338.    if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) {
  339.        if (count == 0) {
  340.            count++;
  341.            intel_batchbuffer_flush(intel);
  342.            goto again;
  343.        } else {
  344.            _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
  345.            assert(0);
  346.        }
  347.    }
  348.  
  349.    /* work out list of buffers to emit */
  350.    
  351.    /* Do this here as we may have flushed the batchbuffer above,
  352.     * causing more state to be dirty!
  353.     */
  354.    dirty = get_dirty(state);
  355.    state->emitted |= dirty;
  356.    assert(get_dirty(state) == 0);
  357.  
  358.    if (INTEL_DEBUG & DEBUG_STATE)
  359.       fprintf(stderr, "%s dirty: %x\n", __FUNCTION__, dirty);
  360.  
  361.    if (dirty & I915_UPLOAD_INVARIENT) {
  362.       if (INTEL_DEBUG & DEBUG_STATE)
  363.          fprintf(stderr, "I915_UPLOAD_INVARIENT:\n");
  364.       i915_emit_invarient_state(intel);
  365.    }
  366.  
  367.    if (dirty & I915_UPLOAD_RASTER_RULES) {
  368.       if (INTEL_DEBUG & DEBUG_STATE)
  369.          fprintf(stderr, "I915_UPLOAD_RASTER_RULES:\n");
  370.       emit(intel, state->RasterRules, sizeof(state->RasterRules));
  371.    }
  372.  
  373.    if (dirty & I915_UPLOAD_CTX) {
  374.       if (INTEL_DEBUG & DEBUG_STATE)
  375.          fprintf(stderr, "I915_UPLOAD_CTX:\n");
  376.  
  377.       emit(intel, state->Ctx, sizeof(state->Ctx));
  378.    }
  379.  
  380.    if (dirty & I915_UPLOAD_BLEND) {
  381.       if (INTEL_DEBUG & DEBUG_STATE)
  382.          fprintf(stderr, "I915_UPLOAD_BLEND:\n");
  383.  
  384.       emit(intel, state->Blend, sizeof(state->Blend));
  385.    }
  386.  
  387.    if (dirty & I915_UPLOAD_BUFFERS) {
  388.       GLuint count;
  389.  
  390.       if (INTEL_DEBUG & DEBUG_STATE)
  391.          fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
  392.  
  393.       count = 17;
  394.       if (state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP)
  395.          count++;
  396.  
  397.       BEGIN_BATCH(count);
  398.       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
  399.       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
  400.       if (state->draw_region) {
  401.          OUT_RELOC(state->draw_region->bo,
  402.                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
  403.       } else {
  404.          OUT_BATCH(0);
  405.       }
  406.  
  407.       OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
  408.       OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
  409.       if (state->depth_region) {
  410.          OUT_RELOC(state->depth_region->bo,
  411.                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
  412.       } else {
  413.          OUT_BATCH(0);
  414.       }
  415.  
  416.       OUT_BATCH(state->Buffer[I915_DESTREG_DV0]);
  417.       OUT_BATCH(state->Buffer[I915_DESTREG_DV1]);
  418.       OUT_BATCH(state->Buffer[I915_DESTREG_SENABLE]);
  419.       OUT_BATCH(state->Buffer[I915_DESTREG_SR0]);
  420.       OUT_BATCH(state->Buffer[I915_DESTREG_SR1]);
  421.       OUT_BATCH(state->Buffer[I915_DESTREG_SR2]);
  422.  
  423.       if (state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP)
  424.          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]);
  425.       OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]);
  426.       OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]);
  427.       OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]);
  428.       OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]);
  429.       OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]);
  430.  
  431.       ADVANCE_BATCH();
  432.    }
  433.  
  434.    if (dirty & I915_UPLOAD_STIPPLE) {
  435.       if (INTEL_DEBUG & DEBUG_STATE)
  436.          fprintf(stderr, "I915_UPLOAD_STIPPLE:\n");
  437.       emit(intel, state->Stipple, sizeof(state->Stipple));
  438.    }
  439.  
  440.    /* Combine all the dirty texture state into a single command to
  441.     * avoid lockups on I915 hardware.
  442.     */
  443.    if (dirty & I915_UPLOAD_TEX_ALL) {
  444.       int nr = 0;
  445.       GLuint unwind;
  446.  
  447.       for (i = 0; i < I915_TEX_UNITS; i++)
  448.          if (dirty & I915_UPLOAD_TEX(i))
  449.             nr++;
  450.  
  451.       BEGIN_BATCH(2 + nr * 3);
  452.       OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
  453.       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
  454.       for (i = 0; i < I915_TEX_UNITS; i++)
  455.          if (dirty & I915_UPLOAD_TEX(i)) {
  456.             OUT_RELOC(state->tex_buffer[i],
  457.                       I915_GEM_DOMAIN_SAMPLER, 0,
  458.                       state->tex_offset[i]);
  459.  
  460.             OUT_BATCH(state->Tex[i][I915_TEXREG_MS3]);
  461.             OUT_BATCH(state->Tex[i][I915_TEXREG_MS4]);
  462.          }
  463.       ADVANCE_BATCH();
  464.  
  465.       unwind = intel->batch.used;
  466.       BEGIN_BATCH(2 + nr * 3);
  467.       OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr));
  468.       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
  469.       for (i = 0; i < I915_TEX_UNITS; i++)
  470.          if (dirty & I915_UPLOAD_TEX(i)) {
  471.             OUT_BATCH(state->Tex[i][I915_TEXREG_SS2]);
  472.             OUT_BATCH(state->Tex[i][I915_TEXREG_SS3]);
  473.             OUT_BATCH(state->Tex[i][I915_TEXREG_SS4]);
  474.          }
  475.       ADVANCE_BATCH();
  476.       if (i915->last_sampler &&
  477.           memcmp(intel->batch.map + i915->last_sampler,
  478.                  intel->batch.map + unwind,
  479.                  (2 + nr*3)*sizeof(int)) == 0)
  480.           intel->batch.used = unwind;
  481.       else
  482.           i915->last_sampler = unwind;
  483.    }
  484.  
  485.    if (dirty & I915_UPLOAD_CONSTANTS) {
  486.       if (INTEL_DEBUG & DEBUG_STATE)
  487.          fprintf(stderr, "I915_UPLOAD_CONSTANTS:\n");
  488.       emit(intel, state->Constant, state->ConstantSize * sizeof(GLuint));
  489.    }
  490.  
  491.    if (dirty & I915_UPLOAD_PROGRAM) {
  492.       if (state->ProgramSize) {
  493.          if (INTEL_DEBUG & DEBUG_STATE)
  494.             fprintf(stderr, "I915_UPLOAD_PROGRAM:\n");
  495.  
  496.          assert((state->Program[0] & 0x1ff) + 2 == state->ProgramSize);
  497.  
  498.          emit(intel, state->Program, state->ProgramSize * sizeof(GLuint));
  499.          if (INTEL_DEBUG & DEBUG_STATE)
  500.             i915_disassemble_program(state->Program, state->ProgramSize);
  501.       }
  502.    }
  503.  
  504.    assert(get_dirty(state) == 0);
  505. }
  506.  
  507. static void
  508. i915_destroy_context(struct intel_context *intel)
  509. {
  510.    GLuint i;
  511.    struct i915_context *i915 = i915_context(&intel->ctx);
  512.  
  513.    intel_region_release(&i915->state.draw_region);
  514.    intel_region_release(&i915->state.depth_region);
  515.  
  516.    for (i = 0; i < I915_TEX_UNITS; i++) {
  517.       if (i915->state.tex_buffer[i] != NULL) {
  518.          drm_intel_bo_unreference(i915->state.tex_buffer[i]);
  519.          i915->state.tex_buffer[i] = NULL;
  520.       }
  521.    }
  522.  
  523.    _tnl_free_vertices(&intel->ctx);
  524. }
  525.  
  526. void
  527. i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region,
  528.                              uint32_t buffer_id)
  529. {
  530.    state[0] = _3DSTATE_BUF_INFO_CMD;
  531.    state[1] = buffer_id;
  532.  
  533.    if (region != NULL) {
  534.       state[1] |= BUF_3D_PITCH(region->pitch);
  535.  
  536.       if (region->tiling != I915_TILING_NONE) {
  537.          state[1] |= BUF_3D_TILED_SURFACE;
  538.          if (region->tiling == I915_TILING_Y)
  539.             state[1] |= BUF_3D_TILE_WALK_Y;
  540.       }
  541.    } else {
  542.       /* Fill in a default pitch, since 0 is invalid.  We'll be
  543.        * setting the buffer offset to 0 and not referencing the
  544.        * buffer, so the pitch could really be any valid value.
  545.        */
  546.       state[1] |= BUF_3D_PITCH(4096);
  547.    }
  548. }
  549.  
  550. static uint32_t i915_render_target_format_for_mesa_format[MESA_FORMAT_COUNT] =
  551. {
  552.    [MESA_FORMAT_ARGB8888] = DV_PF_8888,
  553.    [MESA_FORMAT_XRGB8888] = DV_PF_8888,
  554.    [MESA_FORMAT_RGB565] = DV_PF_565 | DITHER_FULL_ALWAYS,
  555.    [MESA_FORMAT_ARGB1555] = DV_PF_1555 | DITHER_FULL_ALWAYS,
  556.    [MESA_FORMAT_ARGB4444] = DV_PF_4444 | DITHER_FULL_ALWAYS,
  557. };
  558.  
  559. static bool
  560. i915_render_target_supported(struct intel_context *intel,
  561.                              struct gl_renderbuffer *rb)
  562. {
  563.    gl_format format = rb->Format;
  564.  
  565.    if (format == MESA_FORMAT_S8_Z24 ||
  566.        format == MESA_FORMAT_X8_Z24 ||
  567.        format == MESA_FORMAT_Z16) {
  568.       return true;
  569.    }
  570.  
  571.    return i915_render_target_format_for_mesa_format[format] != 0;
  572. }
  573.  
  574. static void
  575. i915_set_draw_region(struct intel_context *intel,
  576.                      struct intel_region *color_regions[],
  577.                      struct intel_region *depth_region,
  578.                      GLuint num_regions)
  579. {
  580.    struct i915_context *i915 = i915_context(&intel->ctx);
  581.    struct gl_context *ctx = &intel->ctx;
  582.    struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
  583.    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
  584.    struct gl_renderbuffer *drb;
  585.    struct intel_renderbuffer *idrb = NULL;
  586.    GLuint value;
  587.    struct i915_hw_state *state = &i915->state;
  588.    uint32_t draw_x, draw_y, draw_offset;
  589.  
  590.    if (state->draw_region != color_regions[0]) {
  591.       intel_region_reference(&state->draw_region, color_regions[0]);
  592.    }
  593.    if (state->depth_region != depth_region) {
  594.       intel_region_reference(&state->depth_region, depth_region);
  595.    }
  596.  
  597.    /*
  598.     * Set stride/cpp values
  599.     */
  600.    i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_CBUFADDR0],
  601.                                 color_regions[0], BUF_3D_ID_COLOR_BACK);
  602.  
  603.    i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_DBUFADDR0],
  604.                                 depth_region, BUF_3D_ID_DEPTH);
  605.  
  606.    /*
  607.     * Compute/set I915_DESTREG_DV1 value
  608.     */
  609.    value = (DSTORG_HORT_BIAS(0x8) |     /* .5 */
  610.             DSTORG_VERT_BIAS(0x8) |     /* .5 */
  611.             LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL);
  612.    if (irb != NULL) {
  613.       value |= i915_render_target_format_for_mesa_format[intel_rb_format(irb)];
  614.    } else {
  615.       value |= DV_PF_8888;
  616.    }
  617.  
  618.    /* This isn't quite safe, thus being hidden behind an option.  When changing
  619.     * the value of this bit, the pipeline needs to be MI_FLUSHed.  And it
  620.     * can only be set when a depth buffer is already defined.
  621.     */
  622.    if (intel->is_945 && intel->use_early_z &&
  623.        depth_region->tiling != I915_TILING_NONE)
  624.       value |= CLASSIC_EARLY_DEPTH;
  625.  
  626.    if (depth_region && depth_region->cpp == 4) {
  627.       value |= DEPTH_FRMT_24_FIXED_8_OTHER;
  628.    }
  629.    else {
  630.       value |= DEPTH_FRMT_16_FIXED;
  631.    }
  632.    state->Buffer[I915_DESTREG_DV1] = value;
  633.  
  634.    drb = ctx->DrawBuffer->Attachment[BUFFER_DEPTH].Renderbuffer;
  635.    if (!drb)
  636.       drb = ctx->DrawBuffer->Attachment[BUFFER_STENCIL].Renderbuffer;
  637.  
  638.    if (drb)
  639.       idrb = intel_renderbuffer(drb);
  640.  
  641.    /* We set up the drawing rectangle to be offset into the color
  642.     * region's location in the miptree.  If it doesn't match with
  643.     * depth's offsets, we can't render to it.
  644.     *
  645.     * (Well, not actually true -- the hw grew a bit to let depth's
  646.     * offset get forced to 0,0.  We may want to use that if people are
  647.     * hitting that case.  Also, some configurations may be supportable
  648.     * by tweaking the start offset of the buffers around, which we
  649.     * can't do in general due to tiling)
  650.     */
  651.    FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
  652.             idrb && irb && (idrb->draw_x != irb->draw_x ||
  653.                             idrb->draw_y != irb->draw_y));
  654.  
  655.    if (irb) {
  656.       draw_x = irb->draw_x;
  657.       draw_y = irb->draw_y;
  658.    } else if (idrb) {
  659.       draw_x = idrb->draw_x;
  660.       draw_y = idrb->draw_y;
  661.    } else {
  662.       draw_x = 0;
  663.       draw_y = 0;
  664.    }
  665.  
  666.    draw_offset = (draw_y << 16) | draw_x;
  667.  
  668.    FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
  669.             (ctx->DrawBuffer->Width + draw_x > 2048) ||
  670.             (ctx->DrawBuffer->Height + draw_y > 2048));
  671.    /* When changing drawing rectangle offset, an MI_FLUSH is first required. */
  672.    if (draw_offset != i915->last_draw_offset) {
  673.       state->Buffer[I915_DESTREG_DRAWRECT0] = MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE;
  674.       i915->last_draw_offset = draw_offset;
  675.    } else
  676.       state->Buffer[I915_DESTREG_DRAWRECT0] = MI_NOOP;
  677.  
  678.    state->Buffer[I915_DESTREG_DRAWRECT1] = _3DSTATE_DRAWRECT_INFO;
  679.    state->Buffer[I915_DESTREG_DRAWRECT2] = 0;
  680.    state->Buffer[I915_DESTREG_DRAWRECT3] = draw_offset;
  681.    state->Buffer[I915_DESTREG_DRAWRECT4] =
  682.       ((ctx->DrawBuffer->Width + draw_x - 1) & 0xffff) |
  683.       ((ctx->DrawBuffer->Height + draw_y - 1) << 16);
  684.    state->Buffer[I915_DESTREG_DRAWRECT5] = draw_offset;
  685.  
  686.    I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
  687. }
  688.  
  689. static void
  690. i915_update_color_write_enable(struct i915_context *i915, bool enable)
  691. {
  692.    uint32_t dw = i915->state.Ctx[I915_CTXREG_LIS6];
  693.    if (enable)
  694.       dw |= S6_COLOR_WRITE_ENABLE;
  695.    else
  696.       dw &= ~S6_COLOR_WRITE_ENABLE;
  697.    if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
  698.       I915_STATECHANGE(i915, I915_UPLOAD_CTX);
  699.       i915->state.Ctx[I915_CTXREG_LIS6] = dw;
  700.    }
  701. }
  702.  
  703. /**
  704.  * Update the hardware state for drawing into a window or framebuffer object.
  705.  *
  706.  * Called by glDrawBuffer, glBindFramebufferEXT, MakeCurrent, and other
  707.  * places within the driver.
  708.  *
  709.  * Basically, this needs to be called any time the current framebuffer
  710.  * changes, the renderbuffers change, or we need to draw into different
  711.  * color buffers.
  712.  */
  713. static void
  714. i915_update_draw_buffer(struct intel_context *intel)
  715. {
  716.    struct i915_context *i915 = (struct i915_context *)intel;
  717.    struct gl_context *ctx = &intel->ctx;
  718.    struct gl_framebuffer *fb = ctx->DrawBuffer;
  719.    struct intel_region *colorRegion = NULL, *depthRegion = NULL;
  720.    struct intel_renderbuffer *irbDepth = NULL, *irbStencil = NULL;
  721.  
  722.    if (!fb) {
  723.       /* this can happen during the initial context initialization */
  724.       return;
  725.    }
  726.  
  727.    irbDepth = intel_get_renderbuffer(fb, BUFFER_DEPTH);
  728.    irbStencil = intel_get_renderbuffer(fb, BUFFER_STENCIL);
  729.  
  730.    /* Do this here, not core Mesa, since this function is called from
  731.     * many places within the driver.
  732.     */
  733.    if (ctx->NewState & _NEW_BUFFERS) {
  734.       /* this updates the DrawBuffer->_NumColorDrawBuffers fields, etc */
  735.       _mesa_update_framebuffer(ctx);
  736.       /* this updates the DrawBuffer's Width/Height if it's a FBO */
  737.       _mesa_update_draw_buffer_bounds(ctx);
  738.    }
  739.  
  740.    if (fb->_Status != GL_FRAMEBUFFER_COMPLETE_EXT) {
  741.       /* this may occur when we're called by glBindFrameBuffer() during
  742.        * the process of someone setting up renderbuffers, etc.
  743.        */
  744.       /*_mesa_debug(ctx, "DrawBuffer: incomplete user FBO\n");*/
  745.       return;
  746.    }
  747.  
  748.    /* How many color buffers are we drawing into?
  749.     *
  750.     * If there is more than one drawbuffer (GL_FRONT_AND_BACK), or the
  751.     * drawbuffers are too big, we have to fallback to software.
  752.     */
  753.    if ((fb->Width > ctx->Const.MaxRenderbufferSize)
  754.        || (fb->Height > ctx->Const.MaxRenderbufferSize)) {
  755.       FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, true);
  756.    } else if (fb->_NumColorDrawBuffers > 1) {
  757.       FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, true);
  758.    } else {
  759.       struct intel_renderbuffer *irb;
  760.       irb = intel_renderbuffer(fb->_ColorDrawBuffers[0]);
  761.       colorRegion = (irb && irb->mt) ? irb->mt->region : NULL;
  762.       FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, false);
  763.    }
  764.  
  765.    /* Check for depth fallback. */
  766.    if (irbDepth && irbDepth->mt) {
  767.       FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, false);
  768.       depthRegion = irbDepth->mt->region;
  769.    } else if (irbDepth && !irbDepth->mt) {
  770.       FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, true);
  771.       depthRegion = NULL;
  772.    } else { /* !irbDepth */
  773.       /* No fallback is needed because there is no depth buffer. */
  774.       FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, false);
  775.       depthRegion = NULL;
  776.    }
  777.  
  778.    /* Check for stencil fallback. */
  779.    if (irbStencil && irbStencil->mt) {
  780.       assert(intel_rb_format(irbStencil) == MESA_FORMAT_S8_Z24);
  781.       FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, false);
  782.    } else if (irbStencil && !irbStencil->mt) {
  783.       FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, true);
  784.    } else { /* !irbStencil */
  785.       /* No fallback is needed because there is no stencil buffer. */
  786.       FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, false);
  787.    }
  788.  
  789.    /* If we have a (packed) stencil buffer attached but no depth buffer,
  790.     * we still need to set up the shared depth/stencil state so we can use it.
  791.     */
  792.    if (depthRegion == NULL && irbStencil && irbStencil->mt
  793.        && intel_rb_format(irbStencil) == MESA_FORMAT_S8_Z24) {
  794.       depthRegion = irbStencil->mt->region;
  795.    }
  796.  
  797.    /*
  798.     * Update depth and stencil test state
  799.     */
  800.    ctx->Driver.Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
  801.    ctx->Driver.Enable(ctx, GL_STENCIL_TEST, ctx->Stencil.Enabled);
  802.  
  803.    i915_update_color_write_enable(i915, colorRegion != NULL);
  804.  
  805.    intel->vtbl.set_draw_region(intel, &colorRegion, depthRegion,
  806.                                fb->_NumColorDrawBuffers);
  807.    intel->NewGLState |= _NEW_BUFFERS;
  808.  
  809.    /* update viewport since it depends on window size */
  810.    intelCalcViewport(ctx);
  811.  
  812.    /* Set state we know depends on drawable parameters:
  813.     */
  814.    ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y,
  815.                        ctx->Scissor.Width, ctx->Scissor.Height);
  816.    ctx->Driver.DepthRange(ctx, ctx->Viewport.Near, ctx->Viewport.Far);
  817.  
  818.    /* Update culling direction which changes depending on the
  819.     * orientation of the buffer:
  820.     */
  821.    ctx->Driver.FrontFace(ctx, ctx->Polygon.FrontFace);
  822. }
  823.  
  824. static void
  825. i915_new_batch(struct intel_context *intel)
  826. {
  827.    struct i915_context *i915 = i915_context(&intel->ctx);
  828.  
  829.    /* Mark all state as needing to be emitted when starting a new batchbuffer.
  830.     * Using hardware contexts would be an alternative, but they have some
  831.     * difficulties associated with them (physical address requirements).
  832.     */
  833.    i915->state.emitted = 0;
  834.    i915->last_draw_offset = 0;
  835.    i915->last_sampler = 0;
  836.  
  837.    i915->current_vb_bo = NULL;
  838.    i915->current_vertex_size = 0;
  839. }
  840.  
  841. static void
  842. i915_assert_not_dirty( struct intel_context *intel )
  843. {
  844.    struct i915_context *i915 = i915_context(&intel->ctx);
  845.    GLuint dirty = get_dirty(&i915->state);
  846.    assert(!dirty);
  847.    (void) dirty;
  848. }
  849.  
  850. static void
  851. i915_invalidate_state(struct intel_context *intel, GLuint new_state)
  852. {
  853.    struct gl_context *ctx = &intel->ctx;
  854.  
  855.    _swsetup_InvalidateState(ctx, new_state);
  856.    _tnl_InvalidateState(ctx, new_state);
  857.    _tnl_invalidate_vertex_state(ctx, new_state);
  858. }
  859.  
  860. void
  861. i915InitVtbl(struct i915_context *i915)
  862. {
  863.    i915->intel.vtbl.check_vertex_size = i915_check_vertex_size;
  864.    i915->intel.vtbl.destroy = i915_destroy_context;
  865.    i915->intel.vtbl.emit_state = i915_emit_state;
  866.    i915->intel.vtbl.new_batch = i915_new_batch;
  867.    i915->intel.vtbl.reduced_primitive_state = i915_reduced_primitive_state;
  868.    i915->intel.vtbl.render_start = i915_render_start;
  869.    i915->intel.vtbl.render_prevalidate = i915_render_prevalidate;
  870.    i915->intel.vtbl.set_draw_region = i915_set_draw_region;
  871.    i915->intel.vtbl.update_draw_buffer = i915_update_draw_buffer;
  872.    i915->intel.vtbl.update_texture_state = i915UpdateTextureState;
  873.    i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty;
  874.    i915->intel.vtbl.finish_batch = intel_finish_vb;
  875.    i915->intel.vtbl.invalidate_state = i915_invalidate_state;
  876.    i915->intel.vtbl.render_target_supported = i915_render_target_supported;
  877. }
  878.