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  1. /*
  2.  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
  3.  * All Rights Reserved.
  4.  *
  5.  * Permission is hereby granted, free of charge, to any person obtaining
  6.  * a copy of this software and associated documentation files (the
  7.  * "Software"), to deal in the Software without restriction, including
  8.  * without limitation the rights to use, copy, modify, merge, publish,
  9.  * distribute, sub license, and/or sell copies of the Software, and to
  10.  * permit persons to whom the Software is furnished to do so, subject to
  11.  * the following conditions:
  12.  *
  13.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  14.  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  15.  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  16.  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  17.  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  20.  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  21.  *
  22.  * The above copyright notice and this permission notice (including the
  23.  * next paragraph) shall be included in all copies or substantial portions
  24.  * of the Software.
  25.  */
  26.  
  27. #define _FILE_OFFSET_BITS 64
  28. #include "radeon_drm_cs.h"
  29.  
  30. #include "util/u_hash_table.h"
  31. #include "util/u_memory.h"
  32. #include "util/u_simple_list.h"
  33. #include "util/u_double_list.h"
  34. #include "os/os_thread.h"
  35. #include "os/os_mman.h"
  36. #include "os/os_time.h"
  37.  
  38. #include "state_tracker/drm_driver.h"
  39.  
  40. #include <sys/ioctl.h>
  41. #include <xf86drm.h>
  42. #include <errno.h>
  43.  
  44. /*
  45.  * this are copy from radeon_drm, once an updated libdrm is released
  46.  * we should bump configure.ac requirement for it and remove the following
  47.  * field
  48.  */
  49. #define RADEON_BO_FLAGS_MACRO_TILE  1
  50. #define RADEON_BO_FLAGS_MICRO_TILE  2
  51. #define RADEON_BO_FLAGS_MICRO_TILE_SQUARE 0x20
  52.  
  53. #ifndef DRM_RADEON_GEM_WAIT
  54. #define DRM_RADEON_GEM_WAIT     0x2b
  55.  
  56. #define RADEON_GEM_NO_WAIT      0x1
  57. #define RADEON_GEM_USAGE_READ   0x2
  58. #define RADEON_GEM_USAGE_WRITE  0x4
  59.  
  60. struct drm_radeon_gem_wait {
  61.     uint32_t    handle;
  62.     uint32_t    flags;  /* one of RADEON_GEM_* */
  63. };
  64.  
  65. #endif
  66.  
  67. #ifndef RADEON_VA_MAP
  68.  
  69. #define RADEON_VA_MAP               1
  70. #define RADEON_VA_UNMAP             2
  71.  
  72. #define RADEON_VA_RESULT_OK         0
  73. #define RADEON_VA_RESULT_ERROR      1
  74. #define RADEON_VA_RESULT_VA_EXIST   2
  75.  
  76. #define RADEON_VM_PAGE_VALID        (1 << 0)
  77. #define RADEON_VM_PAGE_READABLE     (1 << 1)
  78. #define RADEON_VM_PAGE_WRITEABLE    (1 << 2)
  79. #define RADEON_VM_PAGE_SYSTEM       (1 << 3)
  80. #define RADEON_VM_PAGE_SNOOPED      (1 << 4)
  81.  
  82. struct drm_radeon_gem_va {
  83.     uint32_t    handle;
  84.     uint32_t    operation;
  85.     uint32_t    vm_id;
  86.     uint32_t    flags;
  87.     uint64_t    offset;
  88. };
  89.  
  90. #define DRM_RADEON_GEM_VA   0x2b
  91. #endif
  92.  
  93.  
  94.  
  95. extern const struct pb_vtbl radeon_bo_vtbl;
  96.  
  97.  
  98. static INLINE struct radeon_bo *radeon_bo(struct pb_buffer *bo)
  99. {
  100.     assert(bo->vtbl == &radeon_bo_vtbl);
  101.     return (struct radeon_bo *)bo;
  102. }
  103.  
  104. struct radeon_bo_va_hole {
  105.     struct list_head list;
  106.     uint64_t         offset;
  107.     uint64_t         size;
  108. };
  109.  
  110. struct radeon_bomgr {
  111.     /* Base class. */
  112.     struct pb_manager base;
  113.  
  114.     /* Winsys. */
  115.     struct radeon_drm_winsys *rws;
  116.  
  117.     /* List of buffer handles and its mutex. */
  118.     struct util_hash_table *bo_handles;
  119.     pipe_mutex bo_handles_mutex;
  120.     pipe_mutex bo_va_mutex;
  121.  
  122.     /* is virtual address supported */
  123.     bool va;
  124.     uint64_t va_offset;
  125.     struct list_head va_holes;
  126. };
  127.  
  128. static INLINE struct radeon_bomgr *radeon_bomgr(struct pb_manager *mgr)
  129. {
  130.     return (struct radeon_bomgr *)mgr;
  131. }
  132.  
  133. static struct radeon_bo *get_radeon_bo(struct pb_buffer *_buf)
  134. {
  135.     struct radeon_bo *bo = NULL;
  136.  
  137.     if (_buf->vtbl == &radeon_bo_vtbl) {
  138.         bo = radeon_bo(_buf);
  139.     } else {
  140.         struct pb_buffer *base_buf;
  141.         pb_size offset;
  142.         pb_get_base_buffer(_buf, &base_buf, &offset);
  143.  
  144.         if (base_buf->vtbl == &radeon_bo_vtbl)
  145.             bo = radeon_bo(base_buf);
  146.     }
  147.  
  148.     return bo;
  149. }
  150.  
  151. static void radeon_bo_wait(struct pb_buffer *_buf, enum radeon_bo_usage usage)
  152. {
  153.     struct radeon_bo *bo = get_radeon_bo(_buf);
  154.  
  155.     while (p_atomic_read(&bo->num_active_ioctls)) {
  156.         sched_yield();
  157.     }
  158.  
  159.     /* XXX use this when it's ready */
  160.     /*if (bo->rws->info.drm_minor >= 12) {
  161.         struct drm_radeon_gem_wait args = {};
  162.         args.handle = bo->handle;
  163.         args.flags = usage;
  164.         while (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT,
  165.                                    &args, sizeof(args)) == -EBUSY);
  166.     } else*/ {
  167.         struct drm_radeon_gem_wait_idle args;
  168.         memset(&args, 0, sizeof(args));
  169.         args.handle = bo->handle;
  170.         while (drmCommandWrite(bo->rws->fd, DRM_RADEON_GEM_WAIT_IDLE,
  171.                                    &args, sizeof(args)) == -EBUSY);
  172.     }
  173. }
  174.  
  175. static boolean radeon_bo_is_busy(struct pb_buffer *_buf,
  176.                                  enum radeon_bo_usage usage)
  177. {
  178.     struct radeon_bo *bo = get_radeon_bo(_buf);
  179.  
  180.     if (p_atomic_read(&bo->num_active_ioctls)) {
  181.         return TRUE;
  182.     }
  183.  
  184.     /* XXX use this when it's ready */
  185.     /*if (bo->rws->info.drm_minor >= 12) {
  186.         struct drm_radeon_gem_wait args = {};
  187.         args.handle = bo->handle;
  188.         args.flags = usage | RADEON_GEM_NO_WAIT;
  189.         return drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT,
  190.                                    &args, sizeof(args)) != 0;
  191.     } else*/ {
  192.         struct drm_radeon_gem_busy args;
  193.         memset(&args, 0, sizeof(args));
  194.         args.handle = bo->handle;
  195.         return drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_BUSY,
  196.                                    &args, sizeof(args)) != 0;
  197.     }
  198. }
  199.  
  200. static uint64_t radeon_bomgr_find_va(struct radeon_bomgr *mgr, uint64_t size, uint64_t alignment)
  201. {
  202.     struct radeon_bo_va_hole *hole, *n;
  203.     uint64_t offset = 0, waste = 0;
  204.  
  205.     pipe_mutex_lock(mgr->bo_va_mutex);
  206.     /* first look for a hole */
  207.     LIST_FOR_EACH_ENTRY_SAFE(hole, n, &mgr->va_holes, list) {
  208.         offset = hole->offset;
  209.         waste = 0;
  210.         if (alignment) {
  211.             waste = offset % alignment;
  212.             waste = waste ? alignment - waste : 0;
  213.         }
  214.         offset += waste;
  215.         if (offset >= (hole->offset + hole->size)) {
  216.             continue;
  217.         }
  218.         if (!waste && hole->size == size) {
  219.             offset = hole->offset;
  220.             list_del(&hole->list);
  221.             FREE(hole);
  222.             pipe_mutex_unlock(mgr->bo_va_mutex);
  223.             return offset;
  224.         }
  225.         if ((hole->size - waste) > size) {
  226.             if (waste) {
  227.                 n = CALLOC_STRUCT(radeon_bo_va_hole);
  228.                 n->size = waste;
  229.                 n->offset = hole->offset;
  230.                 list_add(&n->list, &hole->list);
  231.             }
  232.             hole->size -= (size + waste);
  233.             hole->offset += size + waste;
  234.             pipe_mutex_unlock(mgr->bo_va_mutex);
  235.             return offset;
  236.         }
  237.         if ((hole->size - waste) == size) {
  238.             hole->size = waste;
  239.             pipe_mutex_unlock(mgr->bo_va_mutex);
  240.             return offset;
  241.         }
  242.     }
  243.  
  244.     offset = mgr->va_offset;
  245.     waste = 0;
  246.     if (alignment) {
  247.         waste = offset % alignment;
  248.         waste = waste ? alignment - waste : 0;
  249.     }
  250.     if (waste) {
  251.         n = CALLOC_STRUCT(radeon_bo_va_hole);
  252.         n->size = waste;
  253.         n->offset = offset;
  254.         list_add(&n->list, &mgr->va_holes);
  255.     }
  256.     offset += waste;
  257.     mgr->va_offset += size + waste;
  258.     pipe_mutex_unlock(mgr->bo_va_mutex);
  259.     return offset;
  260. }
  261.  
  262. static void radeon_bomgr_force_va(struct radeon_bomgr *mgr, uint64_t va, uint64_t size)
  263. {
  264.     pipe_mutex_lock(mgr->bo_va_mutex);
  265.     if (va >= mgr->va_offset) {
  266.         if (va > mgr->va_offset) {
  267.             struct radeon_bo_va_hole *hole;
  268.             hole = CALLOC_STRUCT(radeon_bo_va_hole);
  269.             if (hole) {
  270.                 hole->size = va - mgr->va_offset;
  271.                 hole->offset = mgr->va_offset;
  272.                 list_add(&hole->list, &mgr->va_holes);
  273.             }
  274.         }
  275.         mgr->va_offset = va + size;
  276.     } else {
  277.         struct radeon_bo_va_hole *hole, *n;
  278.         uint64_t hole_end, va_end;
  279.  
  280.         /* Prune/free all holes that fall into the range
  281.          */
  282.         LIST_FOR_EACH_ENTRY_SAFE(hole, n, &mgr->va_holes, list) {
  283.             hole_end = hole->offset + hole->size;
  284.             va_end = va + size;
  285.             if (hole->offset >= va_end || hole_end <= va)
  286.                 continue;
  287.             if (hole->offset >= va && hole_end <= va_end) {
  288.                 list_del(&hole->list);
  289.                 FREE(hole);
  290.                 continue;
  291.             }
  292.             if (hole->offset >= va)
  293.                 hole->offset = va_end;
  294.             else
  295.                 hole_end = va;
  296.             hole->size = hole_end - hole->offset;
  297.         }
  298.     }
  299.     pipe_mutex_unlock(mgr->bo_va_mutex);
  300. }
  301.  
  302. static void radeon_bomgr_free_va(struct radeon_bomgr *mgr, uint64_t va, uint64_t size)
  303. {
  304.     struct radeon_bo_va_hole *hole;
  305.  
  306.     pipe_mutex_lock(mgr->bo_va_mutex);
  307.     if ((va + size) == mgr->va_offset) {
  308.         mgr->va_offset = va;
  309.         /* Delete uppermost hole if it reaches the new top */
  310.         if (!LIST_IS_EMPTY(&mgr->va_holes)) {
  311.             hole = container_of(mgr->va_holes.next, hole, list);
  312.             if ((hole->offset + hole->size) == va) {
  313.                 mgr->va_offset = hole->offset;
  314.                 list_del(&hole->list);
  315.                 FREE(hole);
  316.             }
  317.         }
  318.     } else {
  319.         struct radeon_bo_va_hole *next;
  320.  
  321.         hole = container_of(&mgr->va_holes, hole, list);
  322.         LIST_FOR_EACH_ENTRY(next, &mgr->va_holes, list) {
  323.             if (next->offset < va)
  324.                 break;
  325.             hole = next;
  326.         }
  327.  
  328.         if (&hole->list != &mgr->va_holes) {
  329.             /* Grow upper hole if it's adjacent */
  330.             if (hole->offset == (va + size)) {
  331.                 hole->offset = va;
  332.                 hole->size += size;
  333.                 /* Merge lower hole if it's adjacent */
  334.                 if (next != hole && &next->list != &mgr->va_holes &&
  335.                     (next->offset + next->size) == va) {
  336.                     next->size += hole->size;
  337.                     list_del(&hole->list);
  338.                     FREE(hole);
  339.                 }
  340.                 goto out;
  341.             }
  342.         }
  343.  
  344.         /* Grow lower hole if it's adjacent */
  345.         if (next != hole && &next->list != &mgr->va_holes &&
  346.             (next->offset + next->size) == va) {
  347.             next->size += size;
  348.             goto out;
  349.         }
  350.  
  351.         /* FIXME on allocation failure we just lose virtual address space
  352.          * maybe print a warning
  353.          */
  354.         next = CALLOC_STRUCT(radeon_bo_va_hole);
  355.         if (next) {
  356.             next->size = size;
  357.             next->offset = va;
  358.             list_add(&next->list, &hole->list);
  359.         }
  360.     }
  361. out:
  362.     pipe_mutex_unlock(mgr->bo_va_mutex);
  363. }
  364.  
  365. static void radeon_bo_destroy(struct pb_buffer *_buf)
  366. {
  367.     struct radeon_bo *bo = radeon_bo(_buf);
  368.     struct radeon_bomgr *mgr = bo->mgr;
  369.     struct drm_gem_close args;
  370.  
  371.     memset(&args, 0, sizeof(args));
  372.  
  373.     if (bo->name) {
  374.         pipe_mutex_lock(bo->mgr->bo_handles_mutex);
  375.         util_hash_table_remove(bo->mgr->bo_handles,
  376.                                (void*)(uintptr_t)bo->name);
  377.         pipe_mutex_unlock(bo->mgr->bo_handles_mutex);
  378.     }
  379.  
  380.     if (bo->ptr)
  381.         os_munmap(bo->ptr, bo->base.size);
  382.  
  383.     /* Close object. */
  384.     args.handle = bo->handle;
  385.     drmIoctl(bo->rws->fd, DRM_IOCTL_GEM_CLOSE, &args);
  386.  
  387.     if (mgr->va) {
  388.         radeon_bomgr_free_va(mgr, bo->va, bo->va_size);
  389.     }
  390.  
  391.     pipe_mutex_destroy(bo->map_mutex);
  392.  
  393.     if (bo->initial_domain & RADEON_DOMAIN_VRAM)
  394.         bo->rws->allocated_vram -= align(bo->base.size, 4096);
  395.     else if (bo->initial_domain & RADEON_DOMAIN_GTT)
  396.         bo->rws->allocated_gtt -= align(bo->base.size, 4096);
  397.     FREE(bo);
  398. }
  399.  
  400. void *radeon_bo_do_map(struct radeon_bo *bo)
  401. {
  402.     struct drm_radeon_gem_mmap args = {0};
  403.     void *ptr;
  404.  
  405.     /* Return the pointer if it's already mapped. */
  406.     if (bo->ptr)
  407.         return bo->ptr;
  408.  
  409.     /* Map the buffer. */
  410.     pipe_mutex_lock(bo->map_mutex);
  411.     /* Return the pointer if it's already mapped (in case of a race). */
  412.     if (bo->ptr) {
  413.         pipe_mutex_unlock(bo->map_mutex);
  414.         return bo->ptr;
  415.     }
  416.     args.handle = bo->handle;
  417.     args.offset = 0;
  418.     args.size = (uint64_t)bo->base.size;
  419.     if (drmCommandWriteRead(bo->rws->fd,
  420.                             DRM_RADEON_GEM_MMAP,
  421.                             &args,
  422.                             sizeof(args))) {
  423.         pipe_mutex_unlock(bo->map_mutex);
  424.         fprintf(stderr, "radeon: gem_mmap failed: %p 0x%08X\n",
  425.                 bo, bo->handle);
  426.         return NULL;
  427.     }
  428.  
  429.     ptr = os_mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED,
  430.                bo->rws->fd, args.addr_ptr);
  431.     if (ptr == MAP_FAILED) {
  432.         pipe_mutex_unlock(bo->map_mutex);
  433.         fprintf(stderr, "radeon: mmap failed, errno: %i\n", errno);
  434.         return NULL;
  435.     }
  436.     bo->ptr = ptr;
  437.     pipe_mutex_unlock(bo->map_mutex);
  438.  
  439.     return bo->ptr;
  440. }
  441.  
  442. static void *radeon_bo_map(struct radeon_winsys_cs_handle *buf,
  443.                            struct radeon_winsys_cs *rcs,
  444.                            enum pipe_transfer_usage usage)
  445. {
  446.     struct radeon_bo *bo = (struct radeon_bo*)buf;
  447.     struct radeon_drm_cs *cs = (struct radeon_drm_cs*)rcs;
  448.  
  449.     /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
  450.     if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
  451.         /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
  452.         if (usage & PIPE_TRANSFER_DONTBLOCK) {
  453.             if (!(usage & PIPE_TRANSFER_WRITE)) {
  454.                 /* Mapping for read.
  455.                  *
  456.                  * Since we are mapping for read, we don't need to wait
  457.                  * if the GPU is using the buffer for read too
  458.                  * (neither one is changing it).
  459.                  *
  460.                  * Only check whether the buffer is being used for write. */
  461.                 if (cs && radeon_bo_is_referenced_by_cs_for_write(cs, bo)) {
  462.                     cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC);
  463.                     return NULL;
  464.                 }
  465.  
  466.                 if (radeon_bo_is_busy((struct pb_buffer*)bo,
  467.                                       RADEON_USAGE_WRITE)) {
  468.                     return NULL;
  469.                 }
  470.             } else {
  471.                 if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) {
  472.                     cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC);
  473.                     return NULL;
  474.                 }
  475.  
  476.                 if (radeon_bo_is_busy((struct pb_buffer*)bo,
  477.                                       RADEON_USAGE_READWRITE)) {
  478.                     return NULL;
  479.                 }
  480.             }
  481.         } else {
  482.             uint64_t time = os_time_get_nano();
  483.  
  484.             if (!(usage & PIPE_TRANSFER_WRITE)) {
  485.                 /* Mapping for read.
  486.                  *
  487.                  * Since we are mapping for read, we don't need to wait
  488.                  * if the GPU is using the buffer for read too
  489.                  * (neither one is changing it).
  490.                  *
  491.                  * Only check whether the buffer is being used for write. */
  492.                 if (cs && radeon_bo_is_referenced_by_cs_for_write(cs, bo)) {
  493.                     cs->flush_cs(cs->flush_data, 0);
  494.                 }
  495.                 radeon_bo_wait((struct pb_buffer*)bo,
  496.                                RADEON_USAGE_WRITE);
  497.             } else {
  498.                 /* Mapping for write. */
  499.                 if (cs) {
  500.                     if (radeon_bo_is_referenced_by_cs(cs, bo)) {
  501.                         cs->flush_cs(cs->flush_data, 0);
  502.                     } else {
  503.                         /* Try to avoid busy-waiting in radeon_bo_wait. */
  504.                         if (p_atomic_read(&bo->num_active_ioctls))
  505.                             radeon_drm_cs_sync_flush(rcs);
  506.                     }
  507.                 }
  508.  
  509.                 radeon_bo_wait((struct pb_buffer*)bo, RADEON_USAGE_READWRITE);
  510.             }
  511.  
  512.             bo->mgr->rws->buffer_wait_time += os_time_get_nano() - time;
  513.         }
  514.     }
  515.  
  516.     return radeon_bo_do_map(bo);
  517. }
  518.  
  519. static void radeon_bo_unmap(struct radeon_winsys_cs_handle *_buf)
  520. {
  521.     /* NOP */
  522. }
  523.  
  524. static void radeon_bo_get_base_buffer(struct pb_buffer *buf,
  525.                                       struct pb_buffer **base_buf,
  526.                                       unsigned *offset)
  527. {
  528.     *base_buf = buf;
  529.     *offset = 0;
  530. }
  531.  
  532. static enum pipe_error radeon_bo_validate(struct pb_buffer *_buf,
  533.                                           struct pb_validate *vl,
  534.                                           unsigned flags)
  535. {
  536.     /* Always pinned */
  537.     return PIPE_OK;
  538. }
  539.  
  540. static void radeon_bo_fence(struct pb_buffer *buf,
  541.                             struct pipe_fence_handle *fence)
  542. {
  543. }
  544.  
  545. const struct pb_vtbl radeon_bo_vtbl = {
  546.     radeon_bo_destroy,
  547.     NULL, /* never called */
  548.     NULL, /* never called */
  549.     radeon_bo_validate,
  550.     radeon_bo_fence,
  551.     radeon_bo_get_base_buffer,
  552. };
  553.  
  554. static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr,
  555.                                                 pb_size size,
  556.                                                 const struct pb_desc *desc)
  557. {
  558.     struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
  559.     struct radeon_drm_winsys *rws = mgr->rws;
  560.     struct radeon_bo *bo;
  561.     struct drm_radeon_gem_create args;
  562.     struct radeon_bo_desc *rdesc = (struct radeon_bo_desc*)desc;
  563.     int r;
  564.  
  565.     memset(&args, 0, sizeof(args));
  566.  
  567.     assert(rdesc->initial_domains);
  568.     assert((rdesc->initial_domains &
  569.             ~(RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) == 0);
  570.  
  571.     args.size = size;
  572.     args.alignment = desc->alignment;
  573.     args.initial_domain = rdesc->initial_domains;
  574.  
  575.     if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_CREATE,
  576.                             &args, sizeof(args))) {
  577.         fprintf(stderr, "radeon: Failed to allocate a buffer:\n");
  578.         fprintf(stderr, "radeon:    size      : %d bytes\n", size);
  579.         fprintf(stderr, "radeon:    alignment : %d bytes\n", desc->alignment);
  580.         fprintf(stderr, "radeon:    domains   : %d\n", args.initial_domain);
  581.         return NULL;
  582.     }
  583.  
  584.     bo = CALLOC_STRUCT(radeon_bo);
  585.     if (!bo)
  586.         return NULL;
  587.  
  588.     pipe_reference_init(&bo->base.reference, 1);
  589.     bo->base.alignment = desc->alignment;
  590.     bo->base.usage = desc->usage;
  591.     bo->base.size = size;
  592.     bo->base.vtbl = &radeon_bo_vtbl;
  593.     bo->mgr = mgr;
  594.     bo->rws = mgr->rws;
  595.     bo->handle = args.handle;
  596.     bo->va = 0;
  597.     bo->initial_domain = rdesc->initial_domains;
  598.     pipe_mutex_init(bo->map_mutex);
  599.  
  600.     if (mgr->va) {
  601.         struct drm_radeon_gem_va va;
  602.  
  603.         bo->va_size = align(size,  4096);
  604.         bo->va = radeon_bomgr_find_va(mgr, bo->va_size, desc->alignment);
  605.  
  606.         va.handle = bo->handle;
  607.         va.vm_id = 0;
  608.         va.operation = RADEON_VA_MAP;
  609.         va.flags = RADEON_VM_PAGE_READABLE |
  610.                    RADEON_VM_PAGE_WRITEABLE |
  611.                    RADEON_VM_PAGE_SNOOPED;
  612.         va.offset = bo->va;
  613.         r = drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_VA, &va, sizeof(va));
  614.         if (r && va.operation == RADEON_VA_RESULT_ERROR) {
  615.             fprintf(stderr, "radeon: Failed to allocate virtual address for buffer:\n");
  616.             fprintf(stderr, "radeon:    size      : %d bytes\n", size);
  617.             fprintf(stderr, "radeon:    alignment : %d bytes\n", desc->alignment);
  618.             fprintf(stderr, "radeon:    domains   : %d\n", args.initial_domain);
  619.             fprintf(stderr, "radeon:    va        : 0x%016llx\n", (unsigned long long)bo->va);
  620.             radeon_bo_destroy(&bo->base);
  621.             return NULL;
  622.         }
  623.         if (va.operation == RADEON_VA_RESULT_VA_EXIST) {
  624.             radeon_bomgr_free_va(mgr, bo->va, bo->va_size);
  625.             bo->va = va.offset;
  626.             radeon_bomgr_force_va(mgr, bo->va, bo->va_size);
  627.         }
  628.     }
  629.  
  630.     if (rdesc->initial_domains & RADEON_DOMAIN_VRAM)
  631.         rws->allocated_vram += align(size, 4096);
  632.     else if (rdesc->initial_domains & RADEON_DOMAIN_GTT)
  633.         rws->allocated_gtt += align(size, 4096);
  634.  
  635.     return &bo->base;
  636. }
  637.  
  638. static void radeon_bomgr_flush(struct pb_manager *mgr)
  639. {
  640.     /* NOP */
  641. }
  642.  
  643. /* This is for the cache bufmgr. */
  644. static boolean radeon_bomgr_is_buffer_busy(struct pb_manager *_mgr,
  645.                                            struct pb_buffer *_buf)
  646. {
  647.    struct radeon_bo *bo = radeon_bo(_buf);
  648.  
  649.    if (radeon_bo_is_referenced_by_any_cs(bo)) {
  650.        return TRUE;
  651.    }
  652.  
  653.    if (radeon_bo_is_busy((struct pb_buffer*)bo, RADEON_USAGE_READWRITE)) {
  654.        return TRUE;
  655.    }
  656.  
  657.    return FALSE;
  658. }
  659.  
  660. static void radeon_bomgr_destroy(struct pb_manager *_mgr)
  661. {
  662.     struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
  663.     util_hash_table_destroy(mgr->bo_handles);
  664.     pipe_mutex_destroy(mgr->bo_handles_mutex);
  665.     pipe_mutex_destroy(mgr->bo_va_mutex);
  666.     FREE(mgr);
  667. }
  668.  
  669. #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
  670.  
  671. static unsigned handle_hash(void *key)
  672. {
  673.     return PTR_TO_UINT(key);
  674. }
  675.  
  676. static int handle_compare(void *key1, void *key2)
  677. {
  678.     return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
  679. }
  680.  
  681. struct pb_manager *radeon_bomgr_create(struct radeon_drm_winsys *rws)
  682. {
  683.     struct radeon_bomgr *mgr;
  684.  
  685.     mgr = CALLOC_STRUCT(radeon_bomgr);
  686.     if (!mgr)
  687.         return NULL;
  688.  
  689.     mgr->base.destroy = radeon_bomgr_destroy;
  690.     mgr->base.create_buffer = radeon_bomgr_create_bo;
  691.     mgr->base.flush = radeon_bomgr_flush;
  692.     mgr->base.is_buffer_busy = radeon_bomgr_is_buffer_busy;
  693.  
  694.     mgr->rws = rws;
  695.     mgr->bo_handles = util_hash_table_create(handle_hash, handle_compare);
  696.     pipe_mutex_init(mgr->bo_handles_mutex);
  697.     pipe_mutex_init(mgr->bo_va_mutex);
  698.  
  699.     mgr->va = rws->info.r600_virtual_address;
  700.     mgr->va_offset = rws->info.r600_va_start;
  701.     list_inithead(&mgr->va_holes);
  702.  
  703.     return &mgr->base;
  704. }
  705.  
  706. static unsigned eg_tile_split(unsigned tile_split)
  707. {
  708.     switch (tile_split) {
  709.     case 0:     tile_split = 64;    break;
  710.     case 1:     tile_split = 128;   break;
  711.     case 2:     tile_split = 256;   break;
  712.     case 3:     tile_split = 512;   break;
  713.     default:
  714.     case 4:     tile_split = 1024;  break;
  715.     case 5:     tile_split = 2048;  break;
  716.     case 6:     tile_split = 4096;  break;
  717.     }
  718.     return tile_split;
  719. }
  720.  
  721. static unsigned eg_tile_split_rev(unsigned eg_tile_split)
  722. {
  723.     switch (eg_tile_split) {
  724.     case 64:    return 0;
  725.     case 128:   return 1;
  726.     case 256:   return 2;
  727.     case 512:   return 3;
  728.     default:
  729.     case 1024:  return 4;
  730.     case 2048:  return 5;
  731.     case 4096:  return 6;
  732.     }
  733. }
  734.  
  735. static void radeon_bo_get_tiling(struct pb_buffer *_buf,
  736.                                  enum radeon_bo_layout *microtiled,
  737.                                  enum radeon_bo_layout *macrotiled,
  738.                                  unsigned *bankw, unsigned *bankh,
  739.                                  unsigned *tile_split,
  740.                                  unsigned *stencil_tile_split,
  741.                                  unsigned *mtilea)
  742. {
  743.     struct radeon_bo *bo = get_radeon_bo(_buf);
  744.     struct drm_radeon_gem_set_tiling args;
  745.  
  746.     memset(&args, 0, sizeof(args));
  747.  
  748.     args.handle = bo->handle;
  749.  
  750.     drmCommandWriteRead(bo->rws->fd,
  751.                         DRM_RADEON_GEM_GET_TILING,
  752.                         &args,
  753.                         sizeof(args));
  754.  
  755.     *microtiled = RADEON_LAYOUT_LINEAR;
  756.     *macrotiled = RADEON_LAYOUT_LINEAR;
  757.     if (args.tiling_flags & RADEON_BO_FLAGS_MICRO_TILE)
  758.         *microtiled = RADEON_LAYOUT_TILED;
  759.  
  760.     if (args.tiling_flags & RADEON_BO_FLAGS_MACRO_TILE)
  761.         *macrotiled = RADEON_LAYOUT_TILED;
  762.     if (bankw && tile_split && stencil_tile_split && mtilea && tile_split) {
  763.         *bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
  764.         *bankh = (args.tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
  765.         *tile_split = (args.tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
  766.         *stencil_tile_split = (args.tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
  767.         *mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
  768.         *tile_split = eg_tile_split(*tile_split);
  769.     }
  770. }
  771.  
  772. static void radeon_bo_set_tiling(struct pb_buffer *_buf,
  773.                                  struct radeon_winsys_cs *rcs,
  774.                                  enum radeon_bo_layout microtiled,
  775.                                  enum radeon_bo_layout macrotiled,
  776.                                  unsigned bankw, unsigned bankh,
  777.                                  unsigned tile_split,
  778.                                  unsigned stencil_tile_split,
  779.                                  unsigned mtilea,
  780.                                  uint32_t pitch)
  781. {
  782.     struct radeon_bo *bo = get_radeon_bo(_buf);
  783.     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
  784.     struct drm_radeon_gem_set_tiling args;
  785.  
  786.     memset(&args, 0, sizeof(args));
  787.  
  788.     /* Tiling determines how DRM treats the buffer data.
  789.      * We must flush CS when changing it if the buffer is referenced. */
  790.     if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) {
  791.         cs->flush_cs(cs->flush_data, 0);
  792.     }
  793.  
  794.     while (p_atomic_read(&bo->num_active_ioctls)) {
  795.         sched_yield();
  796.     }
  797.  
  798.     if (microtiled == RADEON_LAYOUT_TILED)
  799.         args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE;
  800.     else if (microtiled == RADEON_LAYOUT_SQUARETILED)
  801.         args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE_SQUARE;
  802.  
  803.     if (macrotiled == RADEON_LAYOUT_TILED)
  804.         args.tiling_flags |= RADEON_BO_FLAGS_MACRO_TILE;
  805.  
  806.     args.tiling_flags |= (bankw & RADEON_TILING_EG_BANKW_MASK) <<
  807.         RADEON_TILING_EG_BANKW_SHIFT;
  808.     args.tiling_flags |= (bankh & RADEON_TILING_EG_BANKH_MASK) <<
  809.         RADEON_TILING_EG_BANKH_SHIFT;
  810.     if (tile_split) {
  811.         args.tiling_flags |= (eg_tile_split_rev(tile_split) &
  812.                               RADEON_TILING_EG_TILE_SPLIT_MASK) <<
  813.             RADEON_TILING_EG_TILE_SPLIT_SHIFT;
  814.     }
  815.     args.tiling_flags |= (stencil_tile_split &
  816.                           RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK) <<
  817.         RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT;
  818.     args.tiling_flags |= (mtilea & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK) <<
  819.         RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT;
  820.  
  821.     args.handle = bo->handle;
  822.     args.pitch = pitch;
  823.  
  824.     drmCommandWriteRead(bo->rws->fd,
  825.                         DRM_RADEON_GEM_SET_TILING,
  826.                         &args,
  827.                         sizeof(args));
  828. }
  829.  
  830. static struct radeon_winsys_cs_handle *radeon_drm_get_cs_handle(struct pb_buffer *_buf)
  831. {
  832.     /* return radeon_bo. */
  833.     return (struct radeon_winsys_cs_handle*)get_radeon_bo(_buf);
  834. }
  835.  
  836. static struct pb_buffer *
  837. radeon_winsys_bo_create(struct radeon_winsys *rws,
  838.                         unsigned size,
  839.                         unsigned alignment,
  840.                         boolean use_reusable_pool,
  841.                         enum radeon_bo_domain domain)
  842. {
  843.     struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
  844.     struct radeon_bo_desc desc;
  845.     struct pb_manager *provider;
  846.     struct pb_buffer *buffer;
  847.  
  848.     memset(&desc, 0, sizeof(desc));
  849.     desc.base.alignment = alignment;
  850.  
  851.     /* Additional criteria for the cache manager. */
  852.     desc.base.usage = domain;
  853.     desc.initial_domains = domain;
  854.  
  855.     /* Assign a buffer manager. */
  856.     if (use_reusable_pool)
  857.         provider = ws->cman;
  858.     else
  859.         provider = ws->kman;
  860.  
  861.     buffer = provider->create_buffer(provider, size, &desc.base);
  862.     if (!buffer)
  863.         return NULL;
  864.  
  865.     return (struct pb_buffer*)buffer;
  866. }
  867.  
  868. static struct pb_buffer *radeon_winsys_bo_from_handle(struct radeon_winsys *rws,
  869.                                                       struct winsys_handle *whandle,
  870.                                                       unsigned *stride)
  871. {
  872.     struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
  873.     struct radeon_bo *bo;
  874.     struct radeon_bomgr *mgr = radeon_bomgr(ws->kman);
  875.     struct drm_gem_open open_arg = {};
  876.     int r;
  877.  
  878.     memset(&open_arg, 0, sizeof(open_arg));
  879.  
  880.     /* We must maintain a list of pairs <handle, bo>, so that we always return
  881.      * the same BO for one particular handle. If we didn't do that and created
  882.      * more than one BO for the same handle and then relocated them in a CS,
  883.      * we would hit a deadlock in the kernel.
  884.      *
  885.      * The list of pairs is guarded by a mutex, of course. */
  886.     pipe_mutex_lock(mgr->bo_handles_mutex);
  887.  
  888.     /* First check if there already is an existing bo for the handle. */
  889.     bo = util_hash_table_get(mgr->bo_handles, (void*)(uintptr_t)whandle->handle);
  890.     if (bo) {
  891.         /* Increase the refcount. */
  892.         struct pb_buffer *b = NULL;
  893.         pb_reference(&b, &bo->base);
  894.         goto done;
  895.     }
  896.  
  897.     /* There isn't, create a new one. */
  898.     bo = CALLOC_STRUCT(radeon_bo);
  899.     if (!bo) {
  900.         goto fail;
  901.     }
  902.  
  903.     /* Open the BO. */
  904.     open_arg.name = whandle->handle;
  905.     if (drmIoctl(ws->fd, DRM_IOCTL_GEM_OPEN, &open_arg)) {
  906.         FREE(bo);
  907.         goto fail;
  908.     }
  909.     bo->handle = open_arg.handle;
  910.     bo->name = whandle->handle;
  911.  
  912.     /* Initialize it. */
  913.     pipe_reference_init(&bo->base.reference, 1);
  914.     bo->base.alignment = 0;
  915.     bo->base.usage = PB_USAGE_GPU_WRITE | PB_USAGE_GPU_READ;
  916.     bo->base.size = open_arg.size;
  917.     bo->base.vtbl = &radeon_bo_vtbl;
  918.     bo->mgr = mgr;
  919.     bo->rws = mgr->rws;
  920.     bo->va = 0;
  921.     pipe_mutex_init(bo->map_mutex);
  922.  
  923.     util_hash_table_set(mgr->bo_handles, (void*)(uintptr_t)whandle->handle, bo);
  924.  
  925. done:
  926.     pipe_mutex_unlock(mgr->bo_handles_mutex);
  927.  
  928.     if (stride)
  929.         *stride = whandle->stride;
  930.  
  931.     if (mgr->va && !bo->va) {
  932.         struct drm_radeon_gem_va va;
  933.  
  934.         bo->va_size = ((bo->base.size + 4095) & ~4095);
  935.         bo->va = radeon_bomgr_find_va(mgr, bo->va_size, 1 << 20);
  936.  
  937.         va.handle = bo->handle;
  938.         va.operation = RADEON_VA_MAP;
  939.         va.vm_id = 0;
  940.         va.offset = bo->va;
  941.         va.flags = RADEON_VM_PAGE_READABLE |
  942.                    RADEON_VM_PAGE_WRITEABLE |
  943.                    RADEON_VM_PAGE_SNOOPED;
  944.         va.offset = bo->va;
  945.         r = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_VA, &va, sizeof(va));
  946.         if (r && va.operation == RADEON_VA_RESULT_ERROR) {
  947.             fprintf(stderr, "radeon: Failed to assign virtual address space\n");
  948.             radeon_bo_destroy(&bo->base);
  949.             return NULL;
  950.         }
  951.         if (va.operation == RADEON_VA_RESULT_VA_EXIST) {
  952.             radeon_bomgr_free_va(mgr, bo->va, bo->va_size);
  953.             bo->va = va.offset;
  954.             radeon_bomgr_force_va(mgr, bo->va, bo->va_size);
  955.         }
  956.     }
  957.  
  958.     ws->allocated_vram += align(open_arg.size, 4096);
  959.     bo->initial_domain = RADEON_DOMAIN_VRAM;
  960.  
  961.     return (struct pb_buffer*)bo;
  962.  
  963. fail:
  964.     pipe_mutex_unlock(mgr->bo_handles_mutex);
  965.     return NULL;
  966. }
  967.  
  968. static boolean radeon_winsys_bo_get_handle(struct pb_buffer *buffer,
  969.                                            unsigned stride,
  970.                                            struct winsys_handle *whandle)
  971. {
  972.     struct drm_gem_flink flink;
  973.     struct radeon_bo *bo = get_radeon_bo(buffer);
  974.  
  975.     memset(&flink, 0, sizeof(flink));
  976.  
  977.     if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
  978.         if (!bo->flinked) {
  979.             flink.handle = bo->handle;
  980.  
  981.             if (ioctl(bo->rws->fd, DRM_IOCTL_GEM_FLINK, &flink)) {
  982.                 return FALSE;
  983.             }
  984.  
  985.             bo->flinked = TRUE;
  986.             bo->flink = flink.name;
  987.  
  988.             pipe_mutex_lock(bo->mgr->bo_handles_mutex);
  989.             util_hash_table_set(bo->mgr->bo_handles, (void*)(uintptr_t)bo->flink, bo);
  990.             pipe_mutex_unlock(bo->mgr->bo_handles_mutex);
  991.         }
  992.         whandle->handle = bo->flink;
  993.     } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
  994.         whandle->handle = bo->handle;
  995.     }
  996.  
  997.     whandle->stride = stride;
  998.     return TRUE;
  999. }
  1000.  
  1001. static uint64_t radeon_winsys_bo_va(struct radeon_winsys_cs_handle *buf)
  1002. {
  1003.     return ((struct radeon_bo*)buf)->va;
  1004. }
  1005.  
  1006. void radeon_bomgr_init_functions(struct radeon_drm_winsys *ws)
  1007. {
  1008.     ws->base.buffer_get_cs_handle = radeon_drm_get_cs_handle;
  1009.     ws->base.buffer_set_tiling = radeon_bo_set_tiling;
  1010.     ws->base.buffer_get_tiling = radeon_bo_get_tiling;
  1011.     ws->base.buffer_map = radeon_bo_map;
  1012.     ws->base.buffer_unmap = radeon_bo_unmap;
  1013.     ws->base.buffer_wait = radeon_bo_wait;
  1014.     ws->base.buffer_is_busy = radeon_bo_is_busy;
  1015.     ws->base.buffer_create = radeon_winsys_bo_create;
  1016.     ws->base.buffer_from_handle = radeon_winsys_bo_from_handle;
  1017.     ws->base.buffer_get_handle = radeon_winsys_bo_get_handle;
  1018.     ws->base.buffer_get_virtual_address = radeon_winsys_bo_va;
  1019. }
  1020.