Subversion Repositories Kolibri OS

Rev

Go to most recent revision | Blame | Last modification | View Log | RSS feed

  1. /*
  2.  * Copyright 2011 Advanced Micro Devices, Inc.
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20.  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21.  * SOFTWARE.
  22.  *
  23.  * Authors: Tom Stellard <thomas.stellard@amd.com>
  24.  *
  25.  */
  26.  
  27. #ifndef RADEON_LLVM_H
  28. #define RADEON_LLVM_H
  29.  
  30. #include <llvm-c/Core.h>
  31. #include "gallivm/lp_bld_init.h"
  32. #include "gallivm/lp_bld_tgsi.h"
  33.  
  34. #define RADEON_LLVM_MAX_INPUTS 32 * 4
  35. #define RADEON_LLVM_MAX_OUTPUTS 32 * 4
  36. #define RADEON_LLVM_MAX_BRANCH_DEPTH 16
  37. #define RADEON_LLVM_MAX_LOOP_DEPTH 16
  38. #define RADEON_LLVM_MAX_ARRAYS 16
  39.  
  40. #define RADEON_LLVM_MAX_SYSTEM_VALUES 4
  41.  
  42. struct radeon_llvm_branch {
  43.         LLVMBasicBlockRef endif_block;
  44.         LLVMBasicBlockRef if_block;
  45.         LLVMBasicBlockRef else_block;
  46.         unsigned has_else;
  47. };
  48.  
  49. struct radeon_llvm_loop {
  50.         LLVMBasicBlockRef loop_block;
  51.         LLVMBasicBlockRef endloop_block;
  52. };
  53.  
  54. struct radeon_llvm_context {
  55.  
  56.         struct lp_build_tgsi_soa_context soa;
  57.  
  58.         unsigned chip_class;
  59.         unsigned type;
  60.         unsigned face_gpr;
  61.         unsigned two_side;
  62.         unsigned clip_vertex;
  63.         struct r600_shader_io * r600_inputs;
  64.         struct r600_shader_io * r600_outputs;
  65.         struct pipe_stream_output_info *stream_outputs;
  66.         unsigned color_buffer_count;
  67.         unsigned fs_color_all;
  68.         unsigned alpha_to_one;
  69.         unsigned has_txq_cube_array_z_comp;
  70.  
  71.         /*=== Front end configuration ===*/
  72.  
  73.         /* Special Intrinsics */
  74.  
  75.         /** Write to an output register: float store_output(float, i32) */
  76.         const char * store_output_intr;
  77.  
  78.         /** Swizzle a vector value: <4 x float> swizzle(<4 x float>, i32)
  79.          * The swizzle is an unsigned integer that encodes a TGSI_SWIZZLE_* value
  80.          * in 2-bits.
  81.          * Swizzle{0-1} = X Channel
  82.          * Swizzle{2-3} = Y Channel
  83.          * Swizzle{4-5} = Z Channel
  84.          * Swizzle{6-7} = W Channel
  85.          */
  86.         const char * swizzle_intr;
  87.  
  88.         /* Instructions that are not described by any of the TGSI opcodes. */
  89.  
  90.         /** This function is responsible for initilizing the inputs array and will be
  91.           * called once for each input declared in the TGSI shader.
  92.           */
  93.         void (*load_input)(struct radeon_llvm_context *,
  94.                         unsigned input_index,
  95.                         const struct tgsi_full_declaration *decl);
  96.  
  97.         void (*load_system_value)(struct radeon_llvm_context *,
  98.                         unsigned index,
  99.                         const struct tgsi_full_declaration *decl);
  100.  
  101.         /** User data to use with the callbacks */
  102.         void * userdata;
  103.  
  104.         /** This array contains the input values for the shader.  Typically these
  105.           * values will be in the form of a target intrinsic that will inform the
  106.           * backend how to load the actual inputs to the shader.
  107.           */
  108.         LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS];
  109.         LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS][TGSI_NUM_CHANNELS];
  110.         unsigned output_reg_count;
  111.  
  112.         LLVMValueRef system_values[RADEON_LLVM_MAX_SYSTEM_VALUES];
  113.  
  114.         /*=== Private Members ===*/
  115.  
  116.         struct radeon_llvm_branch branch[RADEON_LLVM_MAX_BRANCH_DEPTH];
  117.         struct radeon_llvm_loop loop[RADEON_LLVM_MAX_LOOP_DEPTH];
  118.  
  119.         unsigned branch_depth;
  120.         unsigned loop_depth;
  121.  
  122.         struct tgsi_declaration_range arrays[RADEON_LLVM_MAX_ARRAYS];
  123.         unsigned num_arrays;
  124.  
  125.         LLVMValueRef main_fn;
  126.  
  127.         struct gallivm_state gallivm;
  128. };
  129.  
  130. static inline LLVMTypeRef tgsi2llvmtype(
  131.                 struct lp_build_tgsi_context * bld_base,
  132.                 enum tgsi_opcode_type type)
  133. {
  134.         LLVMContextRef ctx = bld_base->base.gallivm->context;
  135.  
  136.         switch (type) {
  137.         case TGSI_TYPE_UNSIGNED:
  138.         case TGSI_TYPE_SIGNED:
  139.                 return LLVMInt32TypeInContext(ctx);
  140.         case TGSI_TYPE_UNTYPED:
  141.         case TGSI_TYPE_FLOAT:
  142.                 return LLVMFloatTypeInContext(ctx);
  143.         default: break;
  144.         }
  145.         return 0;
  146. }
  147.  
  148. static inline LLVMValueRef bitcast(
  149.                 struct lp_build_tgsi_context * bld_base,
  150.                 enum tgsi_opcode_type type,
  151.                 LLVMValueRef value
  152. )
  153. {
  154.         LLVMBuilderRef builder = bld_base->base.gallivm->builder;
  155.         LLVMTypeRef dst_type = tgsi2llvmtype(bld_base, type);
  156.  
  157.         if (dst_type)
  158.                 return LLVMBuildBitCast(builder, value, dst_type, "");
  159.         else
  160.                 return value;
  161. }
  162.  
  163.  
  164. void radeon_llvm_emit_prepare_cube_coords(struct lp_build_tgsi_context * bld_base,
  165.                                           struct lp_build_emit_data * emit_data,
  166.                                           LLVMValueRef *coords_arg);
  167.  
  168. void radeon_llvm_context_init(struct radeon_llvm_context * ctx);
  169.  
  170. void radeon_llvm_create_func(struct radeon_llvm_context * ctx,
  171.                              LLVMTypeRef *ParamTypes, unsigned ParamCount);
  172.  
  173. void radeon_llvm_dispose(struct radeon_llvm_context * ctx);
  174.  
  175. inline static struct radeon_llvm_context * radeon_llvm_context(
  176.         struct lp_build_tgsi_context * bld_base)
  177. {
  178.         return (struct radeon_llvm_context*)bld_base;
  179. }
  180.  
  181. unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan);
  182.  
  183. void radeon_llvm_finalize_module(struct radeon_llvm_context * ctx);
  184.  
  185. LLVMValueRef
  186. build_intrinsic(LLVMBuilderRef builder,
  187.                 const char *name,
  188.                 LLVMTypeRef ret_type,
  189.                 LLVMValueRef *args,
  190.                 unsigned num_args,
  191.                 LLVMAttribute attr);
  192.  
  193. void
  194. build_tgsi_intrinsic_nomem(
  195.                 const struct lp_build_tgsi_action * action,
  196.                 struct lp_build_tgsi_context * bld_base,
  197.                 struct lp_build_emit_data * emit_data);
  198.  
  199.  
  200.  
  201. #endif /* RADEON_LLVM_H */
  202.