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  1. /*
  2.  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * on the rights to use, copy, modify, merge, publish, distribute, sub
  8.  * license, and/or sell copies of the Software, and to permit persons to whom
  9.  * the Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18.  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19.  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20.  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21.  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *      Jerome Glisse
  25.  */
  26. #ifndef R600_PIPE_H
  27. #define R600_PIPE_H
  28.  
  29. #include "util/u_blitter.h"
  30. #include "util/u_slab.h"
  31. #include "util/u_suballoc.h"
  32. #include "util/u_double_list.h"
  33. #include "util/u_transfer.h"
  34. #include "r600_llvm.h"
  35. #include "r600_public.h"
  36. #include "r600_resource.h"
  37.  
  38. #define R600_NUM_ATOMS 41
  39.  
  40. /* the number of CS dwords for flushing and drawing */
  41. #define R600_MAX_FLUSH_CS_DWORDS        16
  42. #define R600_MAX_DRAW_CS_DWORDS         34
  43. #define R600_TRACE_CS_DWORDS            7
  44.  
  45. #define R600_MAX_USER_CONST_BUFFERS 13
  46. #define R600_MAX_DRIVER_CONST_BUFFERS 3
  47. #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
  48.  
  49. /* start driver buffers after user buffers */
  50. #define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
  51. #define R600_TXQ_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
  52. #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
  53.  
  54. #define R600_MAX_CONST_BUFFER_SIZE 4096
  55.  
  56. #ifdef PIPE_ARCH_BIG_ENDIAN
  57. #define R600_BIG_ENDIAN 1
  58. #else
  59. #define R600_BIG_ENDIAN 0
  60. #endif
  61.  
  62. #define R600_MAP_BUFFER_ALIGNMENT 64
  63.  
  64. #define R600_ERR(fmt, args...) \
  65.         fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
  66.  
  67. /* read caches */
  68. #define R600_CONTEXT_INV_VERTEX_CACHE           (1 << 0)
  69. #define R600_CONTEXT_INV_TEX_CACHE              (1 << 1)
  70. #define R600_CONTEXT_INV_CONST_CACHE            (1 << 2)
  71. /* read-write caches */
  72. #define R600_CONTEXT_STREAMOUT_FLUSH            (1 << 8)
  73. #define R600_CONTEXT_FLUSH_AND_INV              (1 << 9)
  74. #define R600_CONTEXT_FLUSH_AND_INV_CB_META      (1 << 10)
  75. #define R600_CONTEXT_FLUSH_AND_INV_DB_META      (1 << 11)
  76. #define R600_CONTEXT_FLUSH_AND_INV_DB           (1 << 12)
  77. #define R600_CONTEXT_FLUSH_AND_INV_CB           (1 << 13)
  78. /* engine synchronization */
  79. #define R600_CONTEXT_PS_PARTIAL_FLUSH           (1 << 16)
  80. #define R600_CONTEXT_WAIT_3D_IDLE               (1 << 17)
  81. #define R600_CONTEXT_WAIT_CP_DMA_IDLE           (1 << 18)
  82.  
  83. #define R600_QUERY_DRAW_CALLS           (PIPE_QUERY_DRIVER_SPECIFIC + 0)
  84. #define R600_QUERY_REQUESTED_VRAM       (PIPE_QUERY_DRIVER_SPECIFIC + 1)
  85. #define R600_QUERY_REQUESTED_GTT        (PIPE_QUERY_DRIVER_SPECIFIC + 2)
  86. #define R600_QUERY_BUFFER_WAIT_TIME     (PIPE_QUERY_DRIVER_SPECIFIC + 3)
  87.  
  88. struct r600_context;
  89. struct r600_bytecode;
  90. struct r600_shader_key;
  91.  
  92. /* This encapsulates a state or an operation which can emitted into the GPU
  93.  * command stream. It's not limited to states only, it can be used for anything
  94.  * that wants to write commands into the CS (e.g. cache flushes). */
  95. struct r600_atom {
  96.         void (*emit)(struct r600_context *ctx, struct r600_atom *state);
  97.         unsigned                id;
  98.         unsigned                num_dw;
  99.         bool                    dirty;
  100. };
  101.  
  102. /* This is an atom containing GPU commands that never change.
  103.  * This is supposed to be copied directly into the CS. */
  104. struct r600_command_buffer {
  105.         uint32_t *buf;
  106.         unsigned num_dw;
  107.         unsigned max_num_dw;
  108.         unsigned pkt_flags;
  109. };
  110.  
  111. struct r600_db_state {
  112.         struct r600_atom                atom;
  113.         struct r600_surface             *rsurf;
  114. };
  115.  
  116. struct r600_db_misc_state {
  117.         struct r600_atom                atom;
  118.         bool                            occlusion_query_enabled;
  119.         bool                            flush_depthstencil_through_cb;
  120.         bool                            flush_depthstencil_in_place;
  121.         bool                            copy_depth, copy_stencil;
  122.         unsigned                        copy_sample;
  123.         unsigned                        log_samples;
  124.         unsigned                        db_shader_control;
  125.         bool                            htile_clear;
  126. };
  127.  
  128. struct r600_cb_misc_state {
  129.         struct r600_atom atom;
  130.         unsigned cb_color_control; /* this comes from blend state */
  131.         unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
  132.         unsigned nr_cbufs;
  133.         unsigned nr_ps_color_outputs;
  134.         bool multiwrite;
  135.         bool dual_src_blend;
  136. };
  137.  
  138. struct r600_clip_misc_state {
  139.         struct r600_atom atom;
  140.         unsigned pa_cl_clip_cntl;   /* from rasterizer    */
  141.         unsigned pa_cl_vs_out_cntl; /* from vertex shader */
  142.         unsigned clip_plane_enable; /* from rasterizer    */
  143.         unsigned clip_dist_write;   /* from vertex shader */
  144. };
  145.  
  146. struct r600_alphatest_state {
  147.         struct r600_atom atom;
  148.         unsigned sx_alpha_test_control; /* this comes from dsa state */
  149.         unsigned sx_alpha_ref; /* this comes from dsa state */
  150.         bool bypass;
  151.         bool cb0_export_16bpc; /* from set_framebuffer_state */
  152. };
  153.  
  154. struct r600_vgt_state {
  155.         struct r600_atom atom;
  156.         uint32_t vgt_multi_prim_ib_reset_en;
  157.         uint32_t vgt_multi_prim_ib_reset_indx;
  158.         uint32_t vgt_indx_offset;
  159. };
  160.  
  161. struct r600_blend_color {
  162.         struct r600_atom atom;
  163.         struct pipe_blend_color state;
  164. };
  165.  
  166. struct r600_clip_state {
  167.         struct r600_atom atom;
  168.         struct pipe_clip_state state;
  169. };
  170.  
  171. struct r600_cs_shader_state {
  172.         struct r600_atom atom;
  173.         unsigned kernel_index;
  174.         struct r600_pipe_compute *shader;
  175. };
  176.  
  177. struct r600_framebuffer {
  178.         struct r600_atom atom;
  179.         struct pipe_framebuffer_state state;
  180.         unsigned compressed_cb_mask;
  181.         unsigned nr_samples;
  182.         bool export_16bpc;
  183.         bool cb0_is_integer;
  184.         bool is_msaa_resolve;
  185. };
  186.  
  187. struct r600_sample_mask {
  188.         struct r600_atom atom;
  189.         uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
  190. };
  191.  
  192. struct r600_config_state {
  193.         struct r600_atom atom;
  194.         unsigned sq_gpr_resource_mgmt_1;
  195. };
  196.  
  197. struct r600_stencil_ref
  198. {
  199.         ubyte ref_value[2];
  200.         ubyte valuemask[2];
  201.         ubyte writemask[2];
  202. };
  203.  
  204. struct r600_stencil_ref_state {
  205.         struct r600_atom atom;
  206.         struct r600_stencil_ref state;
  207.         struct pipe_stencil_ref pipe_state;
  208. };
  209.  
  210. struct r600_viewport_state {
  211.         struct r600_atom atom;
  212.         struct pipe_viewport_state state;
  213. };
  214.  
  215. struct r600_pipe_fences {
  216.         struct r600_resource            *bo;
  217.         unsigned                        *data;
  218.         unsigned                        next_index;
  219.         /* linked list of preallocated blocks */
  220.         struct list_head                blocks;
  221.         /* linked list of freed fences */
  222.         struct list_head                pool;
  223.         pipe_mutex                      mutex;
  224. };
  225.  
  226. typedef boolean (*r600g_dma_blit_t)(struct pipe_context *ctx,
  227.                                 struct pipe_resource *dst,
  228.                                 unsigned dst_level,
  229.                                 unsigned dst_x, unsigned dst_y, unsigned dst_z,
  230.                                 struct pipe_resource *src,
  231.                                 unsigned src_level,
  232.                                 const struct pipe_box *src_box);
  233.  
  234. /* logging */
  235. #define DBG_TEX_DEPTH           (1 << 0)
  236. #define DBG_COMPUTE             (1 << 1)
  237. #define DBG_VM                  (1 << 2)
  238. #define DBG_TRACE_CS            (1 << 3)
  239. /* shaders */
  240. #define DBG_FS                  (1 << 8)
  241. #define DBG_VS                  (1 << 9)
  242. #define DBG_GS                  (1 << 10)
  243. #define DBG_PS                  (1 << 11)
  244. #define DBG_CS                  (1 << 12)
  245. /* features */
  246. #define DBG_NO_HYPERZ           (1 << 16)
  247. #define DBG_NO_LLVM             (1 << 17)
  248. #define DBG_NO_CP_DMA           (1 << 18)
  249. #define DBG_NO_ASYNC_DMA        (1 << 19)
  250. #define DBG_NO_DISCARD_RANGE    (1 << 20)
  251. /* shader backend */
  252. #define DBG_SB                  (1 << 21)
  253. #define DBG_SB_CS               (1 << 22)
  254. #define DBG_SB_DRY_RUN  (1 << 23)
  255. #define DBG_SB_STAT             (1 << 24)
  256. #define DBG_SB_DUMP             (1 << 25)
  257. #define DBG_SB_NO_FALLBACK      (1 << 26)
  258. #define DBG_SB_DISASM   (1 << 27)
  259. #define DBG_SB_SAFEMATH (1 << 28)
  260.  
  261. struct r600_tiling_info {
  262.         unsigned num_channels;
  263.         unsigned num_banks;
  264.         unsigned group_bytes;
  265. };
  266.  
  267. struct r600_screen {
  268.         struct pipe_screen              screen;
  269.         struct radeon_winsys            *ws;
  270.         unsigned                        debug_flags;
  271.         unsigned                        family;
  272.         enum chip_class                 chip_class;
  273.         struct radeon_info              info;
  274.         bool                            has_streamout;
  275.         bool                            has_msaa;
  276.         bool                            has_cp_dma;
  277.         bool                            has_compressed_msaa_texturing;
  278.         struct r600_tiling_info         tiling_info;
  279.         struct r600_pipe_fences         fences;
  280.  
  281.         /*for compute global memory binding, we allocate stuff here, instead of
  282.          * buffers.
  283.          * XXX: Not sure if this is the best place for global_pool.  Also,
  284.          * it's not thread safe, so it won't work with multiple contexts. */
  285.         struct compute_memory_pool *global_pool;
  286.         struct r600_resource            *trace_bo;
  287.         uint32_t                        *trace_ptr;
  288.         unsigned                        cs_count;
  289.         r600g_dma_blit_t                dma_blit;
  290.  
  291.         /* Auxiliary context. Mainly used to initialize resources.
  292.          * It must be locked prior to using and flushed before unlocking. */
  293.         struct pipe_context             *aux_context;
  294.         pipe_mutex                      aux_context_lock;
  295. };
  296.  
  297. struct r600_pipe_sampler_view {
  298.         struct pipe_sampler_view        base;
  299.         struct r600_resource            *tex_resource;
  300.         uint32_t                        tex_resource_words[8];
  301.         bool                            skip_mip_address_reloc;
  302. };
  303.  
  304. struct r600_rasterizer_state {
  305.         struct r600_command_buffer      buffer;
  306.         boolean                         flatshade;
  307.         boolean                         two_side;
  308.         unsigned                        sprite_coord_enable;
  309.         unsigned                        clip_plane_enable;
  310.         unsigned                        pa_sc_line_stipple;
  311.         unsigned                        pa_cl_clip_cntl;
  312.         float                           offset_units;
  313.         float                           offset_scale;
  314.         bool                            offset_enable;
  315.         bool                            scissor_enable;
  316.         bool                            multisample_enable;
  317. };
  318.  
  319. struct r600_poly_offset_state {
  320.         struct r600_atom                atom;
  321.         enum pipe_format                zs_format;
  322.         float                           offset_units;
  323.         float                           offset_scale;
  324. };
  325.  
  326. struct r600_blend_state {
  327.         struct r600_command_buffer      buffer;
  328.         struct r600_command_buffer      buffer_no_blend;
  329.         unsigned                        cb_target_mask;
  330.         unsigned                        cb_color_control;
  331.         unsigned                        cb_color_control_no_blend;
  332.         bool                            dual_src_blend;
  333.         bool                            alpha_to_one;
  334. };
  335.  
  336. struct r600_dsa_state {
  337.         struct r600_command_buffer      buffer;
  338.         unsigned                        alpha_ref;
  339.         ubyte                           valuemask[2];
  340.         ubyte                           writemask[2];
  341.         unsigned                        zwritemask;
  342.         unsigned                        sx_alpha_test_control;
  343. };
  344.  
  345. struct r600_pipe_shader;
  346.  
  347. struct r600_pipe_shader_selector {
  348.         struct r600_pipe_shader *current;
  349.  
  350.         struct tgsi_token       *tokens;
  351.         struct pipe_stream_output_info  so;
  352.  
  353.         unsigned        num_shaders;
  354.  
  355.         /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
  356.         unsigned        type;
  357.  
  358.         unsigned        nr_ps_max_color_exports;
  359. };
  360.  
  361. struct r600_pipe_sampler_state {
  362.         uint32_t                        tex_sampler_words[3];
  363.         union pipe_color_union          border_color;
  364.         bool                            border_color_use;
  365.         bool                            seamless_cube_map;
  366. };
  367.  
  368. /* needed for blitter save */
  369. #define NUM_TEX_UNITS 16
  370.  
  371. struct r600_seamless_cube_map {
  372.         struct r600_atom                atom;
  373.         bool                            enabled;
  374. };
  375.  
  376. struct r600_samplerview_state {
  377.         struct r600_atom                atom;
  378.         struct r600_pipe_sampler_view   *views[NUM_TEX_UNITS];
  379.         uint32_t                        enabled_mask;
  380.         uint32_t                        dirty_mask;
  381.         uint32_t                        compressed_depthtex_mask; /* which textures are depth */
  382.         uint32_t                        compressed_colortex_mask;
  383.         boolean                         dirty_txq_constants;
  384.         boolean                         dirty_buffer_constants;
  385. };
  386.  
  387. struct r600_sampler_states {
  388.         struct r600_atom                atom;
  389.         struct r600_pipe_sampler_state  *states[NUM_TEX_UNITS];
  390.         uint32_t                        enabled_mask;
  391.         uint32_t                        dirty_mask;
  392.         uint32_t                        has_bordercolor_mask; /* which states contain the border color */
  393. };
  394.  
  395. struct r600_textures_info {
  396.         struct r600_samplerview_state   views;
  397.         struct r600_sampler_states      states;
  398.         bool                            is_array_sampler[NUM_TEX_UNITS];
  399.  
  400.         /* cube array txq workaround */
  401.         uint32_t                        *txq_constants;
  402.         /* buffer related workarounds */
  403.         uint32_t                        *buffer_constants;
  404. };
  405.  
  406. struct r600_fence {
  407.         struct pipe_reference           reference;
  408.         unsigned                        index; /* in the shared bo */
  409.         struct r600_resource            *sleep_bo;
  410.         struct list_head                head;
  411. };
  412.  
  413. #define FENCE_BLOCK_SIZE 16
  414.  
  415. struct r600_fence_block {
  416.         struct r600_fence               fences[FENCE_BLOCK_SIZE];
  417.         struct list_head                head;
  418. };
  419.  
  420. #define R600_CONSTANT_ARRAY_SIZE 256
  421. #define R600_RESOURCE_ARRAY_SIZE 160
  422.  
  423. struct r600_constbuf_state
  424. {
  425.         struct r600_atom                atom;
  426.         struct pipe_constant_buffer     cb[PIPE_MAX_CONSTANT_BUFFERS];
  427.         uint32_t                        enabled_mask;
  428.         uint32_t                        dirty_mask;
  429. };
  430.  
  431. struct r600_vertexbuf_state
  432. {
  433.         struct r600_atom                atom;
  434.         struct pipe_vertex_buffer       vb[PIPE_MAX_ATTRIBS];
  435.         uint32_t                        enabled_mask; /* non-NULL buffers */
  436.         uint32_t                        dirty_mask;
  437. };
  438.  
  439. /* CSO (constant state object, in other words, immutable state). */
  440. struct r600_cso_state
  441. {
  442.         struct r600_atom atom;
  443.         void *cso; /* e.g. r600_blend_state */
  444.         struct r600_command_buffer *cb;
  445. };
  446.  
  447. struct r600_scissor_state
  448. {
  449.         struct r600_atom                atom;
  450.         struct pipe_scissor_state       scissor;
  451.         bool                            enable; /* r6xx only */
  452. };
  453.  
  454. struct r600_fetch_shader {
  455.         struct r600_resource            *buffer;
  456.         unsigned                        offset;
  457. };
  458.  
  459. struct r600_shader_state {
  460.         struct r600_atom                atom;
  461.         struct r600_pipe_shader_selector *shader;
  462. };
  463.  
  464. struct r600_query_buffer {
  465.         /* The buffer where query results are stored. */
  466.         struct r600_resource                    *buf;
  467.         /* Offset of the next free result after current query data */
  468.         unsigned                                results_end;
  469.         /* If a query buffer is full, a new buffer is created and the old one
  470.          * is put in here. When we calculate the result, we sum up the samples
  471.          * from all buffers. */
  472.         struct r600_query_buffer                *previous;
  473. };
  474.  
  475. struct r600_query {
  476.         /* The query buffer and how many results are in it. */
  477.         struct r600_query_buffer                buffer;
  478.         /* The type of query */
  479.         unsigned                                type;
  480.         /* Size of the result in memory for both begin_query and end_query,
  481.          * this can be one or two numbers, or it could even be a size of a structure. */
  482.         unsigned                                result_size;
  483.         /* The number of dwords for begin_query or end_query. */
  484.         unsigned                                num_cs_dw;
  485.         /* linked list of queries */
  486.         struct list_head                        list;
  487.         /* for custom non-GPU queries */
  488.         uint64_t begin_result;
  489.         uint64_t end_result;
  490. };
  491.  
  492. struct r600_so_target {
  493.         struct pipe_stream_output_target b;
  494.  
  495.         /* The buffer where BUFFER_FILLED_SIZE is stored. */
  496.         struct r600_resource    *buf_filled_size;
  497.         unsigned                buf_filled_size_offset;
  498.  
  499.         unsigned                stride_in_dw;
  500.         unsigned                so_index;
  501. };
  502.  
  503. struct r600_streamout {
  504.         struct r600_atom                begin_atom;
  505.         bool                            begin_emitted;
  506.         unsigned                        num_dw_for_end;
  507.  
  508.         unsigned                        enabled_mask;
  509.         unsigned                        num_targets;
  510.         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
  511.  
  512.         unsigned                        append_bitmask;
  513.         bool                            suspended;
  514. };
  515.  
  516. struct r600_ring {
  517.         struct radeon_winsys_cs         *cs;
  518.         bool                            flushing;
  519.         void (*flush)(void *ctx, unsigned flags);
  520. };
  521.  
  522. struct r600_rings {
  523.         struct r600_ring                gfx;
  524.         struct r600_ring                dma;
  525. };
  526.  
  527. struct r600_context {
  528.         struct pipe_context             context;
  529.         struct r600_screen              *screen;
  530.         struct radeon_winsys            *ws;
  531.         struct r600_rings               rings;
  532.         struct blitter_context          *blitter;
  533.         struct u_upload_mgr             *uploader;
  534.         struct u_suballocator           *allocator_so_filled_size;
  535.         struct u_suballocator           *allocator_fetch_shader;
  536.         struct util_slab_mempool        pool_transfers;
  537.         unsigned                        initial_gfx_cs_size;
  538.  
  539.         /* Hardware info. */
  540.         enum radeon_family              family;
  541.         enum chip_class                 chip_class;
  542.         boolean                         has_vertex_cache;
  543.         boolean                         keep_tiling_flags;
  544.         unsigned                        default_ps_gprs, default_vs_gprs;
  545.         unsigned                        r6xx_num_clause_temp_gprs;
  546.         unsigned                        backend_mask;
  547.         unsigned                        max_db; /* for OQ */
  548.  
  549.         /* current unaccounted memory usage */
  550.         uint64_t                        vram;
  551.         uint64_t                        gtt;
  552.  
  553.         /* Miscellaneous state objects. */
  554.         void                            *custom_dsa_flush;
  555.         void                            *custom_blend_resolve;
  556.         void                            *custom_blend_decompress;
  557.         /* With rasterizer discard, there doesn't have to be a pixel shader.
  558.          * In that case, we bind this one: */
  559.         void                            *dummy_pixel_shader;
  560.         /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
  561.          * bug where valid CMASK and FMASK are required to be present to avoid
  562.          * a hardlock in certain operations but aren't actually used
  563.          * for anything useful. */
  564.         struct r600_resource            *dummy_fmask;
  565.         struct r600_resource            *dummy_cmask;
  566.  
  567.         /* State binding slots are here. */
  568.         struct r600_atom                *atoms[R600_NUM_ATOMS];
  569.         /* States for CS initialization. */
  570.         struct r600_command_buffer      start_cs_cmd; /* invariant state mostly */
  571.         /** Compute specific registers initializations.  The start_cs_cmd atom
  572.          *  must be emitted before start_compute_cs_cmd. */
  573.         struct r600_command_buffer      start_compute_cs_cmd;
  574.         /* Register states. */
  575.         struct r600_alphatest_state     alphatest_state;
  576.         struct r600_cso_state           blend_state;
  577.         struct r600_blend_color         blend_color;
  578.         struct r600_cb_misc_state       cb_misc_state;
  579.         struct r600_clip_misc_state     clip_misc_state;
  580.         struct r600_clip_state          clip_state;
  581.         struct r600_db_misc_state       db_misc_state;
  582.         struct r600_db_state            db_state;
  583.         struct r600_cso_state           dsa_state;
  584.         struct r600_framebuffer         framebuffer;
  585.         struct r600_poly_offset_state   poly_offset_state;
  586.         struct r600_cso_state           rasterizer_state;
  587.         struct r600_sample_mask         sample_mask;
  588.         struct r600_scissor_state       scissor;
  589.         struct r600_seamless_cube_map   seamless_cube_map;
  590.         struct r600_config_state        config_state;
  591.         struct r600_stencil_ref_state   stencil_ref;
  592.         struct r600_vgt_state           vgt_state;
  593.         struct r600_viewport_state      viewport;
  594.         /* Shaders and shader resources. */
  595.         struct r600_cso_state           vertex_fetch_shader;
  596.         struct r600_shader_state        vertex_shader;
  597.         struct r600_shader_state        pixel_shader;
  598.         struct r600_cs_shader_state     cs_shader_state;
  599.         struct r600_constbuf_state      constbuf_state[PIPE_SHADER_TYPES];
  600.         struct r600_textures_info       samplers[PIPE_SHADER_TYPES];
  601.         /** Vertex buffers for fetch shaders */
  602.         struct r600_vertexbuf_state     vertex_buffer_state;
  603.         /** Vertex buffers for compute shaders */
  604.         struct r600_vertexbuf_state     cs_vertex_buffer_state;
  605.         struct r600_streamout           streamout;
  606.  
  607.         /* Additional context states. */
  608.         unsigned                        flags;
  609.         unsigned                        compute_cb_target_mask;
  610.         struct r600_pipe_shader_selector *ps_shader;
  611.         struct r600_pipe_shader_selector *vs_shader;
  612.         struct r600_rasterizer_state    *rasterizer;
  613.         bool                            alpha_to_one;
  614.         bool                            force_blend_disable;
  615.         boolean                         dual_src_blend;
  616.         unsigned                        zwritemask;
  617.  
  618.         /* Index buffer. */
  619.         struct pipe_index_buffer        index_buffer;
  620.  
  621.         /* Last draw state (-1 = unset). */
  622.         int                             last_primitive_type; /* Last primitive type used in draw_vbo. */
  623.         int                             last_start_instance;
  624.  
  625.         /* Queries. */
  626.         /* The list of active queries. Only one query of each type can be active. */
  627.         int                             num_occlusion_queries;
  628.         int                             num_pipelinestat_queries;
  629.         /* Keep track of non-timer queries, because they should be suspended
  630.          * during context flushing.
  631.          * The timer queries (TIME_ELAPSED) shouldn't be suspended. */
  632.         struct list_head                active_nontimer_queries;
  633.         unsigned                        num_cs_dw_nontimer_queries_suspend;
  634.         /* If queries have been suspended. */
  635.         bool                            nontimer_queries_suspended;
  636.         unsigned                        num_draw_calls;
  637.  
  638.         /* Render condition. */
  639.         struct pipe_query               *current_render_cond;
  640.         unsigned                        current_render_cond_mode;
  641.         boolean                         current_render_cond_cond;
  642.         boolean                         predicate_drawing;
  643.  
  644.         void                            *sb_context;
  645.         struct r600_isa         *isa;
  646. };
  647.  
  648. static INLINE void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
  649.                                             struct r600_command_buffer *cb)
  650. {
  651.         assert(cs->cdw + cb->num_dw <= RADEON_MAX_CMDBUF_DWORDS);
  652.         memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->num_dw);
  653.         cs->cdw += cb->num_dw;
  654. }
  655.  
  656. void r600_trace_emit(struct r600_context *rctx);
  657.  
  658. static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
  659. {
  660.         atom->emit(rctx, atom);
  661.         atom->dirty = false;
  662.         if (rctx->screen->trace_bo) {
  663.                 r600_trace_emit(rctx);
  664.         }
  665. }
  666.  
  667. static INLINE void r600_set_cso_state(struct r600_cso_state *state, void *cso)
  668. {
  669.         state->cso = cso;
  670.         state->atom.dirty = cso != NULL;
  671. }
  672.  
  673. static INLINE void r600_set_cso_state_with_cb(struct r600_cso_state *state, void *cso,
  674.                                               struct r600_command_buffer *cb)
  675. {
  676.         state->cb = cb;
  677.         state->atom.num_dw = cb->num_dw;
  678.         r600_set_cso_state(state, cso);
  679. }
  680.  
  681. /* compute_memory_pool.c */
  682. struct compute_memory_pool;
  683. void compute_memory_pool_delete(struct compute_memory_pool* pool);
  684. struct compute_memory_pool* compute_memory_pool_new(
  685.         struct r600_screen *rscreen);
  686.  
  687. /* evergreen_state.c */
  688. struct pipe_sampler_view *
  689. evergreen_create_sampler_view_custom(struct pipe_context *ctx,
  690.                                      struct pipe_resource *texture,
  691.                                      const struct pipe_sampler_view *state,
  692.                                      unsigned width0, unsigned height0);
  693. void evergreen_init_common_regs(struct r600_command_buffer *cb,
  694.                                 enum chip_class ctx_chip_class,
  695.                                 enum radeon_family ctx_family,
  696.                                 int ctx_drm_minor);
  697. void cayman_init_common_regs(struct r600_command_buffer *cb,
  698.                              enum chip_class ctx_chip_class,
  699.                              enum radeon_family ctx_family,
  700.                              int ctx_drm_minor);
  701.  
  702. void evergreen_init_state_functions(struct r600_context *rctx);
  703. void evergreen_init_atom_start_cs(struct r600_context *rctx);
  704. void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
  705. void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
  706. void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
  707. void *evergreen_create_resolve_blend(struct r600_context *rctx);
  708. void *evergreen_create_decompress_blend(struct r600_context *rctx);
  709. boolean evergreen_is_format_supported(struct pipe_screen *screen,
  710.                                       enum pipe_format format,
  711.                                       enum pipe_texture_target target,
  712.                                       unsigned sample_count,
  713.                                       unsigned usage);
  714. void evergreen_init_color_surface(struct r600_context *rctx,
  715.                                   struct r600_surface *surf);
  716. void evergreen_init_color_surface_rat(struct r600_context *rctx,
  717.                                         struct r600_surface *surf);
  718. void evergreen_update_db_shader_control(struct r600_context * rctx);
  719.  
  720. /* r600_blit.c */
  721. void r600_copy_buffer(struct pipe_context *ctx, struct pipe_resource *dst, unsigned dstx,
  722.                       struct pipe_resource *src, const struct pipe_box *src_box);
  723. void r600_screen_clear_buffer(struct r600_screen *rscreen, struct pipe_resource *dst,
  724.                               unsigned offset, unsigned size, unsigned char value);
  725. void r600_init_blit_functions(struct r600_context *rctx);
  726. void r600_blit_decompress_depth(struct pipe_context *ctx,
  727.                 struct r600_texture *texture,
  728.                 struct r600_texture *staging,
  729.                 unsigned first_level, unsigned last_level,
  730.                 unsigned first_layer, unsigned last_layer,
  731.                 unsigned first_sample, unsigned last_sample);
  732. void r600_decompress_depth_textures(struct r600_context *rctx,
  733.                                     struct r600_samplerview_state *textures);
  734. void r600_decompress_color_textures(struct r600_context *rctx,
  735.                                     struct r600_samplerview_state *textures);
  736.  
  737. /* r600_buffer.c */
  738. bool r600_init_resource(struct r600_screen *rscreen,
  739.                         struct r600_resource *res,
  740.                         unsigned size, unsigned alignment,
  741.                         bool use_reusable_pool, unsigned usage);
  742. struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
  743.                                          const struct pipe_resource *templ,
  744.                                          unsigned alignment);
  745.  
  746. /* r600_pipe.c */
  747. boolean r600_rings_is_buffer_referenced(struct r600_context *ctx,
  748.                                         struct radeon_winsys_cs_handle *buf,
  749.                                         enum radeon_bo_usage usage);
  750. void *r600_buffer_mmap_sync_with_rings(struct r600_context *ctx,
  751.                                         struct r600_resource *resource,
  752.                                         unsigned usage);
  753. const char * r600_llvm_gpu_string(enum radeon_family family);
  754.  
  755.  
  756. /* r600_query.c */
  757. void r600_init_query_functions(struct r600_context *rctx);
  758. void r600_suspend_nontimer_queries(struct r600_context *ctx);
  759. void r600_resume_nontimer_queries(struct r600_context *ctx);
  760.  
  761. /* r600_resource.c */
  762. void r600_init_context_resource_functions(struct r600_context *r600);
  763.  
  764. /* r600_shader.c */
  765. int r600_pipe_shader_create(struct pipe_context *ctx,
  766.                             struct r600_pipe_shader *shader,
  767.                             struct r600_shader_key key);
  768.  
  769. void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
  770.  
  771. /* r600_state.c */
  772. struct pipe_sampler_view *
  773. r600_create_sampler_view_custom(struct pipe_context *ctx,
  774.                                 struct pipe_resource *texture,
  775.                                 const struct pipe_sampler_view *state,
  776.                                 unsigned width_first_level, unsigned height_first_level);
  777. void r600_init_state_functions(struct r600_context *rctx);
  778. void r600_init_atom_start_cs(struct r600_context *rctx);
  779. void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
  780. void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
  781. void *r600_create_db_flush_dsa(struct r600_context *rctx);
  782. void *r600_create_resolve_blend(struct r600_context *rctx);
  783. void *r700_create_resolve_blend(struct r600_context *rctx);
  784. void *r600_create_decompress_blend(struct r600_context *rctx);
  785. bool r600_adjust_gprs(struct r600_context *rctx);
  786. boolean r600_is_format_supported(struct pipe_screen *screen,
  787.                                  enum pipe_format format,
  788.                                  enum pipe_texture_target target,
  789.                                  unsigned sample_count,
  790.                                  unsigned usage);
  791. void r600_update_db_shader_control(struct r600_context * rctx);
  792.  
  793. /* r600_texture.c */
  794. void r600_init_screen_texture_functions(struct pipe_screen *screen);
  795. void r600_init_surface_functions(struct r600_context *r600);
  796. uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
  797.                                   const unsigned char *swizzle_view,
  798.                                   uint32_t *word4_p, uint32_t *yuv_format_p);
  799. struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
  800.                                                 struct pipe_resource *texture,
  801.                                                 const struct pipe_surface *templ,
  802.                                                 unsigned width, unsigned height);
  803.  
  804. unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
  805.                                    const unsigned char *swizzle_view,
  806.                                    boolean vtx);
  807.  
  808. /* r600_hw_context.c */
  809. void r600_get_backend_mask(struct r600_context *ctx);
  810. void r600_context_flush(struct r600_context *ctx, unsigned flags);
  811. void r600_begin_new_cs(struct r600_context *ctx);
  812. void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence,
  813.                              unsigned offset, unsigned value);
  814. void r600_flush_emit(struct r600_context *ctx);
  815. void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
  816. void r600_need_dma_space(struct r600_context *ctx, unsigned num_dw);
  817. void r600_cp_dma_copy_buffer(struct r600_context *rctx,
  818.                              struct pipe_resource *dst, uint64_t dst_offset,
  819.                              struct pipe_resource *src, uint64_t src_offset,
  820.                              unsigned size);
  821. void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
  822.                                    struct pipe_resource *dst, uint64_t offset,
  823.                                    unsigned size, uint32_t clear_value);
  824. void r600_dma_copy(struct r600_context *rctx,
  825.                 struct pipe_resource *dst,
  826.                 struct pipe_resource *src,
  827.                 uint64_t dst_offset,
  828.                 uint64_t src_offset,
  829.                 uint64_t size);
  830. boolean r600_dma_blit(struct pipe_context *ctx,
  831.                         struct pipe_resource *dst,
  832.                         unsigned dst_level,
  833.                         unsigned dst_x, unsigned dst_y, unsigned dst_z,
  834.                         struct pipe_resource *src,
  835.                         unsigned src_level,
  836.                         const struct pipe_box *src_box);
  837. void r600_emit_streamout_begin(struct r600_context *ctx, struct r600_atom *atom);
  838. void r600_emit_streamout_end(struct r600_context *ctx);
  839. void r600_flag_resource_cache_flush(struct r600_context *rctx,
  840.                                     struct pipe_resource *res);
  841.  
  842. /*
  843.  * evergreen_hw_context.c
  844.  */
  845. void evergreen_flush_vgt_streamout(struct r600_context *ctx);
  846. void evergreen_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit);
  847. void evergreen_dma_copy(struct r600_context *rctx,
  848.                 struct pipe_resource *dst,
  849.                 struct pipe_resource *src,
  850.                 uint64_t dst_offset,
  851.                 uint64_t src_offset,
  852.                 uint64_t size);
  853. boolean evergreen_dma_blit(struct pipe_context *ctx,
  854.                         struct pipe_resource *dst,
  855.                         unsigned dst_level,
  856.                         unsigned dst_x, unsigned dst_y, unsigned dst_z,
  857.                         struct pipe_resource *src,
  858.                         unsigned src_level,
  859.                         const struct pipe_box *src_box);
  860.  
  861. /* r600_state_common.c */
  862. void r600_init_common_state_functions(struct r600_context *rctx);
  863. void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
  864. void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
  865. void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
  866. void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
  867. void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
  868. void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
  869. void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom);
  870. void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
  871. void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
  872.                     void (*emit)(struct r600_context *ctx, struct r600_atom *state),
  873.                     unsigned num_dw);
  874. void r600_vertex_buffers_dirty(struct r600_context *rctx);
  875. void r600_sampler_views_dirty(struct r600_context *rctx,
  876.                               struct r600_samplerview_state *state);
  877. void r600_sampler_states_dirty(struct r600_context *rctx,
  878.                                struct r600_sampler_states *state);
  879. void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
  880. void r600_streamout_buffers_dirty(struct r600_context *rctx);
  881. void r600_draw_rectangle(struct blitter_context *blitter,
  882.                          int x1, int y1, int x2, int y2, float depth,
  883.                          enum blitter_attrib_type type, const union pipe_color_union *attrib);
  884. uint32_t r600_translate_stencil_op(int s_op);
  885. uint32_t r600_translate_fill(uint32_t func);
  886. unsigned r600_tex_wrap(unsigned wrap);
  887. unsigned r600_tex_filter(unsigned filter);
  888. unsigned r600_tex_mipfilter(unsigned filter);
  889. unsigned r600_tex_compare(unsigned compare);
  890. bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
  891.  
  892. /* r600_uvd.c */
  893. struct pipe_video_decoder *r600_uvd_create_decoder(struct pipe_context *context,
  894.                                                    enum pipe_video_profile profile,
  895.                                                    enum pipe_video_entrypoint entrypoint,
  896.                                                    enum pipe_video_chroma_format chroma_format,
  897.                                                    unsigned width, unsigned height,
  898.                                                    unsigned max_references, bool expect_chunked_decode);
  899.  
  900. struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
  901.                                                    const struct pipe_video_buffer *tmpl);
  902.  
  903. int r600_uvd_get_video_param(struct pipe_screen *screen,
  904.                              enum pipe_video_profile profile,
  905.                              enum pipe_video_cap param);
  906.  
  907. /*
  908.  * Helpers for building command buffers
  909.  */
  910.  
  911. #define PKT3_SET_CONFIG_REG     0x68
  912. #define PKT3_SET_CONTEXT_REG    0x69
  913. #define PKT3_SET_CTL_CONST      0x6F
  914. #define PKT3_SET_LOOP_CONST                    0x6C
  915.  
  916. #define R600_CONFIG_REG_OFFSET  0x08000
  917. #define R600_CONTEXT_REG_OFFSET 0x28000
  918. #define R600_CTL_CONST_OFFSET   0x3CFF0
  919. #define R600_LOOP_CONST_OFFSET                 0X0003E200
  920. #define EG_LOOP_CONST_OFFSET               0x0003A200
  921.  
  922. #define PKT_TYPE_S(x)                   (((x) & 0x3) << 30)
  923. #define PKT_COUNT_S(x)                  (((x) & 0x3FFF) << 16)
  924. #define PKT3_IT_OPCODE_S(x)             (((x) & 0xFF) << 8)
  925. #define PKT3_PREDICATE(x)               (((x) >> 0) & 0x1)
  926. #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
  927.  
  928. #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
  929.  
  930. /*Evergreen Compute packet3*/
  931. #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
  932.  
  933. static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
  934. {
  935.         cb->buf[cb->num_dw++] = value;
  936. }
  937.  
  938. static INLINE void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
  939. {
  940.         assert(cb->num_dw+num <= cb->max_num_dw);
  941.         memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
  942.         cb->num_dw += num;
  943. }
  944.  
  945. static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
  946. {
  947.         assert(reg < R600_CONTEXT_REG_OFFSET);
  948.         assert(cb->num_dw+2+num <= cb->max_num_dw);
  949.         cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
  950.         cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
  951. }
  952.  
  953. /**
  954.  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
  955.  * shaders.
  956.  */
  957. static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
  958. {
  959.         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
  960.         assert(cb->num_dw+2+num <= cb->max_num_dw);
  961.         cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
  962.         cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
  963. }
  964.  
  965. /**
  966.  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
  967.  * shaders.
  968.  */
  969. static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
  970. {
  971.         assert(reg >= R600_CTL_CONST_OFFSET);
  972.         assert(cb->num_dw+2+num <= cb->max_num_dw);
  973.         cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
  974.         cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
  975. }
  976.  
  977. static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
  978. {
  979.         assert(reg >= R600_LOOP_CONST_OFFSET);
  980.         assert(cb->num_dw+2+num <= cb->max_num_dw);
  981.         cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
  982.         cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
  983. }
  984.  
  985. /**
  986.  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
  987.  * shaders.
  988.  */
  989. static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
  990. {
  991.         assert(reg >= EG_LOOP_CONST_OFFSET);
  992.         assert(cb->num_dw+2+num <= cb->max_num_dw);
  993.         cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
  994.         cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
  995. }
  996.  
  997. static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
  998. {
  999.         r600_store_config_reg_seq(cb, reg, 1);
  1000.         r600_store_value(cb, value);
  1001. }
  1002.  
  1003. static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
  1004. {
  1005.         r600_store_context_reg_seq(cb, reg, 1);
  1006.         r600_store_value(cb, value);
  1007. }
  1008.  
  1009. static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
  1010. {
  1011.         r600_store_ctl_const_seq(cb, reg, 1);
  1012.         r600_store_value(cb, value);
  1013. }
  1014.  
  1015. static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
  1016. {
  1017.         r600_store_loop_const_seq(cb, reg, 1);
  1018.         r600_store_value(cb, value);
  1019. }
  1020.  
  1021. static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
  1022. {
  1023.         eg_store_loop_const_seq(cb, reg, 1);
  1024.         r600_store_value(cb, value);
  1025. }
  1026.  
  1027. void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
  1028. void r600_release_command_buffer(struct r600_command_buffer *cb);
  1029.  
  1030. /*
  1031.  * Helpers for emitting state into a command stream directly.
  1032.  */
  1033. static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx,
  1034.                                              struct r600_ring *ring,
  1035.                                              struct r600_resource *rbo,
  1036.                                              enum radeon_bo_usage usage)
  1037. {
  1038.         assert(usage);
  1039.         /* make sure that all previous ring use are flushed so everything
  1040.          * look serialized from driver pov
  1041.          */
  1042.         if (!ring->flushing) {
  1043.                 if (ring == &ctx->rings.gfx) {
  1044.                         if (ctx->rings.dma.cs) {
  1045.                                 /* flush dma ring */
  1046.                                 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
  1047.                         }
  1048.                 } else {
  1049.                         /* flush gfx ring */
  1050.                         ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
  1051.                 }
  1052.         }
  1053.         return ctx->ws->cs_add_reloc(ring->cs, rbo->cs_buf, usage, rbo->domains) * 4;
  1054. }
  1055.  
  1056. static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
  1057. {
  1058.         cs->buf[cs->cdw++] = value;
  1059. }
  1060.  
  1061. static INLINE void r600_write_array(struct radeon_winsys_cs *cs, unsigned num, unsigned *ptr)
  1062. {
  1063.         assert(cs->cdw+num <= RADEON_MAX_CMDBUF_DWORDS);
  1064.         memcpy(&cs->buf[cs->cdw], ptr, num * sizeof(ptr[0]));
  1065.         cs->cdw += num;
  1066. }
  1067.  
  1068. static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
  1069. {
  1070.         assert(reg < R600_CONTEXT_REG_OFFSET);
  1071.         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
  1072.         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
  1073.         cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
  1074. }
  1075.  
  1076. static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
  1077. {
  1078.         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
  1079.         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
  1080.         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
  1081.         cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
  1082. }
  1083.  
  1084. static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
  1085. {
  1086.         r600_write_context_reg_seq(cs, reg, num);
  1087.         /* Set the compute bit on the packet header */
  1088.         cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
  1089. }
  1090.  
  1091. static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
  1092. {
  1093.         assert(reg >= R600_CTL_CONST_OFFSET);
  1094.         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
  1095.         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
  1096.         cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
  1097. }
  1098.  
  1099. static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
  1100. {
  1101.         r600_write_config_reg_seq(cs, reg, 1);
  1102.         r600_write_value(cs, value);
  1103. }
  1104.  
  1105. static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
  1106. {
  1107.         r600_write_context_reg_seq(cs, reg, 1);
  1108.         r600_write_value(cs, value);
  1109. }
  1110.  
  1111. static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
  1112. {
  1113.         r600_write_compute_context_reg_seq(cs, reg, 1);
  1114.         r600_write_value(cs, value);
  1115. }
  1116.  
  1117. static INLINE void r600_write_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
  1118. {
  1119.         if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
  1120.                 r600_write_compute_context_reg(cs, reg, value);
  1121.         } else {
  1122.                 r600_write_context_reg(cs, reg, value);
  1123.         }
  1124.  
  1125. }
  1126. static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
  1127. {
  1128.         r600_write_ctl_const_seq(cs, reg, 1);
  1129.         r600_write_value(cs, value);
  1130. }
  1131.  
  1132. /*
  1133.  * common helpers
  1134.  */
  1135. static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
  1136. {
  1137.         return value * (1 << frac_bits);
  1138. }
  1139. #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
  1140.  
  1141. static inline unsigned r600_tex_aniso_filter(unsigned filter)
  1142. {
  1143.         if (filter <= 1)   return 0;
  1144.         if (filter <= 2)   return 1;
  1145.         if (filter <= 4)   return 2;
  1146.         if (filter <= 8)   return 3;
  1147.          /* else */        return 4;
  1148. }
  1149.  
  1150. /* 12.4 fixed-point */
  1151. static INLINE unsigned r600_pack_float_12p4(float x)
  1152. {
  1153.         return x <= 0    ? 0 :
  1154.                x >= 4096 ? 0xffff : x * 16;
  1155. }
  1156.  
  1157. static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
  1158. {
  1159.         struct r600_screen *rscreen = (struct r600_screen*)screen;
  1160.         struct r600_resource *rresource = (struct r600_resource*)resource;
  1161.  
  1162.         return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
  1163. }
  1164.  
  1165. static INLINE void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
  1166. {
  1167.         struct r600_context *rctx = (struct r600_context *)ctx;
  1168.         struct r600_resource *rr = (struct r600_resource *)r;
  1169.  
  1170.         if (r == NULL) {
  1171.                 return;
  1172.         }
  1173.  
  1174.         /*
  1175.          * The idea is to compute a gross estimate of memory requirement of
  1176.          * each draw call. After each draw call, memory will be precisely
  1177.          * accounted. So the uncertainty is only on the current draw call.
  1178.          * In practice this gave very good estimate (+/- 10% of the target
  1179.          * memory limit).
  1180.          */
  1181.         if (rr->domains & RADEON_DOMAIN_GTT) {
  1182.                 rctx->gtt += rr->buf->size;
  1183.         }
  1184.         if (rr->domains & RADEON_DOMAIN_VRAM) {
  1185.                 rctx->vram += rr->buf->size;
  1186.         }
  1187. }
  1188.  
  1189. #endif
  1190.