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  1. /*
  2.  * Copyright 2012 Advanced Micro Devices, Inc.
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * on the rights to use, copy, modify, merge, publish, distribute, sub
  8.  * license, and/or sell copies of the Software, and to permit persons to whom
  9.  * the Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18.  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19.  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20.  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21.  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22.  *
  23.  * Author: Tom Stellard <thomas.stellard@amd.com>
  24.  */
  25.  
  26. #ifndef RADEON_REGALLOC_H
  27. #define RADEON_REGALLOC_H
  28.  
  29. struct ra_regs;
  30.  
  31. enum rc_reg_class {
  32.         RC_REG_CLASS_SINGLE,
  33.         RC_REG_CLASS_DOUBLE,
  34.         RC_REG_CLASS_TRIPLE,
  35.         RC_REG_CLASS_ALPHA,
  36.         RC_REG_CLASS_SINGLE_PLUS_ALPHA,
  37.         RC_REG_CLASS_DOUBLE_PLUS_ALPHA,
  38.         RC_REG_CLASS_TRIPLE_PLUS_ALPHA,
  39.         RC_REG_CLASS_X,
  40.         RC_REG_CLASS_Y,
  41.         RC_REG_CLASS_Z,
  42.         RC_REG_CLASS_XY,
  43.         RC_REG_CLASS_YZ,
  44.         RC_REG_CLASS_XZ,
  45.         RC_REG_CLASS_XW,
  46.         RC_REG_CLASS_YW,
  47.         RC_REG_CLASS_ZW,
  48.         RC_REG_CLASS_XYW,
  49.         RC_REG_CLASS_YZW,
  50.         RC_REG_CLASS_XZW,
  51.         RC_REG_CLASS_COUNT
  52. };
  53.  
  54. struct rc_regalloc_state {
  55.         struct ra_regs *regs;
  56.         unsigned class_ids[RC_REG_CLASS_COUNT];
  57. };
  58.  
  59. void rc_init_regalloc_state(struct rc_regalloc_state *s);
  60. void rc_destroy_regalloc_state(struct rc_regalloc_state *s);
  61.  
  62. #endif /* RADEON_REGALLOC_H */
  63.