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  1.  
  2. #ifndef NVE4_COMPUTE_H
  3. #define NVE4_COMPUTE_H
  4.  
  5. #include "nv50/nv50_defs.xml.h"
  6. #include "nve4_compute.xml.h"
  7.  
  8. /* Input space is implemented as c0[], to which we bind the screen->parm bo.
  9.  */
  10. #define NVE4_CP_INPUT_USER           0x0000
  11. #define NVE4_CP_INPUT_USER_LIMIT     0x1000
  12. #define NVE4_CP_INPUT_GRID_INFO(i)  (0x1000 + (i) * 4)
  13. #define NVE4_CP_INPUT_NTID(i)       (0x1000 + (i) * 4)
  14. #define NVE4_CP_INPUT_NCTAID(i)     (0x100c + (i) * 4)
  15. #define NVE4_CP_INPUT_GRIDID         0x1018
  16. #define NVE4_CP_INPUT_TEX(i)        (0x1040 + (i) * 4)
  17. #define NVE4_CP_INPUT_TEX_STRIDE     4
  18. #define NVE4_CP_INPUT_TEX_MAX        32
  19. #define NVE4_CP_INPUT_MS_OFFSETS     0x10c0
  20. #define NVE4_CP_INPUT_SUF_STRIDE     64
  21. #define NVE4_CP_INPUT_SUF(i)        (0x1100 + (i) * NVE4_CP_INPUT_SUF_STRIDE)
  22. #define NVE4_CP_INPUT_SUF_MAX        32
  23. #define NVE4_CP_INPUT_TRAP_INFO_PTR  0x1900
  24. #define NVE4_CP_INPUT_TEMP_PTR       0x1908
  25. #define NVE4_CP_INPUT_MP_TEMP_SIZE   0x1910
  26. #define NVE4_CP_INPUT_WARP_TEMP_SIZE 0x1914
  27. #define NVE4_CP_INPUT_CSTACK_SIZE    0x1918
  28. #define NVE4_CP_INPUT_SIZE           0x1a00
  29. #define NVE4_CP_PARAM_TRAP_INFO      0x2000
  30. #define NVE4_CP_PARAM_TRAP_INFO_SZ  (1 << 16)
  31. #define NVE4_CP_PARAM_SIZE          (NVE4_CP_PARAM_TRAP_INFO + (1 << 16))
  32.  
  33. struct nve4_cp_launch_desc
  34. {
  35.    u32 unk0[8];
  36.    u32 entry;
  37.    u32 unk9[3];
  38.    u32 griddim_x    : 31;
  39.    u32 unk12        : 1;
  40.    u16 griddim_y;
  41.    u16 griddim_z;
  42.    u32 unk14[3];
  43.    u16 shared_size; /* must be aligned to 0x100 */
  44.    u16 unk15;
  45.    u16 unk16;
  46.    u16 blockdim_x;
  47.    u16 blockdim_y;
  48.    u16 blockdim_z;
  49.    u32 cb_mask      : 8;
  50.    u32 unk20_8      : 21;
  51.    u32 cache_split  : 2;
  52.    u32 unk20_31     : 1;
  53.    u32 unk21[8];
  54.    struct {
  55.       u32 address_l;
  56.       u32 address_h : 8;
  57.       u32 reserved  : 7;
  58.       u32 size      : 17;
  59.    } cb[8];
  60.    u32 local_size_p : 20;
  61.    u32 unk45_20     : 7;
  62.    u32 bar_alloc    : 5;
  63.    u32 local_size_n : 20;
  64.    u32 unk46_20     : 4;
  65.    u32 gpr_alloc    : 8;
  66.    u32 cstack_size  : 20;
  67.    u32 unk47_20     : 12;
  68.    u32 unk48[16];
  69. };
  70.  
  71. static INLINE void
  72. nve4_cp_launch_desc_init_default(struct nve4_cp_launch_desc *desc)
  73. {
  74.    memset(desc, 0, sizeof(*desc));
  75.  
  76.    desc->unk0[7]  = 0xbc000000;
  77.    desc->unk9[2]  = 0x44014000;
  78.    desc->unk47_20 = 0x300;
  79. }
  80.  
  81. static INLINE void
  82. nve4_cp_launch_desc_set_cb(struct nve4_cp_launch_desc *desc,
  83.                            unsigned index,
  84.                            struct nouveau_bo *bo,
  85.                            uint32_t base, uint16_t size)
  86. {
  87.    uint64_t address = bo->offset + base;
  88.  
  89.    assert(index < 8);
  90.    assert(!(base & 0xff));
  91.    assert(size <= 65536);
  92.  
  93.    desc->cb[index].address_l = address;
  94.    desc->cb[index].address_h = address >> 32;
  95.    desc->cb[index].size = size;
  96.  
  97.    desc->cb_mask |= 1 << index;
  98. }
  99.  
  100. static INLINE void
  101. nve4_cp_launch_desc_set_ctx_cb(struct nve4_cp_launch_desc *desc,
  102.                                unsigned index,
  103.                                const struct nvc0_constbuf *cb)
  104. {
  105.    assert(index < 8);
  106.  
  107.    if (!cb->u.buf) {
  108.       desc->cb_mask &= ~(1 << index);
  109.    } else {
  110.       const struct nv04_resource *buf = nv04_resource(cb->u.buf);
  111.       assert(!cb->user);
  112.       nve4_cp_launch_desc_set_cb(desc, index,
  113.                                  buf->bo, buf->offset + cb->offset, cb->size);
  114.    }
  115. }
  116.  
  117. struct nve4_mp_trap_info {
  118.    u32 lock;
  119.    u32 pc;
  120.    u32 trapstat;
  121.    u32 warperr;
  122.    u32 tid[3];
  123.    u32 ctaid[3];
  124.    u32 pad028[2];
  125.    u32 r[64];
  126.    u32 flags;
  127.    u32 pad134[3];
  128.    u32 s[0x3000];
  129. };
  130.  
  131. #endif /* NVE4_COMPUTE_H */
  132.