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  1. #ifndef __NVC0_SCREEN_H__
  2. #define __NVC0_SCREEN_H__
  3.  
  4. #include "nouveau/nouveau_screen.h"
  5. #include "nouveau/nouveau_mm.h"
  6. #include "nouveau/nouveau_fence.h"
  7. #include "nouveau/nouveau_heap.h"
  8.  
  9. #include "nouveau/nv_object.xml.h"
  10.  
  11. #include "nvc0_winsys.h"
  12. #include "nvc0_stateobj.h"
  13.  
  14. #define NVC0_TIC_MAX_ENTRIES 2048
  15. #define NVC0_TSC_MAX_ENTRIES 2048
  16.  
  17. /* doesn't count reserved slots (for auxiliary constants, immediates, etc.) */
  18. #define NVC0_MAX_PIPE_CONSTBUFS         14
  19. #define NVE4_MAX_PIPE_CONSTBUFS_COMPUTE  7
  20.  
  21. #define NVC0_MAX_SURFACE_SLOTS 16
  22.  
  23. struct nvc0_context;
  24.  
  25. struct nvc0_blitter;
  26.  
  27. struct nvc0_screen {
  28.    struct nouveau_screen base;
  29.  
  30.    struct nvc0_context *cur_ctx;
  31.  
  32.    int num_occlusion_queries_active;
  33.  
  34.    struct nouveau_bo *text;
  35.    struct nouveau_bo *parm;       /* for COMPUTE */
  36.    struct nouveau_bo *uniform_bo; /* for 3D */
  37.    struct nouveau_bo *tls;
  38.    struct nouveau_bo *txc; /* TIC (offset 0) and TSC (65536) */
  39.    struct nouveau_bo *poly_cache;
  40.  
  41.    uint16_t mp_count;
  42.    uint16_t mp_count_compute; /* magic reg can make compute use fewer MPs */
  43.  
  44.    struct nouveau_heap *text_heap;
  45.    struct nouveau_heap *lib_code; /* allocated from text_heap */
  46.  
  47.    struct nvc0_blitter *blitter;
  48.  
  49.    struct {
  50.       void **entries;
  51.       int next;
  52.       uint32_t lock[NVC0_TIC_MAX_ENTRIES / 32];
  53.    } tic;
  54.    
  55.    struct {
  56.       void **entries;
  57.       int next;
  58.       uint32_t lock[NVC0_TSC_MAX_ENTRIES / 32];
  59.    } tsc;
  60.  
  61.    struct {
  62.       struct nouveau_bo *bo;
  63.       uint32_t *map;
  64.    } fence;
  65.  
  66.    struct {
  67.       struct nvc0_program *prog; /* compute state object to read MP counters */
  68.       struct pipe_query *mp_counter[8]; /* counter to query allocation */
  69.       uint8_t num_mp_pm_active[2];
  70.       boolean mp_counters_enabled;
  71.    } pm;
  72.  
  73.    struct nouveau_mman *mm_VRAM_fe0;
  74.  
  75.    struct nouveau_object *eng3d; /* sqrt(1/2)|kepler> + sqrt(1/2)|fermi> */
  76.    struct nouveau_object *eng2d;
  77.    struct nouveau_object *m2mf;
  78.    struct nouveau_object *compute;
  79. };
  80.  
  81. static INLINE struct nvc0_screen *
  82. nvc0_screen(struct pipe_screen *screen)
  83. {
  84.    return (struct nvc0_screen *)screen;
  85. }
  86.  
  87.  
  88. /* Performance counter queries:
  89.  */
  90. #define NVE4_PM_QUERY_COUNT  39
  91. #define NVE4_PM_QUERY(i)    (PIPE_QUERY_DRIVER_SPECIFIC + (i))
  92. #define NVE4_PM_QUERY_LAST   NVE4_PM_QUERY(NVE4_PM_QUERY_COUNT - 1)
  93. #define NVE4_PM_QUERY_PROF_TRIGGER_0            0
  94. #define NVE4_PM_QUERY_PROF_TRIGGER_1            1
  95. #define NVE4_PM_QUERY_PROF_TRIGGER_2            2
  96. #define NVE4_PM_QUERY_PROF_TRIGGER_3            3
  97. #define NVE4_PM_QUERY_PROF_TRIGGER_4            4
  98. #define NVE4_PM_QUERY_PROF_TRIGGER_5            5
  99. #define NVE4_PM_QUERY_PROF_TRIGGER_6            6
  100. #define NVE4_PM_QUERY_PROF_TRIGGER_7            7
  101. #define NVE4_PM_QUERY_LAUNCHED_WARPS            8
  102. #define NVE4_PM_QUERY_LAUNCHED_THREADS          9
  103. #define NVE4_PM_QUERY_LAUNCHED_CTA              10
  104. #define NVE4_PM_QUERY_INST_ISSUED1              11
  105. #define NVE4_PM_QUERY_INST_ISSUED2              12
  106. #define NVE4_PM_QUERY_INST_EXECUTED             13
  107. #define NVE4_PM_QUERY_LD_LOCAL                  14
  108. #define NVE4_PM_QUERY_ST_LOCAL                  15
  109. #define NVE4_PM_QUERY_LD_SHARED                 16
  110. #define NVE4_PM_QUERY_ST_SHARED                 17
  111. #define NVE4_PM_QUERY_L1_LOCAL_LOAD_HIT         18
  112. #define NVE4_PM_QUERY_L1_LOCAL_LOAD_MISS        19
  113. #define NVE4_PM_QUERY_L1_LOCAL_STORE_HIT        20
  114. #define NVE4_PM_QUERY_L1_LOCAL_STORE_MISS       21
  115. #define NVE4_PM_QUERY_GLD_REQUEST               22
  116. #define NVE4_PM_QUERY_GST_REQUEST               23
  117. #define NVE4_PM_QUERY_L1_GLOBAL_LOAD_HIT        24
  118. #define NVE4_PM_QUERY_L1_GLOBAL_LOAD_MISS       25
  119. #define NVE4_PM_QUERY_GLD_TRANSACTIONS_UNCACHED 26
  120. #define NVE4_PM_QUERY_GST_TRANSACTIONS          27
  121. #define NVE4_PM_QUERY_BRANCH                    28
  122. #define NVE4_PM_QUERY_BRANCH_DIVERGENT          29
  123. #define NVE4_PM_QUERY_ACTIVE_WARPS              30
  124. #define NVE4_PM_QUERY_ACTIVE_CYCLES             31
  125. #define NVE4_PM_QUERY_INST_ISSUED               32
  126. #define NVE4_PM_QUERY_METRIC_IPC                33
  127. #define NVE4_PM_QUERY_METRIC_IPAC               34
  128. #define NVE4_PM_QUERY_METRIC_IPEC               35
  129. #define NVE4_PM_QUERY_METRIC_MP_OCCUPANCY       36
  130. #define NVE4_PM_QUERY_METRIC_MP_EFFICIENCY      37
  131. #define NVE4_PM_QUERY_METRIC_INST_REPLAY_OHEAD  38
  132. /*
  133. #define NVE4_PM_QUERY_GR_IDLE                   50
  134. #define NVE4_PM_QUERY_BSP_IDLE                  51
  135. #define NVE4_PM_QUERY_VP_IDLE                   52
  136. #define NVE4_PM_QUERY_PPP_IDLE                  53
  137. #define NVE4_PM_QUERY_CE0_IDLE                  54
  138. #define NVE4_PM_QUERY_CE1_IDLE                  55
  139. #define NVE4_PM_QUERY_CE2_IDLE                  56
  140. */
  141. /* L2 queries (PCOUNTER) */
  142. /*
  143. #define NVE4_PM_QUERY_L2_SUBP_WRITE_L1_SECTOR_QUERIES 57
  144. ...
  145. */
  146. /* TEX queries (PCOUNTER) */
  147. /*
  148. #define NVE4_PM_QUERY_TEX0_CACHE_SECTOR_QUERIES 58
  149. ...
  150. */
  151.  
  152. /* Driver statistics queries:
  153.  */
  154. #ifdef NOUVEAU_ENABLE_DRIVER_STATISTICS
  155.  
  156. #define NVC0_QUERY_DRV_STAT(i)    (PIPE_QUERY_DRIVER_SPECIFIC + 1024 + (i))
  157. #define NVC0_QUERY_DRV_STAT_COUNT  29
  158. #define NVC0_QUERY_DRV_STAT_LAST   NVC0_QUERY_DRV_STAT(NVC0_QUERY_DRV_STAT_COUNT - 1)
  159. #define NVC0_QUERY_DRV_STAT_TEX_OBJECT_CURRENT_COUNT         0
  160. #define NVC0_QUERY_DRV_STAT_TEX_OBJECT_CURRENT_BYTES         1
  161. #define NVC0_QUERY_DRV_STAT_BUF_OBJECT_CURRENT_COUNT         2
  162. #define NVC0_QUERY_DRV_STAT_BUF_OBJECT_CURRENT_BYTES_VID     3
  163. #define NVC0_QUERY_DRV_STAT_BUF_OBJECT_CURRENT_BYTES_SYS     4
  164. #define NVC0_QUERY_DRV_STAT_TEX_TRANSFERS_READ               5
  165. #define NVC0_QUERY_DRV_STAT_TEX_TRANSFERS_WRITE              6
  166. #define NVC0_QUERY_DRV_STAT_TEX_COPY_COUNT                   7
  167. #define NVC0_QUERY_DRV_STAT_TEX_BLIT_COUNT                   8
  168. #define NVC0_QUERY_DRV_STAT_TEX_CACHE_FLUSH_COUNT            9
  169. #define NVC0_QUERY_DRV_STAT_BUF_TRANSFERS_READ              10
  170. #define NVC0_QUERY_DRV_STAT_BUF_TRANSFERS_WRITE             11
  171. #define NVC0_QUERY_DRV_STAT_BUF_READ_BYTES_STAGING_VID      12
  172. #define NVC0_QUERY_DRV_STAT_BUF_WRITE_BYTES_DIRECT          13
  173. #define NVC0_QUERY_DRV_STAT_BUF_WRITE_BYTES_STAGING_VID     14
  174. #define NVC0_QUERY_DRV_STAT_BUF_WRITE_BYTES_STAGING_SYS     15
  175. #define NVC0_QUERY_DRV_STAT_BUF_COPY_BYTES                  16
  176. #define NVC0_QUERY_DRV_STAT_BUF_NON_KERNEL_FENCE_SYNC_COUNT 17
  177. #define NVC0_QUERY_DRV_STAT_ANY_NON_KERNEL_FENCE_SYNC_COUNT 18
  178. #define NVC0_QUERY_DRV_STAT_QUERY_SYNC_COUNT                19
  179. #define NVC0_QUERY_DRV_STAT_GPU_SERIALIZE_COUNT             20
  180. #define NVC0_QUERY_DRV_STAT_DRAW_CALLS_ARRAY                21
  181. #define NVC0_QUERY_DRV_STAT_DRAW_CALLS_INDEXED              22
  182. #define NVC0_QUERY_DRV_STAT_DRAW_CALLS_FALLBACK_COUNT       23
  183. #define NVC0_QUERY_DRV_STAT_USER_BUFFER_UPLOAD_BYTES        24
  184. #define NVC0_QUERY_DRV_STAT_CONSTBUF_UPLOAD_COUNT           25
  185. #define NVC0_QUERY_DRV_STAT_CONSTBUF_UPLOAD_BYTES           26
  186. #define NVC0_QUERY_DRV_STAT_PUSHBUF_COUNT                   27
  187. #define NVC0_QUERY_DRV_STAT_RESOURCE_VALIDATE_COUNT         28
  188.  
  189. #else
  190.  
  191. #define NVC0_QUERY_DRV_STAT_COUNT 0
  192.  
  193. #endif
  194.  
  195. int nvc0_screen_get_driver_query_info(struct pipe_screen *, unsigned,
  196.                                       struct pipe_driver_query_info *);
  197.  
  198. boolean nvc0_blitter_create(struct nvc0_screen *);
  199. void nvc0_blitter_destroy(struct nvc0_screen *);
  200.  
  201. void nvc0_screen_make_buffers_resident(struct nvc0_screen *);
  202.  
  203. int nvc0_screen_tic_alloc(struct nvc0_screen *, void *);
  204. int nvc0_screen_tsc_alloc(struct nvc0_screen *, void *);
  205.  
  206. int nve4_screen_compute_setup(struct nvc0_screen *, struct nouveau_pushbuf *);
  207.  
  208. boolean nvc0_screen_resize_tls_area(struct nvc0_screen *, uint32_t lpos,
  209.                                     uint32_t lneg, uint32_t cstack);
  210.  
  211. static INLINE void
  212. nvc0_resource_fence(struct nv04_resource *res, uint32_t flags)
  213. {
  214.    struct nvc0_screen *screen = nvc0_screen(res->base.screen);
  215.  
  216.    if (res->mm) {
  217.       nouveau_fence_ref(screen->base.fence.current, &res->fence);
  218.       if (flags & NOUVEAU_BO_WR)
  219.          nouveau_fence_ref(screen->base.fence.current, &res->fence_wr);
  220.    }
  221. }
  222.  
  223. static INLINE void
  224. nvc0_resource_validate(struct nv04_resource *res, uint32_t flags)
  225. {
  226.    if (likely(res->bo)) {
  227.       if (flags & NOUVEAU_BO_WR)
  228.          res->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING |
  229.             NOUVEAU_BUFFER_STATUS_DIRTY;
  230.       if (flags & NOUVEAU_BO_RD)
  231.          res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
  232.  
  233.       nvc0_resource_fence(res, flags);
  234.    }
  235. }
  236.  
  237. struct nvc0_format {
  238.    uint32_t rt;
  239.    uint32_t tic;
  240.    uint32_t vtx;
  241.    uint32_t usage;
  242. };
  243.  
  244. extern const struct nvc0_format nvc0_format_table[];
  245.  
  246. static INLINE void
  247. nvc0_screen_tic_unlock(struct nvc0_screen *screen, struct nv50_tic_entry *tic)
  248. {
  249.    if (tic->id >= 0)
  250.       screen->tic.lock[tic->id / 32] &= ~(1 << (tic->id % 32));
  251. }
  252.  
  253. static INLINE void
  254. nvc0_screen_tsc_unlock(struct nvc0_screen *screen, struct nv50_tsc_entry *tsc)
  255. {
  256.    if (tsc->id >= 0)
  257.       screen->tsc.lock[tsc->id / 32] &= ~(1 << (tsc->id % 32));
  258. }
  259.  
  260. static INLINE void
  261. nvc0_screen_tic_free(struct nvc0_screen *screen, struct nv50_tic_entry *tic)
  262. {
  263.    if (tic->id >= 0) {
  264.       screen->tic.entries[tic->id] = NULL;
  265.       screen->tic.lock[tic->id / 32] &= ~(1 << (tic->id % 32));
  266.    }
  267. }
  268.  
  269. static INLINE void
  270. nvc0_screen_tsc_free(struct nvc0_screen *screen, struct nv50_tsc_entry *tsc)
  271. {
  272.    if (tsc->id >= 0) {
  273.       screen->tsc.entries[tsc->id] = NULL;
  274.       screen->tsc.lock[tsc->id / 32] &= ~(1 << (tsc->id % 32));
  275.    }
  276. }
  277.  
  278. #endif
  279.