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  1. /*
  2.  * Copyright 2010 Christoph Bumiller
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice shall be included in
  12.  * all copies or substantial portions of the Software.
  13.  *
  14.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20.  * OTHER DEALINGS IN THE SOFTWARE.
  21.  */
  22.  
  23. #include "util/u_format.h"
  24. #include "util/u_format_s3tc.h"
  25. #include "pipe/p_screen.h"
  26.  
  27. #include "vl/vl_decoder.h"
  28. #include "vl/vl_video_buffer.h"
  29.  
  30. #include "nvc0_context.h"
  31. #include "nvc0_screen.h"
  32.  
  33. #include "nvc0_graph_macros.h"
  34.  
  35. #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  36. # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  37. #endif
  38.  
  39. static boolean
  40. nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  41.                                 enum pipe_format format,
  42.                                 enum pipe_texture_target target,
  43.                                 unsigned sample_count,
  44.                                 unsigned bindings)
  45. {
  46.    if (sample_count > 8)
  47.       return FALSE;
  48.    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  49.       return FALSE;
  50.  
  51.    if (!util_format_is_supported(format, bindings))
  52.       return FALSE;
  53.  
  54.    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  55.       if (util_format_get_blocksizebits(format) == 3 * 32)
  56.          return FALSE;
  57.  
  58.    /* transfers & shared are always supported */
  59.    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  60.                  PIPE_BIND_TRANSFER_WRITE |
  61.                  PIPE_BIND_SHARED);
  62.  
  63.    return (nvc0_format_table[format].usage & bindings) == bindings;
  64. }
  65.  
  66. static boolean
  67. nvc0_screen_video_supported(struct pipe_screen *screen,
  68.                             enum pipe_format format,
  69.                             enum pipe_video_profile profile)
  70. {
  71.    if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
  72.       return format == PIPE_FORMAT_NV12;
  73.  
  74.    return vl_video_buffer_is_format_supported(screen, format, profile);
  75. }
  76.  
  77.  
  78. static int
  79. nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  80. {
  81.    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  82.  
  83.    switch (param) {
  84.    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  85.       return 16 * 5;
  86.    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  87.    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  88.       return 15;
  89.    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  90.       return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
  91.    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  92.       return 2048;
  93.    case PIPE_CAP_MIN_TEXEL_OFFSET:
  94.       return -8;
  95.    case PIPE_CAP_MAX_TEXEL_OFFSET:
  96.       return 7;
  97.    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  98.    case PIPE_CAP_TEXTURE_SWIZZLE:
  99.    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  100.    case PIPE_CAP_NPOT_TEXTURES:
  101.    case PIPE_CAP_ANISOTROPIC_FILTER:
  102.    case PIPE_CAP_SEAMLESS_CUBE_MAP:
  103.    case PIPE_CAP_CUBE_MAP_ARRAY:
  104.    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  105.    case PIPE_CAP_TEXTURE_MULTISAMPLE:
  106.       return 1;
  107.    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
  108.       return 65536;
  109.    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  110.       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
  111.    case PIPE_CAP_TWO_SIDED_STENCIL:
  112.    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  113.    case PIPE_CAP_POINT_SPRITE:
  114.    case PIPE_CAP_TGSI_TEXCOORD:
  115.       return 1;
  116.    case PIPE_CAP_SM3:
  117.       return 1;
  118.    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  119.       return 150;
  120.    case PIPE_CAP_MAX_RENDER_TARGETS:
  121.       return 8;
  122.    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  123.       return 1;
  124.    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
  125.    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  126.    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
  127.       return 1;
  128.    case PIPE_CAP_QUERY_TIMESTAMP:
  129.    case PIPE_CAP_QUERY_TIME_ELAPSED:
  130.    case PIPE_CAP_OCCLUSION_QUERY:
  131.    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
  132.    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
  133.       return 1;
  134.    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
  135.       return 4;
  136.    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
  137.    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
  138.       return 128;
  139.    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  140.    case PIPE_CAP_INDEP_BLEND_ENABLE:
  141.    case PIPE_CAP_INDEP_BLEND_FUNC:
  142.       return 1;
  143.    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  144.    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  145.       return 1;
  146.    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  147.    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  148.       return 0;
  149.    case PIPE_CAP_SHADER_STENCIL_EXPORT:
  150.       return 0;
  151.    case PIPE_CAP_PRIMITIVE_RESTART:
  152.    case PIPE_CAP_TGSI_INSTANCEID:
  153.    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  154.    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  155.    case PIPE_CAP_CONDITIONAL_RENDER:
  156.    case PIPE_CAP_TEXTURE_BARRIER:
  157.    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
  158.    case PIPE_CAP_START_INSTANCE:
  159.       return 1;
  160.    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
  161.       return 0; /* state trackers will know better */
  162.    case PIPE_CAP_USER_CONSTANT_BUFFERS:
  163.    case PIPE_CAP_USER_INDEX_BUFFERS:
  164.    case PIPE_CAP_USER_VERTEX_BUFFERS:
  165.       return 1;
  166.    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  167.       return 256;
  168.    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
  169.       return 1; /* 256 for binding as RT, but that's not possible in GL */
  170.    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
  171.       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
  172.    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
  173.    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
  174.    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
  175.       return 0;
  176.    case PIPE_CAP_COMPUTE:
  177.       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
  178.    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  179.       return 1;
  180.    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
  181.       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
  182.    case PIPE_CAP_ENDIANNESS:
  183.       return PIPE_ENDIAN_LITTLE;
  184.    default:
  185.       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
  186.       return 0;
  187.    }
  188. }
  189.  
  190. static int
  191. nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
  192.                              enum pipe_shader_cap param)
  193. {
  194.    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  195.  
  196.    switch (shader) {
  197.    case PIPE_SHADER_VERTEX:
  198.       /*
  199.    case PIPE_SHADER_TESSELLATION_CONTROL:
  200.    case PIPE_SHADER_TESSELLATION_EVALUATION:
  201.       */
  202.    case PIPE_SHADER_GEOMETRY:
  203.    case PIPE_SHADER_FRAGMENT:
  204.       break;
  205.    case PIPE_SHADER_COMPUTE:
  206.       if (class_3d < NVE4_3D_CLASS)
  207.          return 0;
  208.       break;
  209.    default:
  210.       return 0;
  211.    }
  212.    
  213.    switch (param) {
  214.    case PIPE_SHADER_CAP_PREFERRED_IR:
  215.       return PIPE_SHADER_IR_TGSI;
  216.    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
  217.    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
  218.    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
  219.    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
  220.       return 16384;
  221.    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
  222.       return 16;
  223.    case PIPE_SHADER_CAP_MAX_INPUTS:
  224.       if (shader == PIPE_SHADER_VERTEX)
  225.          return 32;
  226.       /* NOTE: These only count our slots for GENERIC varyings.
  227.        * The address space may be larger, but the actual hard limit seems to be
  228.        * less than what the address space layout permits, so don't add TEXCOORD,
  229.        * COLOR, etc. here.
  230.        */
  231.       if (shader == PIPE_SHADER_FRAGMENT)
  232.          return 0x1f0 / 16;
  233.       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
  234.        * and excludes 0x60 per-patch inputs.
  235.        */
  236.       return 0x200 / 16;
  237.    case PIPE_SHADER_CAP_MAX_CONSTS:
  238.       return 65536 / 16;
  239.    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
  240.       if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
  241.          return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
  242.       return NVC0_MAX_PIPE_CONSTBUFS;
  243.    case PIPE_SHADER_CAP_MAX_ADDRS:
  244.       return 1;
  245.    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
  246.    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
  247.       return shader != PIPE_SHADER_FRAGMENT;
  248.    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
  249.    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
  250.       return 1;
  251.    case PIPE_SHADER_CAP_MAX_PREDS:
  252.       return 0;
  253.    case PIPE_SHADER_CAP_MAX_TEMPS:
  254.       return NVC0_CAP_MAX_PROGRAM_TEMPS;
  255.    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
  256.       return 1;
  257.    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
  258.       return 0;
  259.    case PIPE_SHADER_CAP_SUBROUTINES:
  260.       return 1;
  261.    case PIPE_SHADER_CAP_INTEGERS:
  262.       return 1;
  263.    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
  264.       return 16; /* would be 32 in linked (OpenGL-style) mode */
  265.       /*
  266.    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLER_VIEWS:
  267.       return 32;
  268.       */
  269.    default:
  270.       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
  271.       return 0;
  272.    }
  273. }
  274.  
  275. static float
  276. nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
  277. {
  278.    switch (param) {
  279.    case PIPE_CAPF_MAX_LINE_WIDTH:
  280.    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
  281.       return 10.0f;
  282.    case PIPE_CAPF_MAX_POINT_WIDTH:
  283.       return 63.0f;
  284.    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
  285.       return 63.375f;
  286.    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
  287.       return 16.0f;
  288.    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
  289.       return 15.0f;
  290.    default:
  291.       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
  292.       return 0.0f;
  293.    }
  294. }
  295.  
  296. static int
  297. nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
  298.                               enum pipe_compute_cap param, void *data)
  299. {
  300.    uint64_t *data64 = (uint64_t *)data;
  301.    const uint16_t obj_class = nvc0_screen(pscreen)->compute->oclass;
  302.  
  303.    switch (param) {
  304.    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
  305.       data64[0] = 3;
  306.       return 8;
  307.    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
  308.       data64[0] = (obj_class >= NVE4_COMPUTE_CLASS) ? 0x7fffffff : 65535;
  309.       data64[1] = 65535;
  310.       data64[2] = 65535;
  311.       return 24;
  312.    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
  313.       data64[0] = 1024;
  314.       data64[1] = 1024;
  315.       data64[2] = 64;
  316.       return 24;
  317.    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
  318.       data64[0] = 1024;
  319.       return 8;
  320.    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
  321.       data64[0] = (uint64_t)1 << 40;
  322.       return 8;
  323.    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
  324.       data64[0] = 48 << 10;
  325.       return 8;
  326.    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
  327.       data64[0] = 512 << 10;
  328.       return 8;
  329.    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
  330.       data64[0] = 4096;
  331.       return 8;
  332.    default:
  333.       return 0;
  334.    }
  335. }
  336.  
  337. static void
  338. nvc0_screen_destroy(struct pipe_screen *pscreen)
  339. {
  340.    struct nvc0_screen *screen = nvc0_screen(pscreen);
  341.  
  342.    if (screen->base.fence.current) {
  343.       nouveau_fence_wait(screen->base.fence.current);
  344.       nouveau_fence_ref(NULL, &screen->base.fence.current);
  345.    }
  346.    if (screen->base.pushbuf)
  347.       screen->base.pushbuf->user_priv = NULL;
  348.  
  349.    if (screen->blitter)
  350.       nvc0_blitter_destroy(screen);
  351.    if (screen->pm.prog) {
  352.       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
  353.       nvc0_program_destroy(NULL, screen->pm.prog);
  354.    }
  355.  
  356.    nouveau_bo_ref(NULL, &screen->text);
  357.    nouveau_bo_ref(NULL, &screen->uniform_bo);
  358.    nouveau_bo_ref(NULL, &screen->tls);
  359.    nouveau_bo_ref(NULL, &screen->txc);
  360.    nouveau_bo_ref(NULL, &screen->fence.bo);
  361.    nouveau_bo_ref(NULL, &screen->poly_cache);
  362.    nouveau_bo_ref(NULL, &screen->parm);
  363.  
  364.    nouveau_heap_destroy(&screen->lib_code);
  365.    nouveau_heap_destroy(&screen->text_heap);
  366.  
  367.    FREE(screen->tic.entries);
  368.  
  369.    nouveau_mm_destroy(screen->mm_VRAM_fe0);
  370.  
  371.    nouveau_object_del(&screen->eng3d);
  372.    nouveau_object_del(&screen->eng2d);
  373.    nouveau_object_del(&screen->m2mf);
  374.    nouveau_object_del(&screen->compute);
  375.  
  376.    nouveau_screen_fini(&screen->base);
  377.  
  378.    FREE(screen);
  379. }
  380.  
  381. static int
  382. nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
  383.                      unsigned size, const uint32_t *data)
  384. {
  385.    struct nouveau_pushbuf *push = screen->base.pushbuf;
  386.  
  387.    size /= 4;
  388.  
  389.    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
  390.    PUSH_DATA (push, (m - 0x3800) / 8);
  391.    PUSH_DATA (push, pos);
  392.    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
  393.    PUSH_DATA (push, pos);
  394.    PUSH_DATAp(push, data, size);
  395.  
  396.    return pos + size;
  397. }
  398.  
  399. static void
  400. nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
  401. {
  402.    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
  403.    PUSH_DATA (push, 0xff);
  404.    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
  405.    PUSH_DATA (push, 0xff);
  406.    PUSH_DATA (push, 0xff);
  407.    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
  408.    PUSH_DATA (push, 0xff);
  409.    PUSH_DATA (push, 0xff);
  410.    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
  411.    PUSH_DATA (push, 0x3f);
  412.  
  413.    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
  414.    PUSH_DATA (push, (3 << 16) | 3);
  415.    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
  416.    PUSH_DATA (push, (2 << 16) | 2);
  417.    BEGIN_NVC0(push, SUBC_3D(0x0de8), 1);
  418.    PUSH_DATA (push, 1);
  419.  
  420.    BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
  421.    PUSH_DATA (push, 0);
  422.    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
  423.    PUSH_DATA (push, 0x10);
  424.    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
  425.    PUSH_DATA (push, 0x10);
  426.    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
  427.    PUSH_DATA (push, 0x10);
  428.    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
  429.    PUSH_DATA (push, 0x10);
  430.    PUSH_DATA (push, 0x10);
  431.    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
  432.    PUSH_DATA (push, 0x10);
  433.    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
  434.    PUSH_DATA (push, 0xe);
  435.  
  436.    BEGIN_NVC0(push, SUBC_3D(0x164c), 1);
  437.    PUSH_DATA (push, 1 << 12);
  438.    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
  439.    PUSH_DATA (push, 0);
  440.    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
  441.    PUSH_DATA (push, 3);
  442.  
  443.    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
  444.    PUSH_DATA (push, 0x3fffff);
  445.    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
  446.    PUSH_DATA (push, 1);
  447.    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
  448.    PUSH_DATA (push, 1);
  449.    BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
  450.    PUSH_DATA (push, 3);
  451.  
  452.    if (obj_class >= NVE4_3D_CLASS) {
  453.       BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
  454.       PUSH_DATA (push, 1);
  455.    }
  456.  
  457.    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
  458.     * are supposed to do */
  459. }
  460.  
  461. static void
  462. nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
  463. {
  464.    struct nvc0_screen *screen = nvc0_screen(pscreen);
  465.    struct nouveau_pushbuf *push = screen->base.pushbuf;
  466.  
  467.    /* we need to do it after possible flush in MARK_RING */
  468.    *sequence = ++screen->base.fence.sequence;
  469.  
  470.    BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);
  471.    PUSH_DATAh(push, screen->fence.bo->offset);
  472.    PUSH_DATA (push, screen->fence.bo->offset);
  473.    PUSH_DATA (push, *sequence);
  474.    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
  475.               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
  476. }
  477.  
  478. static u32
  479. nvc0_screen_fence_update(struct pipe_screen *pscreen)
  480. {
  481.    struct nvc0_screen *screen = nvc0_screen(pscreen);
  482.    return screen->fence.map[0];
  483. }
  484.  
  485. static int
  486. nvc0_screen_init_compute(struct nvc0_screen *screen)
  487. {
  488.    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
  489.  
  490.    switch (screen->base.device->chipset & 0xf0) {
  491.    case 0xc0:
  492.    case 0xd0:
  493.       return 0;
  494.    case 0xe0:
  495.    case 0xf0:
  496.       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
  497.    default:
  498.       return -1;
  499.    }
  500. }
  501.  
  502. boolean
  503. nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
  504.                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
  505. {
  506.    struct nouveau_bo *bo = NULL;
  507.    int ret;
  508.    uint64_t size = (lpos + lneg) * 32 + cstack;
  509.  
  510.    if (size >= (1 << 20)) {
  511.       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
  512.       return FALSE;
  513.    }
  514.  
  515.    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
  516.    size  = align(size, 0x8000);
  517.    size *= screen->mp_count;
  518.  
  519.    size = align(size, 1 << 17);
  520.  
  521.    ret = nouveau_bo_new(screen->base.device, NOUVEAU_BO_VRAM, 1 << 17, size,
  522.                         NULL, &bo);
  523.    if (ret) {
  524.       NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
  525.       return FALSE;
  526.    }
  527.    nouveau_bo_ref(NULL, &screen->tls);
  528.    screen->tls = bo;
  529.    return TRUE;
  530. }
  531.  
  532. #define FAIL_SCREEN_INIT(str, err)                    \
  533.    do {                                               \
  534.       NOUVEAU_ERR(str, err);                          \
  535.       nvc0_screen_destroy(pscreen);                   \
  536.       return NULL;                                    \
  537.    } while(0)
  538.  
  539. struct pipe_screen *
  540. nvc0_screen_create(struct nouveau_device *dev)
  541. {
  542.    struct nvc0_screen *screen;
  543.    struct pipe_screen *pscreen;
  544.    struct nouveau_object *chan;
  545.    struct nouveau_pushbuf *push;
  546.    uint64_t value;
  547.    uint32_t obj_class;
  548.    int ret;
  549.    unsigned i;
  550.    union nouveau_bo_config mm_config;
  551.  
  552.    switch (dev->chipset & ~0xf) {
  553.    case 0xc0:
  554.    case 0xd0:
  555.    case 0xe0:
  556.    case 0xf0:
  557.       break;
  558.    default:
  559.       return NULL;
  560.    }
  561.  
  562.    screen = CALLOC_STRUCT(nvc0_screen);
  563.    if (!screen)
  564.       return NULL;
  565.    pscreen = &screen->base.base;
  566.  
  567.    ret = nouveau_screen_init(&screen->base, dev);
  568.    if (ret) {
  569.       nvc0_screen_destroy(pscreen);
  570.       return NULL;
  571.    }
  572.    chan = screen->base.channel;
  573.    push = screen->base.pushbuf;
  574.    push->user_priv = screen;
  575.    push->rsvd_kick = 5;
  576.  
  577.    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
  578.       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
  579.    screen->base.sysmem_bindings |=
  580.       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
  581.  
  582.    pscreen->destroy = nvc0_screen_destroy;
  583.    pscreen->context_create = nvc0_create;
  584.    pscreen->is_format_supported = nvc0_screen_is_format_supported;
  585.    pscreen->get_param = nvc0_screen_get_param;
  586.    pscreen->get_shader_param = nvc0_screen_get_shader_param;
  587.    pscreen->get_paramf = nvc0_screen_get_paramf;
  588.    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
  589.  
  590.    nvc0_screen_init_resource_functions(pscreen);
  591.  
  592.    screen->base.base.get_video_param = nvc0_screen_get_video_param;
  593.    screen->base.base.is_video_format_supported = nvc0_screen_video_supported;
  594.  
  595.    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL,
  596.                         &screen->fence.bo);
  597.    if (ret)
  598.       goto fail;
  599.    nouveau_bo_map(screen->fence.bo, 0, NULL);
  600.    screen->fence.map = screen->fence.bo->map;
  601.    screen->base.fence.emit = nvc0_screen_fence_emit;
  602.    screen->base.fence.update = nvc0_screen_fence_update;
  603.  
  604.    switch (dev->chipset & 0xf0) {
  605.    case 0xf0:
  606.       obj_class = NVF0_P2MF_CLASS;
  607.       break;
  608.    case 0xe0:
  609.       obj_class = NVE4_P2MF_CLASS;
  610.       break;
  611.    default:
  612.       obj_class = NVC0_M2MF_CLASS;
  613.       break;
  614.    }
  615.    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
  616.                             &screen->m2mf);
  617.    if (ret)
  618.       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
  619.  
  620.    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
  621.    PUSH_DATA (push, screen->m2mf->oclass);
  622.    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
  623.       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
  624.       PUSH_DATA (push, 0xa0b5);
  625.    }
  626.  
  627.    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
  628.                             &screen->eng2d);
  629.    if (ret)
  630.       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
  631.  
  632.    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
  633.    PUSH_DATA (push, screen->eng2d->oclass);
  634.    BEGIN_NVC0(push, NVC0_2D(SINGLE_GPC), 1);
  635.    PUSH_DATA (push, 0);
  636.    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
  637.    PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY);
  638.    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
  639.    PUSH_DATA (push, 0);
  640.    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
  641.    PUSH_DATA (push, 0);
  642.    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
  643.    PUSH_DATA (push, 0x3f);
  644.    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
  645.    PUSH_DATA (push, 1);
  646.  
  647.    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
  648.    PUSH_DATAh(push, screen->fence.bo->offset + 16);
  649.    PUSH_DATA (push, screen->fence.bo->offset + 16);
  650.  
  651.    switch (dev->chipset & 0xf0) {
  652.    case 0xf0:
  653.       obj_class = NVF0_3D_CLASS;
  654.       break;
  655.    case 0xe0:
  656.       obj_class = NVE4_3D_CLASS;
  657.       break;
  658.    case 0xd0:
  659.    case 0xc0:
  660.    default:
  661.       switch (dev->chipset) {
  662.       case 0xd9:
  663.       case 0xc8:
  664.          obj_class = NVC8_3D_CLASS;
  665.          break;
  666.       case 0xc1:
  667.          obj_class = NVC1_3D_CLASS;
  668.          break;
  669.       default:
  670.          obj_class = NVC0_3D_CLASS;
  671.          break;
  672.       }
  673.       break;
  674.    }
  675.    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
  676.                             &screen->eng3d);
  677.    if (ret)
  678.       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
  679.    screen->base.class_3d = obj_class;
  680.  
  681.    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
  682.    PUSH_DATA (push, screen->eng3d->oclass);
  683.  
  684.    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
  685.    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
  686.  
  687.    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
  688.       /* kill shaders after about 1 second (at 100 MHz) */
  689.       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
  690.       PUSH_DATA (push, 0x17);
  691.    }
  692.  
  693.    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE), dev->drm_version >= 0x01000101);
  694.    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
  695.    for (i = 0; i < 8; ++i)
  696.            PUSH_DATA(push, dev->drm_version >= 0x01000101);
  697.  
  698.    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
  699.    PUSH_DATA (push, 1);
  700.  
  701.    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
  702.    PUSH_DATA (push, 0);
  703.    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
  704.    PUSH_DATA (push, 0);
  705.    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
  706.    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
  707.    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
  708.    PUSH_DATA (push, 0);
  709.    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
  710.    PUSH_DATA (push, 1);
  711.    BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1);
  712.    PUSH_DATA (push, 0);
  713.    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
  714.    PUSH_DATA (push, 1);
  715.    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
  716.    PUSH_DATA (push, 0);
  717.    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
  718.       BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
  719.       PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
  720.    } else {
  721.       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
  722.       PUSH_DATA (push, 15);
  723.    }
  724.    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
  725.    PUSH_DATA (push, 8); /* 128 */
  726.    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
  727.    PUSH_DATA (push, 1);
  728.    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
  729.       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
  730.       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
  731.    }
  732.  
  733.    nvc0_magic_3d_init(push, screen->eng3d->oclass);
  734.  
  735.    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
  736.                         &screen->text);
  737.    if (ret)
  738.       goto fail;
  739.  
  740.    /* XXX: getting a page fault at the end of the code buffer every few
  741.     *  launches, don't use the last 256 bytes to work around them - prefetch ?
  742.     */
  743.    nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
  744.  
  745.    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
  746.                         &screen->uniform_bo);
  747.    if (ret)
  748.       goto fail;
  749.  
  750.    for (i = 0; i < 5; ++i) {
  751.       /* TIC and TSC entries for each unit (nve4+ only) */
  752.       /* auxiliary constants (6 user clip planes, base instance id) */
  753.       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
  754.       PUSH_DATA (push, 512);
  755.       PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
  756.       PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
  757.       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
  758.       PUSH_DATA (push, (15 << 4) | 1);
  759.       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
  760.          unsigned j;
  761.          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
  762.          PUSH_DATA (push, 0);
  763.          for (j = 0; j < 8; ++j)
  764.             PUSH_DATA(push, j);
  765.       } else {
  766.          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
  767.          PUSH_DATA (push, 0x54);
  768.       }
  769.    }
  770.    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
  771.    PUSH_DATA (push, 0);
  772.  
  773.    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
  774.    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
  775.    PUSH_DATA (push, 256);
  776.    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
  777.    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
  778.    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
  779.    PUSH_DATA (push, 0);
  780.    PUSH_DATAf(push, 0.0f);
  781.    PUSH_DATAf(push, 0.0f);
  782.    PUSH_DATAf(push, 0.0f);
  783.    PUSH_DATAf(push, 0.0f);
  784.    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
  785.    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
  786.    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
  787.  
  788.    if (dev->drm_version >= 0x01000101) {
  789.       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
  790.       if (ret) {
  791.          NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
  792.          goto fail;
  793.       }
  794.    } else {
  795.       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
  796.          value = (8 << 8) | 4;
  797.       else
  798.          value = (16 << 8) | 4;
  799.    }
  800.    screen->mp_count = value >> 8;
  801.    screen->mp_count_compute = screen->mp_count;
  802.  
  803.    nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
  804.  
  805.    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
  806.    PUSH_DATAh(push, screen->text->offset);
  807.    PUSH_DATA (push, screen->text->offset);
  808.    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
  809.    PUSH_DATAh(push, screen->tls->offset);
  810.    PUSH_DATA (push, screen->tls->offset);
  811.    PUSH_DATA (push, screen->tls->size >> 32);
  812.    PUSH_DATA (push, screen->tls->size);
  813.    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
  814.    PUSH_DATA (push, 0);
  815.    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
  816.    PUSH_DATA (push, 0);
  817.  
  818.    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
  819.                         &screen->poly_cache);
  820.    if (ret)
  821.       goto fail;
  822.  
  823.    BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
  824.    PUSH_DATAh(push, screen->poly_cache->offset);
  825.    PUSH_DATA (push, screen->poly_cache->offset);
  826.    PUSH_DATA (push, 3);
  827.  
  828.    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL,
  829.                         &screen->txc);
  830.    if (ret)
  831.       goto fail;
  832.  
  833.    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
  834.    PUSH_DATAh(push, screen->txc->offset);
  835.    PUSH_DATA (push, screen->txc->offset);
  836.    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
  837.  
  838.    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
  839.    PUSH_DATAh(push, screen->txc->offset + 65536);
  840.    PUSH_DATA (push, screen->txc->offset + 65536);
  841.    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
  842.  
  843.    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
  844.    PUSH_DATA (push, 0);
  845.    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
  846.    PUSH_DATA (push, 0);
  847.    PUSH_DATA (push, 0);
  848.    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
  849.    PUSH_DATA (push, 0x3f);
  850.  
  851.    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
  852.    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
  853.    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
  854.    for (i = 0; i < 8 * 2; ++i)
  855.       PUSH_DATA(push, 0);
  856.    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
  857.    PUSH_DATA (push, 0);
  858.    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
  859.    PUSH_DATA (push, 0);
  860.  
  861.    /* neither scissors, viewport nor stencil mask should affect clears */
  862.    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
  863.    PUSH_DATA (push, 0);
  864.  
  865.    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
  866.    PUSH_DATA (push, 1);
  867.    BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2);
  868.    PUSH_DATAf(push, 0.0f);
  869.    PUSH_DATAf(push, 1.0f);
  870.    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
  871.    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
  872.  
  873.    /* We use scissors instead of exact view volume clipping,
  874.     * so they're always enabled.
  875.     */
  876.    BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(0)), 3);
  877.    PUSH_DATA (push, 1);
  878.    PUSH_DATA (push, 8192 << 16);
  879.    PUSH_DATA (push, 8192 << 16);
  880.  
  881. #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
  882.  
  883.    i = 0;
  884.    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, nvc0_9097_per_instance_bf);
  885.    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, nvc0_9097_blend_enables);
  886.    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select);
  887.    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, nvc0_9097_tep_select);
  888.    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, nvc0_9097_gp_select);
  889.    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front);
  890.    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back);
  891.  
  892.    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
  893.    PUSH_DATA (push, 1);
  894.    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
  895.    PUSH_DATA (push, 1);
  896.    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
  897.    PUSH_DATA (push, 0x40);
  898.    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
  899.    PUSH_DATA (push, 0);
  900.    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
  901.    PUSH_DATA (push, 0x30);
  902.    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
  903.    PUSH_DATA (push, 3);
  904.    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
  905.    PUSH_DATA (push, 0x20);
  906.    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
  907.    PUSH_DATA (push, 0x00);
  908.  
  909.    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
  910.    PUSH_DATA (push, 0);
  911.    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
  912.    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
  913.  
  914.    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
  915.  
  916.    if (nvc0_screen_init_compute(screen))
  917.       goto fail;
  918.  
  919.    PUSH_KICK (push);
  920.  
  921.    screen->tic.entries = CALLOC(4096, sizeof(void *));
  922.    screen->tsc.entries = screen->tic.entries + 2048;
  923.  
  924.    mm_config.nvc0.tile_mode = 0;
  925.    mm_config.nvc0.memtype = 0xfe0;
  926.    screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config);
  927.  
  928.    if (!nvc0_blitter_create(screen))
  929.       goto fail;
  930.  
  931.    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
  932.  
  933.    return pscreen;
  934.  
  935. fail:
  936.    nvc0_screen_destroy(pscreen);
  937.    return NULL;
  938. }
  939.  
  940. int
  941. nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
  942. {
  943.    int i = screen->tic.next;
  944.  
  945.    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
  946.       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
  947.  
  948.    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
  949.  
  950.    if (screen->tic.entries[i])
  951.       nv50_tic_entry(screen->tic.entries[i])->id = -1;
  952.  
  953.    screen->tic.entries[i] = entry;
  954.    return i;
  955. }
  956.  
  957. int
  958. nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
  959. {
  960.    int i = screen->tsc.next;
  961.  
  962.    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
  963.       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
  964.  
  965.    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
  966.  
  967.    if (screen->tsc.entries[i])
  968.       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
  969.  
  970.    screen->tsc.entries[i] = entry;
  971.    return i;
  972. }
  973.