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  1. /*
  2.  * Copyright 2010 Christoph Bumiller
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice shall be included in
  12.  * all copies or substantial portions of the Software.
  13.  *
  14.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20.  * OTHER DEALINGS IN THE SOFTWARE.
  21.  */
  22.  
  23. #include "pipe/p_context.h"
  24. #include "pipe/p_state.h"
  25. #include "util/u_inlines.h"
  26. #include "util/u_format.h"
  27. #include "translate/translate.h"
  28.  
  29. #include "nv50_context.h"
  30. #include "nv50_resource.h"
  31.  
  32. #include "nv50_3d.xml.h"
  33.  
  34. void
  35. nv50_vertex_state_delete(struct pipe_context *pipe,
  36.                          void *hwcso)
  37. {
  38.    struct nv50_vertex_stateobj *so = hwcso;
  39.  
  40.    if (so->translate)
  41.       so->translate->release(so->translate);
  42.    FREE(hwcso);
  43. }
  44.  
  45. void *
  46. nv50_vertex_state_create(struct pipe_context *pipe,
  47.                          unsigned num_elements,
  48.                          const struct pipe_vertex_element *elements)
  49. {
  50.     struct nv50_vertex_stateobj *so;
  51.     struct translate_key transkey;
  52.     unsigned i;
  53.  
  54.     so = MALLOC(sizeof(*so) +
  55.                 num_elements * sizeof(struct nv50_vertex_element));
  56.     if (!so)
  57.         return NULL;
  58.     so->num_elements = num_elements;
  59.     so->instance_elts = 0;
  60.     so->instance_bufs = 0;
  61.     so->need_conversion = FALSE;
  62.  
  63.     memset(so->vb_access_size, 0, sizeof(so->vb_access_size));
  64.  
  65.     for (i = 0; i < PIPE_MAX_ATTRIBS; ++i)
  66.        so->min_instance_div[i] = 0xffffffff;
  67.  
  68.     transkey.nr_elements = 0;
  69.     transkey.output_stride = 0;
  70.  
  71.     for (i = 0; i < num_elements; ++i) {
  72.         const struct pipe_vertex_element *ve = &elements[i];
  73.         const unsigned vbi = ve->vertex_buffer_index;
  74.         unsigned size;
  75.         enum pipe_format fmt = ve->src_format;
  76.  
  77.         so->element[i].pipe = elements[i];
  78.         so->element[i].state = nv50_format_table[fmt].vtx;
  79.  
  80.         if (!so->element[i].state) {
  81.             switch (util_format_get_nr_components(fmt)) {
  82.             case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
  83.             case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
  84.             case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
  85.             case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
  86.             default:
  87.                 assert(0);
  88.                 FREE(so);
  89.                 return NULL;
  90.             }
  91.             so->element[i].state = nv50_format_table[fmt].vtx;
  92.             so->need_conversion = TRUE;
  93.         }
  94.         so->element[i].state |= i;
  95.  
  96.         size = util_format_get_blocksize(fmt);
  97.         if (so->vb_access_size[vbi] < (ve->src_offset + size))
  98.            so->vb_access_size[vbi] = ve->src_offset + size;
  99.  
  100.         if (1) {
  101.             unsigned j = transkey.nr_elements++;
  102.  
  103.             transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
  104.             transkey.element[j].input_format = ve->src_format;
  105.             transkey.element[j].input_buffer = vbi;
  106.             transkey.element[j].input_offset = ve->src_offset;
  107.             transkey.element[j].instance_divisor = ve->instance_divisor;
  108.  
  109.             transkey.element[j].output_format = fmt;
  110.             transkey.element[j].output_offset = transkey.output_stride;
  111.             transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3;
  112.  
  113.             if (unlikely(ve->instance_divisor)) {
  114.                so->instance_elts |= 1 << i;
  115.                so->instance_bufs |= 1 << vbi;
  116.                if (ve->instance_divisor < so->min_instance_div[vbi])
  117.                   so->min_instance_div[vbi] = ve->instance_divisor;
  118.             }
  119.         }
  120.     }
  121.  
  122.     so->translate = translate_create(&transkey);
  123.     so->vertex_size = transkey.output_stride / 4;
  124.     so->packet_vertex_limit = NV04_PFIFO_MAX_PACKET_LEN /
  125.        MAX2(so->vertex_size, 1);
  126.  
  127.     return so;
  128. }
  129.  
  130. #define NV50_3D_VERTEX_ATTRIB_INACTIVE              \
  131.    NV50_3D_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT |         \
  132.    NV50_3D_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32 | \
  133.    NV50_3D_VERTEX_ARRAY_ATTRIB_CONST
  134.  
  135. static void
  136. nv50_emit_vtxattr(struct nv50_context *nv50, struct pipe_vertex_buffer *vb,
  137.                   struct pipe_vertex_element *ve, unsigned attr)
  138. {
  139.    struct nouveau_pushbuf *push = nv50->base.pushbuf;
  140.    const void *data = (const uint8_t *)vb->user_buffer + ve->src_offset;
  141.    float v[4];
  142.    const unsigned nc = util_format_get_nr_components(ve->src_format);
  143.    const struct util_format_description *desc =
  144.       util_format_description(ve->src_format);
  145.  
  146.    assert(vb->user_buffer);
  147.  
  148.    if (desc->channel[0].pure_integer) {
  149.       if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) {
  150.          desc->unpack_rgba_sint((int32_t *)v, 0, data, 0, 1, 1);
  151.       } else {
  152.          desc->unpack_rgba_uint((uint32_t *)v, 0, data, 0, 1, 1);
  153.       }
  154.    } else {
  155.       desc->unpack_rgba_float(v, 0, data, 0, 1, 1);
  156.    }
  157.  
  158.    switch (nc) {
  159.    case 4:
  160.       BEGIN_NV04(push, NV50_3D(VTX_ATTR_4F_X(attr)), 4);
  161.       PUSH_DATAf(push, v[0]);
  162.       PUSH_DATAf(push, v[1]);
  163.       PUSH_DATAf(push, v[2]);
  164.       PUSH_DATAf(push, v[3]);
  165.       break;
  166.    case 3:
  167.       BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(attr)), 3);
  168.       PUSH_DATAf(push, v[0]);
  169.       PUSH_DATAf(push, v[1]);
  170.       PUSH_DATAf(push, v[2]);
  171.       break;
  172.    case 2:
  173.       BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(attr)), 2);
  174.       PUSH_DATAf(push, v[0]);
  175.       PUSH_DATAf(push, v[1]);
  176.       break;
  177.    case 1:
  178.       if (attr == nv50->vertprog->vp.edgeflag) {
  179.          BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
  180.          PUSH_DATA (push, v[0] ? 1 : 0);
  181.       }
  182.       BEGIN_NV04(push, NV50_3D(VTX_ATTR_1F(attr)), 1);
  183.       PUSH_DATAf(push, v[0]);
  184.       break;
  185.    default:
  186.       assert(0);
  187.       break;
  188.    }
  189. }
  190.  
  191. static INLINE void
  192. nv50_user_vbuf_range(struct nv50_context *nv50, int vbi,
  193.                      uint32_t *base, uint32_t *size)
  194. {
  195.    if (unlikely(nv50->vertex->instance_bufs & (1 << vbi))) {
  196.       /* TODO: use min and max instance divisor to get a proper range */
  197.       *base = 0;
  198.       *size = nv50->vtxbuf[vbi].buffer->width0;
  199.    } else {
  200.       /* NOTE: if there are user buffers, we *must* have index bounds */
  201.       assert(nv50->vb_elt_limit != ~0);
  202.       *base = nv50->vb_elt_first * nv50->vtxbuf[vbi].stride;
  203.       *size = nv50->vb_elt_limit * nv50->vtxbuf[vbi].stride +
  204.          nv50->vertex->vb_access_size[vbi];
  205.    }
  206. }
  207.  
  208. static void
  209. nv50_upload_user_buffers(struct nv50_context *nv50,
  210.                          uint64_t addrs[], uint32_t limits[])
  211. {
  212.    unsigned b;
  213.  
  214.    for (b = 0; b < nv50->num_vtxbufs; ++b) {
  215.       struct nouveau_bo *bo;
  216.       const struct pipe_vertex_buffer *vb = &nv50->vtxbuf[b];
  217.       uint32_t base, size;
  218.  
  219.       if (!(nv50->vbo_user & (1 << b)) || !vb->stride)
  220.          continue;
  221.       nv50_user_vbuf_range(nv50, b, &base, &size);
  222.  
  223.       limits[b] = base + size - 1;
  224.       addrs[b] = nouveau_scratch_data(&nv50->base, vb->user_buffer, base, size,
  225.                                       &bo);
  226.       if (addrs[b])
  227.          BCTX_REFN_bo(nv50->bufctx_3d, VERTEX_TMP, NOUVEAU_BO_GART |
  228.                       NOUVEAU_BO_RD, bo);
  229.    }
  230.    nv50->base.vbo_dirty = TRUE;
  231. }
  232.  
  233. static void
  234. nv50_update_user_vbufs(struct nv50_context *nv50)
  235. {
  236.    uint64_t address[PIPE_MAX_ATTRIBS];
  237.    struct nouveau_pushbuf *push = nv50->base.pushbuf;
  238.    unsigned i;
  239.    uint32_t written = 0;
  240.  
  241.    for (i = 0; i < nv50->vertex->num_elements; ++i) {
  242.       struct pipe_vertex_element *ve = &nv50->vertex->element[i].pipe;
  243.       const unsigned b = ve->vertex_buffer_index;
  244.       struct pipe_vertex_buffer *vb = &nv50->vtxbuf[b];
  245.       uint32_t base, size;
  246.  
  247.       if (!(nv50->vbo_user & (1 << b)))
  248.          continue;
  249.  
  250.       if (!vb->stride) {
  251.          nv50_emit_vtxattr(nv50, vb, ve, i);
  252.          continue;
  253.       }
  254.       nv50_user_vbuf_range(nv50, b, &base, &size);
  255.  
  256.       if (!(written & (1 << b))) {
  257.          struct nouveau_bo *bo;
  258.          const uint32_t bo_flags = NOUVEAU_BO_GART | NOUVEAU_BO_RD;
  259.          written |= 1 << b;
  260.          address[b] = nouveau_scratch_data(&nv50->base, vb->user_buffer,
  261.                                            base, size, &bo);
  262.          if (address[b])
  263.             BCTX_REFN_bo(nv50->bufctx_3d, VERTEX_TMP, bo_flags, bo);
  264.       }
  265.  
  266.       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
  267.       PUSH_DATAh(push, address[b] + base + size - 1);
  268.       PUSH_DATA (push, address[b] + base + size - 1);
  269.       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_START_HIGH(i)), 2);
  270.       PUSH_DATAh(push, address[b] + ve->src_offset);
  271.       PUSH_DATA (push, address[b] + ve->src_offset);
  272.    }
  273.    nv50->base.vbo_dirty = TRUE;
  274. }
  275.  
  276. static INLINE void
  277. nv50_release_user_vbufs(struct nv50_context *nv50)
  278. {
  279.    if (nv50->vbo_user) {
  280.       nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_VERTEX_TMP);
  281.       nouveau_scratch_done(&nv50->base);
  282.    }
  283. }
  284.  
  285. void
  286. nv50_vertex_arrays_validate(struct nv50_context *nv50)
  287. {
  288.    uint64_t addrs[PIPE_MAX_ATTRIBS];
  289.    uint32_t limits[PIPE_MAX_ATTRIBS];
  290.    struct nouveau_pushbuf *push = nv50->base.pushbuf;
  291.    struct nv50_vertex_stateobj *vertex = nv50->vertex;
  292.    struct pipe_vertex_buffer *vb;
  293.    struct nv50_vertex_element *ve;
  294.    uint32_t mask;
  295.    uint32_t refd = 0;
  296.    unsigned i;
  297.    const unsigned n = MAX2(vertex->num_elements, nv50->state.num_vtxelts);
  298.  
  299.    if (unlikely(vertex->need_conversion))
  300.       nv50->vbo_fifo = ~0;
  301.    else
  302.    if (nv50->vbo_user & ~nv50->vbo_constant)
  303.       nv50->vbo_fifo = nv50->vbo_push_hint ? ~0 : 0;
  304.    else
  305.       nv50->vbo_fifo = 0;
  306.  
  307.    if (!nv50->vbo_fifo) {
  308.       /* if vertex buffer was written by GPU - flush VBO cache */
  309.       for (i = 0; i < nv50->num_vtxbufs; ++i) {
  310.          struct nv04_resource *buf = nv04_resource(nv50->vtxbuf[i].buffer);
  311.          if (buf && buf->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
  312.             buf->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
  313.             nv50->base.vbo_dirty = TRUE;
  314.             break;
  315.          }
  316.       }
  317.    }
  318.  
  319.    /* update vertex format state */
  320.    BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_ATTRIB(0)), n);
  321.    if (nv50->vbo_fifo) {
  322.       nv50->state.num_vtxelts = vertex->num_elements;
  323.       for (i = 0; i < vertex->num_elements; ++i)
  324.          PUSH_DATA (push, vertex->element[i].state);
  325.       for (; i < n; ++i)
  326.          PUSH_DATA (push, NV50_3D_VERTEX_ATTRIB_INACTIVE);
  327.       for (i = 0; i < n; ++i) {
  328.          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
  329.          PUSH_DATA (push, 0);
  330.       }
  331.       return;
  332.    }
  333.    for (i = 0; i < vertex->num_elements; ++i) {
  334.       const unsigned b = vertex->element[i].pipe.vertex_buffer_index;
  335.       ve = &vertex->element[i];
  336.       vb = &nv50->vtxbuf[b];
  337.  
  338.       if (likely(vb->stride) || !(nv50->vbo_user & (1 << b)))
  339.          PUSH_DATA(push, ve->state);
  340.       else
  341.          PUSH_DATA(push, ve->state | NV50_3D_VERTEX_ARRAY_ATTRIB_CONST);
  342.    }
  343.    for (; i < n; ++i)
  344.       PUSH_DATA(push, NV50_3D_VERTEX_ATTRIB_INACTIVE);
  345.  
  346.    /* update per-instance enables */
  347.    mask = vertex->instance_elts ^ nv50->state.instance_elts;
  348.    while (mask) {
  349.       const int i = ffs(mask) - 1;
  350.       mask &= ~(1 << i);
  351.       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1);
  352.       PUSH_DATA (push, (vertex->instance_elts >> i) & 1);
  353.    }
  354.    nv50->state.instance_elts = vertex->instance_elts;
  355.  
  356.    if (nv50->vbo_user & ~nv50->vbo_constant)
  357.       nv50_upload_user_buffers(nv50, addrs, limits);
  358.  
  359.    /* update buffers and set constant attributes */
  360.    for (i = 0; i < vertex->num_elements; ++i) {
  361.       uint64_t address, limit;
  362.       const unsigned b = vertex->element[i].pipe.vertex_buffer_index;
  363.       ve = &vertex->element[i];
  364.       vb = &nv50->vtxbuf[b];
  365.  
  366.       if (unlikely(nv50->vbo_constant & (1 << b))) {
  367.          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
  368.          PUSH_DATA (push, 0);
  369.          nv50_emit_vtxattr(nv50, vb, &ve->pipe, i);
  370.          continue;
  371.       } else
  372.       if (nv50->vbo_user & (1 << b)) {
  373.          address = addrs[b] + ve->pipe.src_offset;
  374.          limit = addrs[b] + limits[b];
  375.       } else {
  376.          struct nv04_resource *buf = nv04_resource(vb->buffer);
  377.          if (!(refd & (1 << b))) {
  378.             refd |= 1 << b;
  379.             BCTX_REFN(nv50->bufctx_3d, VERTEX, buf, RD);
  380.          }
  381.          address = buf->address + vb->buffer_offset + ve->pipe.src_offset;
  382.          limit = buf->address + buf->base.width0 - 1;
  383.       }
  384.  
  385.       if (unlikely(ve->pipe.instance_divisor)) {
  386.          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 4);
  387.          PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
  388.          PUSH_DATAh(push, address);
  389.          PUSH_DATA (push, address);
  390.          PUSH_DATA (push, ve->pipe.instance_divisor);
  391.       } else {
  392.          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 3);
  393.          PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
  394.          PUSH_DATAh(push, address);
  395.          PUSH_DATA (push, address);
  396.       }
  397.       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
  398.       PUSH_DATAh(push, limit);
  399.       PUSH_DATA (push, limit);
  400.    }
  401.    for (; i < nv50->state.num_vtxelts; ++i) {
  402.       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
  403.       PUSH_DATA (push, 0);
  404.    }
  405.    nv50->state.num_vtxelts = vertex->num_elements;
  406. }
  407.  
  408. #define NV50_PRIM_GL_CASE(n) \
  409.    case PIPE_PRIM_##n: return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
  410.  
  411. static INLINE unsigned
  412. nv50_prim_gl(unsigned prim)
  413. {
  414.    switch (prim) {
  415.    NV50_PRIM_GL_CASE(POINTS);
  416.    NV50_PRIM_GL_CASE(LINES);
  417.    NV50_PRIM_GL_CASE(LINE_LOOP);
  418.    NV50_PRIM_GL_CASE(LINE_STRIP);
  419.    NV50_PRIM_GL_CASE(TRIANGLES);
  420.    NV50_PRIM_GL_CASE(TRIANGLE_STRIP);
  421.    NV50_PRIM_GL_CASE(TRIANGLE_FAN);
  422.    NV50_PRIM_GL_CASE(QUADS);
  423.    NV50_PRIM_GL_CASE(QUAD_STRIP);
  424.    NV50_PRIM_GL_CASE(POLYGON);
  425.    NV50_PRIM_GL_CASE(LINES_ADJACENCY);
  426.    NV50_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
  427.    NV50_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
  428.    NV50_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
  429.    default:
  430.       return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
  431.       break;
  432.    }
  433. }
  434.  
  435. /* For pre-nva0 transform feedback. */
  436. static const uint8_t nv50_pipe_prim_to_prim_size[PIPE_PRIM_MAX + 1] =
  437. {
  438.    [PIPE_PRIM_POINTS] = 1,
  439.    [PIPE_PRIM_LINES] = 2,
  440.    [PIPE_PRIM_LINE_LOOP] = 2,
  441.    [PIPE_PRIM_LINE_STRIP] = 2,
  442.    [PIPE_PRIM_TRIANGLES] = 3,
  443.    [PIPE_PRIM_TRIANGLE_STRIP] = 3,
  444.    [PIPE_PRIM_TRIANGLE_FAN] = 3,
  445.    [PIPE_PRIM_QUADS] = 3,
  446.    [PIPE_PRIM_QUAD_STRIP] = 3,
  447.    [PIPE_PRIM_POLYGON] = 3,
  448.    [PIPE_PRIM_LINES_ADJACENCY] = 2,
  449.    [PIPE_PRIM_LINE_STRIP_ADJACENCY] = 2,
  450.    [PIPE_PRIM_TRIANGLES_ADJACENCY] = 3,
  451.    [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = 3
  452. };
  453.  
  454. static void
  455. nv50_draw_arrays(struct nv50_context *nv50,
  456.                  unsigned mode, unsigned start, unsigned count,
  457.                  unsigned instance_count)
  458. {
  459.    struct nouveau_pushbuf *push = nv50->base.pushbuf;
  460.    unsigned prim;
  461.  
  462.    if (nv50->state.index_bias) {
  463.       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
  464.       PUSH_DATA (push, 0);
  465.       nv50->state.index_bias = 0;
  466.    }
  467.  
  468.    prim = nv50_prim_gl(mode);
  469.  
  470.    while (instance_count--) {
  471.       BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
  472.       PUSH_DATA (push, prim);
  473.       BEGIN_NV04(push, NV50_3D(VERTEX_BUFFER_FIRST), 2);
  474.       PUSH_DATA (push, start);
  475.       PUSH_DATA (push, count);
  476.       BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
  477.       PUSH_DATA (push, 0);
  478.  
  479.       prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
  480.    }
  481. }
  482.  
  483. static void
  484. nv50_draw_elements_inline_u08(struct nouveau_pushbuf *push, const uint8_t *map,
  485.                               unsigned start, unsigned count)
  486. {
  487.    map += start;
  488.  
  489.    if (count & 3) {
  490.       unsigned i;
  491.       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), count & 3);
  492.       for (i = 0; i < (count & 3); ++i)
  493.          PUSH_DATA(push, *map++);
  494.       count &= ~3;
  495.    }
  496.    while (count) {
  497.       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
  498.  
  499.       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U8), nr);
  500.       for (i = 0; i < nr; ++i) {
  501.          PUSH_DATA(push,
  502.                    (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
  503.          map += 4;
  504.       }
  505.       count -= nr * 4;
  506.    }
  507. }
  508.  
  509. static void
  510. nv50_draw_elements_inline_u16(struct nouveau_pushbuf *push, const uint16_t *map,
  511.                               unsigned start, unsigned count)
  512. {
  513.    map += start;
  514.  
  515.    if (count & 1) {
  516.       count &= ~1;
  517.       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1);
  518.       PUSH_DATA (push, *map++);
  519.    }
  520.    while (count) {
  521.       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
  522.  
  523.       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr);
  524.       for (i = 0; i < nr; ++i) {
  525.          PUSH_DATA(push, (map[1] << 16) | map[0]);
  526.          map += 2;
  527.       }
  528.       count -= nr * 2;
  529.    }
  530. }
  531.  
  532. static void
  533. nv50_draw_elements_inline_u32(struct nouveau_pushbuf *push, const uint32_t *map,
  534.                               unsigned start, unsigned count)
  535. {
  536.    map += start;
  537.  
  538.    while (count) {
  539.       const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
  540.  
  541.       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), nr);
  542.       PUSH_DATAp(push, map, nr);
  543.  
  544.       map += nr;
  545.       count -= nr;
  546.    }
  547. }
  548.  
  549. static void
  550. nv50_draw_elements_inline_u32_short(struct nouveau_pushbuf *push,
  551.                                     const uint32_t *map,
  552.                                     unsigned start, unsigned count)
  553. {
  554.    map += start;
  555.  
  556.    if (count & 1) {
  557.       count--;
  558.       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1);
  559.       PUSH_DATA (push, *map++);
  560.    }
  561.    while (count) {
  562.       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
  563.  
  564.       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr);
  565.       for (i = 0; i < nr; ++i) {
  566.          PUSH_DATA(push, (map[1] << 16) | map[0]);
  567.          map += 2;
  568.       }
  569.       count -= nr * 2;
  570.    }
  571. }
  572.  
  573. static void
  574. nv50_draw_elements(struct nv50_context *nv50, boolean shorten,
  575.                    unsigned mode, unsigned start, unsigned count,
  576.                    unsigned instance_count, int32_t index_bias)
  577. {
  578.    struct nouveau_pushbuf *push = nv50->base.pushbuf;
  579.    unsigned prim;
  580.    const unsigned index_size = nv50->idxbuf.index_size;
  581.  
  582.    prim = nv50_prim_gl(mode);
  583.  
  584.    if (index_bias != nv50->state.index_bias) {
  585.       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
  586.       PUSH_DATA (push, index_bias);
  587.       nv50->state.index_bias = index_bias;
  588.    }
  589.  
  590.    if (nv50->idxbuf.buffer) {
  591.       struct nv04_resource *buf = nv04_resource(nv50->idxbuf.buffer);
  592.       unsigned pb_start;
  593.       unsigned pb_bytes;
  594.       const unsigned base = (buf->offset + nv50->idxbuf.offset) & ~3;
  595.  
  596.       start += ((buf->offset + nv50->idxbuf.offset) & 3) >> (index_size >> 1);
  597.  
  598.       assert(nouveau_resource_mapped_by_gpu(nv50->idxbuf.buffer));
  599.  
  600.       while (instance_count--) {
  601.          BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
  602.          PUSH_DATA (push, prim);
  603.  
  604.          nouveau_pushbuf_space(push, 8, 0, 1);
  605.  
  606.          switch (index_size) {
  607.          case 4:
  608.             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U32), count);
  609.             nouveau_pushbuf_data(push, buf->bo, base + start * 4, count * 4);
  610.             break;
  611.          case 2:
  612.             pb_start = (start & ~1) * 2;
  613.             pb_bytes = ((start + count + 1) & ~1) * 2 - pb_start;
  614.  
  615.             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1);
  616.             PUSH_DATA (push, (start << 31) | count);
  617.             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U16), pb_bytes / 4);
  618.             nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
  619.             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1);
  620.             PUSH_DATA (push, 0);
  621.             break;
  622.          default:
  623.             assert(index_size == 1);
  624.             pb_start = start & ~3;
  625.             pb_bytes = ((start + count + 3) & ~3) - pb_start;
  626.  
  627.             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1);
  628.             PUSH_DATA (push, (start << 30) | count);
  629.             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U8), pb_bytes / 4);
  630.             nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
  631.             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1);
  632.             PUSH_DATA (push, 0);
  633.             break;
  634.          }
  635.          BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
  636.          PUSH_DATA (push, 0);
  637.  
  638.          prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
  639.       }
  640.    } else {
  641.       const void *data = nv50->idxbuf.user_buffer;
  642.  
  643.       while (instance_count--) {
  644.          BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
  645.          PUSH_DATA (push, prim);
  646.          switch (index_size) {
  647.          case 1:
  648.             nv50_draw_elements_inline_u08(push, data, start, count);
  649.             break;
  650.          case 2:
  651.             nv50_draw_elements_inline_u16(push, data, start, count);
  652.             break;
  653.          case 4:
  654.             if (shorten)
  655.                nv50_draw_elements_inline_u32_short(push, data, start, count);
  656.             else
  657.                nv50_draw_elements_inline_u32(push, data, start, count);
  658.             break;
  659.          default:
  660.             assert(0);
  661.             return;
  662.          }
  663.          BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
  664.          PUSH_DATA (push, 0);
  665.  
  666.          prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
  667.       }
  668.    }
  669. }
  670.  
  671. static void
  672. nva0_draw_stream_output(struct nv50_context *nv50,
  673.                         const struct pipe_draw_info *info)
  674. {
  675.    struct nouveau_pushbuf *push = nv50->base.pushbuf;
  676.    struct nv50_so_target *so = nv50_so_target(info->count_from_stream_output);
  677.    struct nv04_resource *res = nv04_resource(so->pipe.buffer);
  678.    unsigned num_instances = info->instance_count;
  679.    unsigned mode = nv50_prim_gl(info->mode);
  680.  
  681.    if (unlikely(nv50->screen->base.class_3d < NVA0_3D_CLASS)) {
  682.       /* A proper implementation without waiting doesn't seem possible,
  683.        * so don't bother.
  684.        */
  685.       NOUVEAU_ERR("draw_stream_output not supported on pre-NVA0 cards\n");
  686.       return;
  687.    }
  688.  
  689.    if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
  690.       res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
  691.       PUSH_SPACE(push, 4);
  692.       BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
  693.       PUSH_DATA (push, 0);
  694.       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1);
  695.       PUSH_DATA (push, 0);
  696.    }
  697.  
  698.    assert(num_instances);
  699.    do {
  700.       PUSH_SPACE(push, 8);
  701.       BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
  702.       PUSH_DATA (push, mode);
  703.       BEGIN_NV04(push, NVA0_3D(DRAW_TFB_BASE), 1);
  704.       PUSH_DATA (push, 0);
  705.       BEGIN_NV04(push, NVA0_3D(DRAW_TFB_STRIDE), 1);
  706.       PUSH_DATA (push, 0);
  707.       BEGIN_NV04(push, NVA0_3D(DRAW_TFB_BYTES), 1);
  708.       nv50_query_pushbuf_submit(push, so->pq, 0x4);
  709.       BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
  710.       PUSH_DATA (push, 0);
  711.  
  712.       mode |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
  713.    } while (--num_instances);
  714. }
  715.  
  716. static void
  717. nv50_draw_vbo_kick_notify(struct nouveau_pushbuf *chan)
  718. {
  719.    struct nv50_screen *screen = chan->user_priv;
  720.  
  721.    nouveau_fence_update(&screen->base, TRUE);
  722.  
  723.    nv50_bufctx_fence(screen->cur_ctx->bufctx_3d, TRUE);
  724. }
  725.  
  726. void
  727. nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
  728. {
  729.    struct nv50_context *nv50 = nv50_context(pipe);
  730.    struct nouveau_pushbuf *push = nv50->base.pushbuf;
  731.  
  732.    /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */
  733.    nv50->vb_elt_first = info->min_index + info->index_bias;
  734.    nv50->vb_elt_limit = info->max_index - info->min_index;
  735.    nv50->instance_off = info->start_instance;
  736.    nv50->instance_max = info->instance_count - 1;
  737.  
  738.    /* For picking only a few vertices from a large user buffer, push is better,
  739.     * if index count is larger and we expect repeated vertices, suggest upload.
  740.     */
  741.    nv50->vbo_push_hint = /* the 64 is heuristic */
  742.       !(info->indexed && ((nv50->vb_elt_limit + 64) < info->count));
  743.  
  744.    if (nv50->vbo_user && !(nv50->dirty & (NV50_NEW_ARRAYS | NV50_NEW_VERTEX))) {
  745.       if (!!nv50->vbo_fifo != nv50->vbo_push_hint)
  746.          nv50->dirty |= NV50_NEW_ARRAYS;
  747.       else
  748.       if (!nv50->vbo_fifo)
  749.          nv50_update_user_vbufs(nv50);
  750.    }
  751.  
  752.    if (unlikely(nv50->num_so_targets && !nv50->gmtyprog))
  753.       nv50->state.prim_size = nv50_pipe_prim_to_prim_size[info->mode];
  754.  
  755.    nv50_state_validate(nv50, ~0, 8); /* 8 as minimum, we use flush_notify */
  756.  
  757.    push->kick_notify = nv50_draw_vbo_kick_notify;
  758.  
  759.    if (nv50->vbo_fifo) {
  760.       nv50_push_vbo(nv50, info);
  761.       push->kick_notify = nv50_default_kick_notify;
  762.       nouveau_pushbuf_bufctx(push, NULL);
  763.       return;
  764.    }
  765.  
  766.    if (nv50->state.instance_base != info->start_instance) {
  767.       nv50->state.instance_base = info->start_instance;
  768.       /* NOTE: this does not affect the shader input, should it ? */
  769.       BEGIN_NV04(push, NV50_3D(VB_INSTANCE_BASE), 1);
  770.       PUSH_DATA (push, info->start_instance);
  771.    }
  772.  
  773.    if (nv50->base.vbo_dirty) {
  774.       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1);
  775.       PUSH_DATA (push, 0);
  776.       nv50->base.vbo_dirty = FALSE;
  777.    }
  778.  
  779.    if (info->indexed) {
  780.       boolean shorten = info->max_index <= 65535;
  781.  
  782.       if (info->primitive_restart != nv50->state.prim_restart) {
  783.          if (info->primitive_restart) {
  784.             BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 2);
  785.             PUSH_DATA (push, 1);
  786.             PUSH_DATA (push, info->restart_index);
  787.  
  788.             if (info->restart_index > 65535)
  789.                shorten = FALSE;
  790.          } else {
  791.             BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 1);
  792.             PUSH_DATA (push, 0);
  793.          }
  794.          nv50->state.prim_restart = info->primitive_restart;
  795.       } else
  796.       if (info->primitive_restart) {
  797.          BEGIN_NV04(push, NV50_3D(PRIM_RESTART_INDEX), 1);
  798.          PUSH_DATA (push, info->restart_index);
  799.  
  800.          if (info->restart_index > 65535)
  801.             shorten = FALSE;
  802.       }
  803.  
  804.       nv50_draw_elements(nv50, shorten,
  805.                          info->mode, info->start, info->count,
  806.                          info->instance_count, info->index_bias);
  807.    } else
  808.    if (unlikely(info->count_from_stream_output)) {
  809.       nva0_draw_stream_output(nv50, info);
  810.    } else {
  811.       nv50_draw_arrays(nv50,
  812.                        info->mode, info->start, info->count,
  813.                        info->instance_count);
  814.    }
  815.    push->kick_notify = nv50_default_kick_notify;
  816.  
  817.    nv50_release_user_vbufs(nv50);
  818.  
  819.    nouveau_pushbuf_bufctx(push, NULL);
  820. }
  821.