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  1. /*
  2.  * Mesa 3-D graphics library
  3.  *
  4.  * Copyright (C) 2012-2013 LunarG, Inc.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included
  14.  * in all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22.  * DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors:
  25.  *    Chia-I Wu <olv@lunarg.com>
  26.  */
  27.  
  28. #include "util/u_format_s3tc.h"
  29. #include "vl/vl_decoder.h"
  30. #include "vl/vl_video_buffer.h"
  31. #include "intel_chipset.h"
  32. #include "intel_reg.h" /* for TIMESTAMP */
  33. #include "intel_winsys.h"
  34.  
  35. #include "ilo_context.h"
  36. #include "ilo_format.h"
  37. #include "ilo_resource.h"
  38. #include "ilo_public.h"
  39. #include "ilo_screen.h"
  40.  
  41. int ilo_debug;
  42.  
  43. static const struct debug_named_value ilo_debug_flags[] = {
  44.    { "3d",        ILO_DEBUG_3D,       "Dump 3D commands and states" },
  45.    { "vs",        ILO_DEBUG_VS,       "Dump vertex shaders" },
  46.    { "gs",        ILO_DEBUG_GS,       "Dump geometry shaders" },
  47.    { "fs",        ILO_DEBUG_FS,       "Dump fragment shaders" },
  48.    { "cs",        ILO_DEBUG_CS,       "Dump compute shaders" },
  49.    { "nohw",      ILO_DEBUG_NOHW,     "Do not send commands to HW" },
  50.    { "nocache",   ILO_DEBUG_NOCACHE,  "Always invalidate HW caches" },
  51.    DEBUG_NAMED_VALUE_END
  52. };
  53.  
  54. static float
  55. ilo_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
  56. {
  57.    switch (param) {
  58.    case PIPE_CAPF_MAX_LINE_WIDTH:
  59.       /* in U3.7, defined in 3DSTATE_SF */
  60.       return 7.0f;
  61.    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
  62.       /* line width minus one, which is reserved for AA region */
  63.       return 6.0f;
  64.    case PIPE_CAPF_MAX_POINT_WIDTH:
  65.       /* in U8.3, defined in 3DSTATE_SF */
  66.       return 255.0f;
  67.    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
  68.       /* same as point width, as we ignore rasterizer->point_smooth */
  69.       return 255.0f;
  70.    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
  71.       /* [2.0, 16.0], defined in SAMPLER_STATE */
  72.       return 16.0f;
  73.    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
  74.       /* [-16.0, 16.0), defined in SAMPLER_STATE */
  75.       return 15.0f;
  76.    case PIPE_CAPF_GUARD_BAND_LEFT:
  77.    case PIPE_CAPF_GUARD_BAND_TOP:
  78.    case PIPE_CAPF_GUARD_BAND_RIGHT:
  79.    case PIPE_CAPF_GUARD_BAND_BOTTOM:
  80.       /* what are these for? */
  81.       return 0.0f;
  82.  
  83.    default:
  84.       return 0.0f;
  85.    }
  86. }
  87.  
  88. static int
  89. ilo_get_shader_param(struct pipe_screen *screen, unsigned shader,
  90.                      enum pipe_shader_cap param)
  91. {
  92.    switch (shader) {
  93.    case PIPE_SHADER_FRAGMENT:
  94.    case PIPE_SHADER_VERTEX:
  95.    case PIPE_SHADER_GEOMETRY:
  96.       break;
  97.    default:
  98.       return 0;
  99.    }
  100.  
  101.    switch (param) {
  102.    /* the limits are copied from the classic driver */
  103.    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
  104.       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 16384;
  105.    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
  106.       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
  107.    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
  108.       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
  109.    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
  110.       return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
  111.    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
  112.       return UINT_MAX;
  113.    case PIPE_SHADER_CAP_MAX_INPUTS:
  114.       /* this is limited by how many attributes SF can remap */
  115.       return 16;
  116.    case PIPE_SHADER_CAP_MAX_CONSTS:
  117.       return 1024;
  118.    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
  119.       return ILO_MAX_CONST_BUFFERS;
  120.    case PIPE_SHADER_CAP_MAX_TEMPS:
  121.       return 256;
  122.    case PIPE_SHADER_CAP_MAX_ADDRS:
  123.       return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
  124.    case PIPE_SHADER_CAP_MAX_PREDS:
  125.       return 0;
  126.    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
  127.       return 1;
  128.    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
  129.       return 0;
  130.    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
  131.       return 0;
  132.    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
  133.       return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
  134.    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
  135.       return 1;
  136.    case PIPE_SHADER_CAP_SUBROUTINES:
  137.       return 0;
  138.    case PIPE_SHADER_CAP_INTEGERS:
  139.       return 1;
  140.    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
  141.       return ILO_MAX_SAMPLERS;
  142.    case PIPE_SHADER_CAP_PREFERRED_IR:
  143.       return PIPE_SHADER_IR_TGSI;
  144.    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
  145.       return 1;
  146.  
  147.    default:
  148.       return 0;
  149.    }
  150. }
  151.  
  152. static int
  153. ilo_get_video_param(struct pipe_screen *screen,
  154.                     enum pipe_video_profile profile,
  155.                     enum pipe_video_cap param)
  156. {
  157.    switch (param) {
  158.    case PIPE_VIDEO_CAP_SUPPORTED:
  159.       return vl_profile_supported(screen, profile);
  160.    case PIPE_VIDEO_CAP_NPOT_TEXTURES:
  161.       return 1;
  162.    case PIPE_VIDEO_CAP_MAX_WIDTH:
  163.    case PIPE_VIDEO_CAP_MAX_HEIGHT:
  164.       return vl_video_buffer_max_size(screen);
  165.    case PIPE_VIDEO_CAP_PREFERED_FORMAT:
  166.       return PIPE_FORMAT_NV12;
  167.    case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
  168.       return 1;
  169.    case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
  170.       return 1;
  171.    case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
  172.       return 0;
  173.  
  174.    default:
  175.       return 0;
  176.    }
  177. }
  178.  
  179. static int
  180. ilo_get_compute_param(struct pipe_screen *screen,
  181.                       enum pipe_compute_cap param,
  182.                       void *ret)
  183. {
  184.    union {
  185.       const char *ir_target;
  186.       uint64_t grid_dimension;
  187.       uint64_t max_grid_size[3];
  188.       uint64_t max_block_size[3];
  189.       uint64_t max_threads_per_block;
  190.       uint64_t max_global_size;
  191.       uint64_t max_local_size;
  192.       uint64_t max_private_size;
  193.       uint64_t max_input_size;
  194.       uint64_t max_mem_alloc_size;
  195.    } val;
  196.    const void *ptr;
  197.    int size;
  198.  
  199.    /* XXX some randomly chosen values */
  200.    switch (param) {
  201.    case PIPE_COMPUTE_CAP_IR_TARGET:
  202.       val.ir_target = "ilog";
  203.  
  204.       ptr = val.ir_target;
  205.       size = strlen(val.ir_target) + 1;
  206.       break;
  207.    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
  208.       val.grid_dimension = Elements(val.max_grid_size);
  209.  
  210.       ptr = &val.grid_dimension;
  211.       size = sizeof(val.grid_dimension);
  212.       break;
  213.    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
  214.       val.max_grid_size[0] = 65535;
  215.       val.max_grid_size[1] = 65535;
  216.       val.max_grid_size[2] = 1;
  217.  
  218.       ptr = &val.max_grid_size;
  219.       size = sizeof(val.max_grid_size);
  220.       break;
  221.    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
  222.       val.max_block_size[0] = 512;
  223.       val.max_block_size[1] = 512;
  224.       val.max_block_size[2] = 512;
  225.  
  226.       ptr = &val.max_block_size;
  227.       size = sizeof(val.max_block_size);
  228.       break;
  229.  
  230.    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
  231.       val.max_threads_per_block = 512;
  232.  
  233.       ptr = &val.max_threads_per_block;
  234.       size = sizeof(val.max_threads_per_block);
  235.       break;
  236.    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
  237.       val.max_global_size = 4;
  238.  
  239.       ptr = &val.max_global_size;
  240.       size = sizeof(val.max_global_size);
  241.       break;
  242.    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
  243.       val.max_local_size = 64 * 1024;
  244.  
  245.       ptr = &val.max_local_size;
  246.       size = sizeof(val.max_local_size);
  247.       break;
  248.    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
  249.       val.max_private_size = 32768;
  250.  
  251.       ptr = &val.max_private_size;
  252.       size = sizeof(val.max_private_size);
  253.       break;
  254.    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
  255.       val.max_input_size = 256;
  256.  
  257.       ptr = &val.max_input_size;
  258.       size = sizeof(val.max_input_size);
  259.       break;
  260.    case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
  261.       val.max_mem_alloc_size = 128 * 1024 * 1024;
  262.  
  263.       ptr = &val.max_mem_alloc_size;
  264.       size = sizeof(val.max_mem_alloc_size);
  265.       break;
  266.    default:
  267.       ptr = NULL;
  268.       size = 0;
  269.       break;
  270.    }
  271.  
  272.    if (ret)
  273.       memcpy(ret, ptr, size);
  274.  
  275.    return size;
  276. }
  277.  
  278. static int
  279. ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
  280. {
  281.    struct ilo_screen *is = ilo_screen(screen);
  282.  
  283.    switch (param) {
  284.    case PIPE_CAP_NPOT_TEXTURES:
  285.    case PIPE_CAP_TWO_SIDED_STENCIL:
  286.       return true;
  287.    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  288.       return 0; /* TODO */
  289.    case PIPE_CAP_ANISOTROPIC_FILTER:
  290.    case PIPE_CAP_POINT_SPRITE:
  291.       return true;
  292.    case PIPE_CAP_MAX_RENDER_TARGETS:
  293.       return ILO_MAX_DRAW_BUFFERS;
  294.    case PIPE_CAP_OCCLUSION_QUERY:
  295.    case PIPE_CAP_QUERY_TIME_ELAPSED:
  296.    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  297.    case PIPE_CAP_TEXTURE_SWIZZLE: /* must be supported for shadow map */
  298.       return true;
  299.    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  300.       /*
  301.        * As defined in SURFACE_STATE, we have
  302.        *
  303.        *           Max WxHxD for 2D and CUBE     Max WxHxD for 3D
  304.        *  GEN6           8192x8192x512            2048x2048x2048
  305.        *  GEN7         16384x16384x2048           2048x2048x2048
  306.        *
  307.        * However, when the texutre size is large, things become unstable.  We
  308.        * require the maximum texture size to be 2^30 bytes in
  309.        * screen->can_create_resource().  Since the maximum pixel size is 2^4
  310.        * bytes (PIPE_FORMAT_R32G32B32A32_FLOAT), textures should not have more
  311.        * than 2^26 pixels.
  312.        *
  313.        * For 3D textures, we have to set the maximum number of levels to 9,
  314.        * which has at most 2^24 pixels.  For 2D textures, we set it to 14,
  315.        * which has at most 2^26 pixels.  And for cube textures, we has to set
  316.        * it to 12.
  317.        */
  318.       return 14;
  319.    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  320.       return 9;
  321.    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  322.       return 12;
  323.    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  324.       return false;
  325.    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  326.    case PIPE_CAP_SM3:
  327.       return true;
  328.    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
  329.       if (is->dev.gen >= ILO_GEN(7) && !is->dev.has_gen7_sol_reset)
  330.          return 0;
  331.       return ILO_MAX_SO_BUFFERS;
  332.    case PIPE_CAP_PRIMITIVE_RESTART:
  333.       return true;
  334.    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  335.       return ILO_MAX_SAMPLERS * 2;
  336.    case PIPE_CAP_INDEP_BLEND_ENABLE:
  337.    case PIPE_CAP_INDEP_BLEND_FUNC:
  338.       return true;
  339.    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  340.       return (is->dev.gen >= ILO_GEN(7)) ? 2048 : 512;
  341.    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  342.    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  343.    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  344.    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  345.    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  346.       return true;
  347.    case PIPE_CAP_SHADER_STENCIL_EXPORT:
  348.       return false;
  349.    case PIPE_CAP_TGSI_INSTANCEID:
  350.    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  351.       return true;
  352.    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
  353.       return false;
  354.    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  355.       return true;
  356.    case PIPE_CAP_SEAMLESS_CUBE_MAP:
  357.    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  358.    case PIPE_CAP_SCALED_RESOLVE:
  359.       return true;
  360.    case PIPE_CAP_MIN_TEXEL_OFFSET:
  361.       return -8;
  362.    case PIPE_CAP_MAX_TEXEL_OFFSET:
  363.       return 7;
  364.    case PIPE_CAP_CONDITIONAL_RENDER:
  365.    case PIPE_CAP_TEXTURE_BARRIER:
  366.       return true;
  367.    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
  368.       return ILO_MAX_SO_BINDINGS / ILO_MAX_SO_BUFFERS;
  369.    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
  370.       return ILO_MAX_SO_BINDINGS;
  371.    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
  372.       if (is->dev.gen >= ILO_GEN(7))
  373.          return is->dev.has_gen7_sol_reset;
  374.       else
  375.          return false; /* TODO */
  376.    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
  377.       return false;
  378.    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  379.       return true;
  380.    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
  381.       return false;
  382.    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  383.       return 140;
  384.    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
  385.    case PIPE_CAP_USER_VERTEX_BUFFERS:
  386.       return false;
  387.    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
  388.    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
  389.    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
  390.       return false;
  391.    case PIPE_CAP_COMPUTE:
  392.       return false; /* TODO */
  393.    case PIPE_CAP_USER_INDEX_BUFFERS:
  394.    case PIPE_CAP_USER_CONSTANT_BUFFERS:
  395.       return true;
  396.    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  397.       /* imposed by OWord (Dual) Block Read */
  398.       return 16;
  399.    case PIPE_CAP_START_INSTANCE:
  400.    case PIPE_CAP_QUERY_TIMESTAMP:
  401.       return true;
  402.    case PIPE_CAP_TEXTURE_MULTISAMPLE:
  403.       return false; /* TODO */
  404.    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
  405.       return 0;
  406.    case PIPE_CAP_CUBE_MAP_ARRAY:
  407.    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  408.       return true;
  409.    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
  410.       return 1;
  411.    case PIPE_CAP_TGSI_TEXCOORD:
  412.       return false;
  413.    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  414.       return true;
  415.    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
  416.       return false; /* TODO */
  417.    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
  418.       return 0;
  419.    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
  420.       /* a BRW_SURFACE_BUFFER can have up to 2^27 elements */
  421.       return 1 << 27;
  422.    case PIPE_CAP_MAX_VIEWPORTS:
  423.       return ILO_MAX_VIEWPORTS;
  424.    case PIPE_CAP_ENDIANNESS:
  425.       return PIPE_ENDIAN_LITTLE;
  426.  
  427.    default:
  428.       return 0;
  429.    }
  430. }
  431.  
  432. static const char *
  433. ilo_get_vendor(struct pipe_screen *screen)
  434. {
  435.    return "LunarG, Inc.";
  436. }
  437.  
  438. static const char *
  439. ilo_get_name(struct pipe_screen *screen)
  440. {
  441.    struct ilo_screen *is = ilo_screen(screen);
  442.    const char *chipset;
  443.  
  444.    /* stolen from classic i965 */
  445.    switch (is->dev.devid) {
  446.    case PCI_CHIP_SANDYBRIDGE_GT1:
  447.    case PCI_CHIP_SANDYBRIDGE_GT2:
  448.    case PCI_CHIP_SANDYBRIDGE_GT2_PLUS:
  449.       chipset = "Intel(R) Sandybridge Desktop";
  450.       break;
  451.    case PCI_CHIP_SANDYBRIDGE_M_GT1:
  452.    case PCI_CHIP_SANDYBRIDGE_M_GT2:
  453.    case PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS:
  454.       chipset = "Intel(R) Sandybridge Mobile";
  455.       break;
  456.    case PCI_CHIP_SANDYBRIDGE_S:
  457.       chipset = "Intel(R) Sandybridge Server";
  458.       break;
  459.    case PCI_CHIP_IVYBRIDGE_GT1:
  460.    case PCI_CHIP_IVYBRIDGE_GT2:
  461.       chipset = "Intel(R) Ivybridge Desktop";
  462.       break;
  463.    case PCI_CHIP_IVYBRIDGE_M_GT1:
  464.    case PCI_CHIP_IVYBRIDGE_M_GT2:
  465.       chipset = "Intel(R) Ivybridge Mobile";
  466.       break;
  467.    case PCI_CHIP_IVYBRIDGE_S_GT1:
  468.    case PCI_CHIP_IVYBRIDGE_S_GT2:
  469.       chipset = "Intel(R) Ivybridge Server";
  470.       break;
  471.    case PCI_CHIP_BAYTRAIL_M_1:
  472.    case PCI_CHIP_BAYTRAIL_M_2:
  473.    case PCI_CHIP_BAYTRAIL_M_3:
  474.    case PCI_CHIP_BAYTRAIL_M_4:
  475.    case PCI_CHIP_BAYTRAIL_D:
  476.       chipset = "Intel(R) Bay Trail";
  477.       break;
  478.    case PCI_CHIP_HASWELL_GT1:
  479.    case PCI_CHIP_HASWELL_GT2:
  480.    case PCI_CHIP_HASWELL_GT3:
  481.    case PCI_CHIP_HASWELL_SDV_GT1:
  482.    case PCI_CHIP_HASWELL_SDV_GT2:
  483.    case PCI_CHIP_HASWELL_SDV_GT3:
  484.    case PCI_CHIP_HASWELL_ULT_GT1:
  485.    case PCI_CHIP_HASWELL_ULT_GT2:
  486.    case PCI_CHIP_HASWELL_ULT_GT3:
  487.    case PCI_CHIP_HASWELL_CRW_GT1:
  488.    case PCI_CHIP_HASWELL_CRW_GT2:
  489.    case PCI_CHIP_HASWELL_CRW_GT3:
  490.       chipset = "Intel(R) Haswell Desktop";
  491.       break;
  492.    case PCI_CHIP_HASWELL_M_GT1:
  493.    case PCI_CHIP_HASWELL_M_GT2:
  494.    case PCI_CHIP_HASWELL_M_GT3:
  495.    case PCI_CHIP_HASWELL_SDV_M_GT1:
  496.    case PCI_CHIP_HASWELL_SDV_M_GT2:
  497.    case PCI_CHIP_HASWELL_SDV_M_GT3:
  498.    case PCI_CHIP_HASWELL_ULT_M_GT1:
  499.    case PCI_CHIP_HASWELL_ULT_M_GT2:
  500.    case PCI_CHIP_HASWELL_ULT_M_GT3:
  501.    case PCI_CHIP_HASWELL_CRW_M_GT1:
  502.    case PCI_CHIP_HASWELL_CRW_M_GT2:
  503.    case PCI_CHIP_HASWELL_CRW_M_GT3:
  504.       chipset = "Intel(R) Haswell Mobile";
  505.       break;
  506.    case PCI_CHIP_HASWELL_S_GT1:
  507.    case PCI_CHIP_HASWELL_S_GT2:
  508.    case PCI_CHIP_HASWELL_S_GT3:
  509.    case PCI_CHIP_HASWELL_SDV_S_GT1:
  510.    case PCI_CHIP_HASWELL_SDV_S_GT2:
  511.    case PCI_CHIP_HASWELL_SDV_S_GT3:
  512.    case PCI_CHIP_HASWELL_ULT_S_GT1:
  513.    case PCI_CHIP_HASWELL_ULT_S_GT2:
  514.    case PCI_CHIP_HASWELL_ULT_S_GT3:
  515.    case PCI_CHIP_HASWELL_CRW_S_GT1:
  516.    case PCI_CHIP_HASWELL_CRW_S_GT2:
  517.    case PCI_CHIP_HASWELL_CRW_S_GT3:
  518.       chipset = "Intel(R) Haswell Server";
  519.       break;
  520.    default:
  521.       chipset = "Unknown Intel Chipset";
  522.       break;
  523.    }
  524.  
  525.    return chipset;
  526. }
  527.  
  528. static uint64_t
  529. ilo_get_timestamp(struct pipe_screen *screen)
  530. {
  531.    struct ilo_screen *is = ilo_screen(screen);
  532.    union {
  533.       uint64_t val;
  534.       uint32_t dw[2];
  535.    } timestamp;
  536.  
  537.    intel_winsys_read_reg(is->winsys, TIMESTAMP, &timestamp.val);
  538.  
  539.    /*
  540.     * From the Ivy Bridge PRM, volume 1 part 3, page 107:
  541.     *
  542.     *     "Note: This timestamp register reflects the value of the PCU TSC.
  543.     *      The PCU TSC counts 10ns increments; this timestamp reflects bits
  544.     *      38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5
  545.     *      hours)."
  546.     *
  547.     * However, it seems dw[0] is garbage and dw[1] contains the lower 32 bits
  548.     * of the timestamp.  We will have to live with a timestamp that rolls over
  549.     * every ~343 seconds.
  550.     *
  551.     * See also brw_get_timestamp().
  552.     */
  553.    return (uint64_t) timestamp.dw[1] * 80;
  554. }
  555.  
  556. static void
  557. ilo_fence_reference(struct pipe_screen *screen,
  558.                     struct pipe_fence_handle **p,
  559.                     struct pipe_fence_handle *f)
  560. {
  561.    struct ilo_fence **ptr = (struct ilo_fence **) p;
  562.    struct ilo_fence *fence = ilo_fence(f);
  563.  
  564.    if (!ptr) {
  565.       /* still need to reference fence */
  566.       if (fence)
  567.          pipe_reference(NULL, &fence->reference);
  568.       return;
  569.    }
  570.  
  571.    /* reference fence and dereference the one pointed to by ptr */
  572.    if (*ptr && pipe_reference(&(*ptr)->reference, &fence->reference)) {
  573.       struct ilo_fence *old = *ptr;
  574.  
  575.       if (old->bo)
  576.          intel_bo_unreference(old->bo);
  577.       FREE(old);
  578.    }
  579.  
  580.    *ptr = fence;
  581. }
  582.  
  583. static boolean
  584. ilo_fence_signalled(struct pipe_screen *screen,
  585.                     struct pipe_fence_handle *f)
  586. {
  587.    struct ilo_fence *fence = ilo_fence(f);
  588.  
  589.    /* mark signalled if the bo is idle */
  590.    if (fence->bo && !intel_bo_is_busy(fence->bo)) {
  591.       intel_bo_unreference(fence->bo);
  592.       fence->bo = NULL;
  593.    }
  594.  
  595.    return (fence->bo == NULL);
  596. }
  597.  
  598. static boolean
  599. ilo_fence_finish(struct pipe_screen *screen,
  600.                  struct pipe_fence_handle *f,
  601.                  uint64_t timeout)
  602. {
  603.    struct ilo_fence *fence = ilo_fence(f);
  604.    const int64_t wait_timeout = (timeout > INT64_MAX) ? -1 : timeout;
  605.  
  606.    /* already signalled */
  607.    if (!fence->bo)
  608.       return true;
  609.  
  610.    /* wait and see if it returns error */
  611.    if (intel_bo_wait(fence->bo, wait_timeout))
  612.       return false;
  613.  
  614.    /* mark signalled */
  615.    intel_bo_unreference(fence->bo);
  616.    fence->bo = NULL;
  617.  
  618.    return true;
  619. }
  620.  
  621. static void
  622. ilo_screen_destroy(struct pipe_screen *screen)
  623. {
  624.    struct ilo_screen *is = ilo_screen(screen);
  625.  
  626.    /* as it seems, winsys is owned by the screen */
  627.    intel_winsys_destroy(is->winsys);
  628.  
  629.    FREE(is);
  630. }
  631.  
  632. static bool
  633. init_dev(struct ilo_dev_info *dev, const struct intel_winsys_info *info)
  634. {
  635.    dev->devid = info->devid;
  636.    dev->has_llc = info->has_llc;
  637.    dev->has_gen7_sol_reset = info->has_gen7_sol_reset;
  638.    dev->has_address_swizzling = info->has_address_swizzling;
  639.  
  640.    /*
  641.     * From the Sandy Bridge PRM, volume 4 part 2, page 18:
  642.     *
  643.     *     "[DevSNB]: The GT1 product's URB provides 32KB of storage, arranged
  644.     *      as 1024 256-bit rows. The GT2 product's URB provides 64KB of
  645.     *      storage, arranged as 2048 256-bit rows. A row corresponds in size
  646.     *      to an EU GRF register. Read/write access to the URB is generally
  647.     *      supported on a row-granular basis."
  648.     *
  649.     * From the Ivy Bridge PRM, volume 4 part 2, page 17:
  650.     *
  651.     *     "URB Size    URB Rows    URB Rows when SLM Enabled
  652.     *      128k        4096        2048
  653.     *      256k        8096        4096"
  654.     */
  655.  
  656.    if (IS_HASWELL(info->devid)) {
  657.       dev->gen = ILO_GEN(7.5);
  658.  
  659.       if (IS_HSW_GT3(info->devid)) {
  660.          dev->gt = 3;
  661.          dev->urb_size = 512 * 1024;
  662.       }
  663.       else if (IS_HSW_GT2(info->devid)) {
  664.          dev->gt = 2;
  665.          dev->urb_size = 256 * 1024;
  666.       }
  667.       else {
  668.          dev->gt = 1;
  669.          dev->urb_size = 128 * 1024;
  670.       }
  671.    }
  672.    else if (IS_GEN7(info->devid)) {
  673.       dev->gen = ILO_GEN(7);
  674.  
  675.       if (IS_IVB_GT2(info->devid)) {
  676.          dev->gt = 2;
  677.          dev->urb_size = 256 * 1024;
  678.       }
  679.       else {
  680.          dev->gt = 1;
  681.          dev->urb_size = 128 * 1024;
  682.       }
  683.    }
  684.    else if (IS_GEN6(info->devid)) {
  685.       dev->gen = ILO_GEN(6);
  686.  
  687.       if (IS_SNB_GT2(info->devid)) {
  688.          dev->gt = 2;
  689.          dev->urb_size = 64 * 1024;
  690.       }
  691.       else {
  692.          dev->gt = 1;
  693.          dev->urb_size = 32 * 1024;
  694.       }
  695.    }
  696.    else {
  697.       ilo_err("unknown GPU generation\n");
  698.       return false;
  699.    }
  700.  
  701.    return true;
  702. }
  703.  
  704. struct pipe_screen *
  705. ilo_screen_create(struct intel_winsys *ws)
  706. {
  707.    struct ilo_screen *is;
  708.    const struct intel_winsys_info *info;
  709.  
  710.    ilo_debug = debug_get_flags_option("ILO_DEBUG", ilo_debug_flags, 0);
  711.  
  712.    is = CALLOC_STRUCT(ilo_screen);
  713.    if (!is)
  714.       return NULL;
  715.  
  716.    is->winsys = ws;
  717.  
  718.    intel_winsys_enable_reuse(is->winsys);
  719.  
  720.    info = intel_winsys_get_info(is->winsys);
  721.    if (!init_dev(&is->dev, info)) {
  722.       FREE(is);
  723.       return NULL;
  724.    }
  725.  
  726.    util_format_s3tc_init();
  727.  
  728.    is->base.destroy = ilo_screen_destroy;
  729.    is->base.get_name = ilo_get_name;
  730.    is->base.get_vendor = ilo_get_vendor;
  731.    is->base.get_param = ilo_get_param;
  732.    is->base.get_paramf = ilo_get_paramf;
  733.    is->base.get_shader_param = ilo_get_shader_param;
  734.    is->base.get_video_param = ilo_get_video_param;
  735.    is->base.get_compute_param = ilo_get_compute_param;
  736.  
  737.    is->base.get_timestamp = ilo_get_timestamp;
  738.  
  739.    is->base.flush_frontbuffer = NULL;
  740.  
  741.    is->base.fence_reference = ilo_fence_reference;
  742.    is->base.fence_signalled = ilo_fence_signalled;
  743.    is->base.fence_finish = ilo_fence_finish;
  744.  
  745.    is->base.get_driver_query_info = NULL;
  746.  
  747.    ilo_init_format_functions(is);
  748.    ilo_init_context_functions(is);
  749.    ilo_init_resource_functions(is);
  750.  
  751.    return &is->base;
  752. }
  753.