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  1. /*
  2.  * Mesa 3-D graphics library
  3.  *
  4.  * Copyright (C) 2013 LunarG, Inc.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included
  14.  * in all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22.  * DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors:
  25.  *    Chia-I Wu <olv@lunarg.com>
  26.  */
  27.  
  28. #include "util/u_dual_blend.h"
  29. #include "util/u_prim.h"
  30. #include "intel_reg.h"
  31.  
  32. #include "ilo_3d.h"
  33. #include "ilo_context.h"
  34. #include "ilo_cp.h"
  35. #include "ilo_gpe_gen6.h"
  36. #include "ilo_shader.h"
  37. #include "ilo_state.h"
  38. #include "ilo_3d_pipeline.h"
  39. #include "ilo_3d_pipeline_gen6.h"
  40.  
  41. /**
  42.  * This should be called before any depth stall flush (including those
  43.  * produced by non-pipelined state commands) or cache flush on GEN6.
  44.  *
  45.  * \see intel_emit_post_sync_nonzero_flush()
  46.  */
  47. static void
  48. gen6_wa_pipe_control_post_sync(struct ilo_3d_pipeline *p,
  49.                                bool caller_post_sync)
  50. {
  51.    assert(p->dev->gen == ILO_GEN(6));
  52.  
  53.    /* emit once */
  54.    if (p->state.has_gen6_wa_pipe_control)
  55.       return;
  56.  
  57.    p->state.has_gen6_wa_pipe_control = true;
  58.  
  59.    /*
  60.     * From the Sandy Bridge PRM, volume 2 part 1, page 60:
  61.     *
  62.     *     "Pipe-control with CS-stall bit set must be sent BEFORE the
  63.     *      pipe-control with a post-sync op and no write-cache flushes."
  64.     *
  65.     * The workaround below necessitates this workaround.
  66.     */
  67.    p->gen6_PIPE_CONTROL(p->dev,
  68.          PIPE_CONTROL_CS_STALL |
  69.          PIPE_CONTROL_STALL_AT_SCOREBOARD,
  70.          NULL, 0, false, p->cp);
  71.  
  72.    /* the caller will emit the post-sync op */
  73.    if (caller_post_sync)
  74.       return;
  75.  
  76.    /*
  77.     * From the Sandy Bridge PRM, volume 2 part 1, page 60:
  78.     *
  79.     *     "Before any depth stall flush (including those produced by
  80.     *      non-pipelined state commands), software needs to first send a
  81.     *      PIPE_CONTROL with no bits set except Post-Sync Operation != 0."
  82.     *
  83.     *     "Before a PIPE_CONTROL with Write Cache Flush Enable =1, a
  84.     *      PIPE_CONTROL with any non-zero post-sync-op is required."
  85.     */
  86.    p->gen6_PIPE_CONTROL(p->dev,
  87.          PIPE_CONTROL_WRITE_IMMEDIATE,
  88.          p->workaround_bo, 0, false, p->cp);
  89. }
  90.  
  91. static void
  92. gen6_wa_pipe_control_wm_multisample_flush(struct ilo_3d_pipeline *p)
  93. {
  94.    assert(p->dev->gen == ILO_GEN(6));
  95.  
  96.    gen6_wa_pipe_control_post_sync(p, false);
  97.  
  98.    /*
  99.     * From the Sandy Bridge PRM, volume 2 part 1, page 305:
  100.     *
  101.     *     "Driver must guarentee that all the caches in the depth pipe are
  102.     *      flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
  103.     *      requires driver to send a PIPE_CONTROL with a CS stall along with a
  104.     *      Depth Flush prior to this command."
  105.     */
  106.    p->gen6_PIPE_CONTROL(p->dev,
  107.          PIPE_CONTROL_DEPTH_CACHE_FLUSH |
  108.          PIPE_CONTROL_CS_STALL,
  109.          0, 0, false, p->cp);
  110. }
  111.  
  112. static void
  113. gen6_wa_pipe_control_wm_depth_flush(struct ilo_3d_pipeline *p)
  114. {
  115.    assert(p->dev->gen == ILO_GEN(6));
  116.  
  117.    gen6_wa_pipe_control_post_sync(p, false);
  118.  
  119.    /*
  120.     * According to intel_emit_depth_stall_flushes() of classic i965, we need
  121.     * to emit a sequence of PIPE_CONTROLs prior to emitting depth related
  122.     * commands.
  123.     */
  124.    p->gen6_PIPE_CONTROL(p->dev,
  125.          PIPE_CONTROL_DEPTH_STALL,
  126.          NULL, 0, false, p->cp);
  127.  
  128.    p->gen6_PIPE_CONTROL(p->dev,
  129.          PIPE_CONTROL_DEPTH_CACHE_FLUSH,
  130.          NULL, 0, false, p->cp);
  131.  
  132.    p->gen6_PIPE_CONTROL(p->dev,
  133.          PIPE_CONTROL_DEPTH_STALL,
  134.          NULL, 0, false, p->cp);
  135. }
  136.  
  137. static void
  138. gen6_wa_pipe_control_wm_max_threads_stall(struct ilo_3d_pipeline *p)
  139. {
  140.    assert(p->dev->gen == ILO_GEN(6));
  141.  
  142.    /* the post-sync workaround should cover this already */
  143.    if (p->state.has_gen6_wa_pipe_control)
  144.       return;
  145.  
  146.    /*
  147.     * From the Sandy Bridge PRM, volume 2 part 1, page 274:
  148.     *
  149.     *     "A PIPE_CONTROL command, with only the Stall At Pixel Scoreboard
  150.     *      field set (DW1 Bit 1), must be issued prior to any change to the
  151.     *      value in this field (Maximum Number of Threads in 3DSTATE_WM)"
  152.     */
  153.    p->gen6_PIPE_CONTROL(p->dev,
  154.          PIPE_CONTROL_STALL_AT_SCOREBOARD,
  155.          NULL, 0, false, p->cp);
  156.  
  157. }
  158.  
  159. static void
  160. gen6_wa_pipe_control_vs_const_flush(struct ilo_3d_pipeline *p)
  161. {
  162.    assert(p->dev->gen == ILO_GEN(6));
  163.  
  164.    gen6_wa_pipe_control_post_sync(p, false);
  165.  
  166.    /*
  167.     * According to upload_vs_state() of classic i965, we need to emit
  168.     * PIPE_CONTROL after 3DSTATE_CONSTANT_VS so that the command is kept being
  169.     * buffered by VS FF, to the point that the FF dies.
  170.     */
  171.    p->gen6_PIPE_CONTROL(p->dev,
  172.          PIPE_CONTROL_DEPTH_STALL |
  173.          PIPE_CONTROL_INSTRUCTION_FLUSH |
  174.          PIPE_CONTROL_STATE_CACHE_INVALIDATE,
  175.          NULL, 0, false, p->cp);
  176. }
  177.  
  178. #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
  179.  
  180. void
  181. gen6_pipeline_common_select(struct ilo_3d_pipeline *p,
  182.                             const struct ilo_context *ilo,
  183.                             struct gen6_pipeline_session *session)
  184. {
  185.    /* PIPELINE_SELECT */
  186.    if (session->hw_ctx_changed) {
  187.       if (p->dev->gen == ILO_GEN(6))
  188.          gen6_wa_pipe_control_post_sync(p, false);
  189.  
  190.       p->gen6_PIPELINE_SELECT(p->dev, 0x0, p->cp);
  191.    }
  192. }
  193.  
  194. void
  195. gen6_pipeline_common_sip(struct ilo_3d_pipeline *p,
  196.                          const struct ilo_context *ilo,
  197.                          struct gen6_pipeline_session *session)
  198. {
  199.    /* STATE_SIP */
  200.    if (session->hw_ctx_changed) {
  201.       if (p->dev->gen == ILO_GEN(6))
  202.          gen6_wa_pipe_control_post_sync(p, false);
  203.  
  204.       p->gen6_STATE_SIP(p->dev, 0, p->cp);
  205.    }
  206. }
  207.  
  208. void
  209. gen6_pipeline_common_base_address(struct ilo_3d_pipeline *p,
  210.                                   const struct ilo_context *ilo,
  211.                                   struct gen6_pipeline_session *session)
  212. {
  213.    /* STATE_BASE_ADDRESS */
  214.    if (session->state_bo_changed || session->kernel_bo_changed ||
  215.        session->batch_bo_changed) {
  216.       if (p->dev->gen == ILO_GEN(6))
  217.          gen6_wa_pipe_control_post_sync(p, false);
  218.  
  219.       p->gen6_STATE_BASE_ADDRESS(p->dev,
  220.             NULL, p->cp->bo, p->cp->bo, NULL, ilo->hw3d->kernel.bo,
  221.             0, 0, 0, 0, p->cp);
  222.  
  223.       /*
  224.        * From the Sandy Bridge PRM, volume 1 part 1, page 28:
  225.        *
  226.        *     "The following commands must be reissued following any change to
  227.        *      the base addresses:
  228.        *
  229.        *       * 3DSTATE_BINDING_TABLE_POINTERS
  230.        *       * 3DSTATE_SAMPLER_STATE_POINTERS
  231.        *       * 3DSTATE_VIEWPORT_STATE_POINTERS
  232.        *       * 3DSTATE_CC_POINTERS
  233.        *       * MEDIA_STATE_POINTERS"
  234.        *
  235.        * 3DSTATE_SCISSOR_STATE_POINTERS is not on the list, but it is
  236.        * reasonable to also reissue the command.  Same to PCB.
  237.        */
  238.       session->viewport_state_changed = true;
  239.  
  240.       session->cc_state_blend_changed = true;
  241.       session->cc_state_dsa_changed = true;
  242.       session->cc_state_cc_changed = true;
  243.  
  244.       session->scissor_state_changed = true;
  245.  
  246.       session->binding_table_vs_changed = true;
  247.       session->binding_table_gs_changed = true;
  248.       session->binding_table_fs_changed = true;
  249.  
  250.       session->sampler_state_vs_changed = true;
  251.       session->sampler_state_gs_changed = true;
  252.       session->sampler_state_fs_changed = true;
  253.  
  254.       session->pcb_state_vs_changed = true;
  255.       session->pcb_state_gs_changed = true;
  256.       session->pcb_state_fs_changed = true;
  257.    }
  258. }
  259.  
  260. static void
  261. gen6_pipeline_common_urb(struct ilo_3d_pipeline *p,
  262.                          const struct ilo_context *ilo,
  263.                          struct gen6_pipeline_session *session)
  264. {
  265.    /* 3DSTATE_URB */
  266.    if (DIRTY(VE) || DIRTY(VS) || DIRTY(GS)) {
  267.       const bool gs_active = (ilo->gs || (ilo->vs &&
  268.                ilo_shader_get_kernel_param(ilo->vs, ILO_KERNEL_VS_GEN6_SO)));
  269.       int vs_entry_size, gs_entry_size;
  270.       int vs_total_size, gs_total_size;
  271.  
  272.       vs_entry_size = (ilo->vs) ?
  273.          ilo_shader_get_kernel_param(ilo->vs, ILO_KERNEL_OUTPUT_COUNT) : 0;
  274.  
  275.       /*
  276.        * As indicated by 2e712e41db0c0676e9f30fc73172c0e8de8d84d4, VF and VS
  277.        * share VUE handles.  The VUE allocation size must be large enough to
  278.        * store either VF outputs (number of VERTEX_ELEMENTs) and VS outputs.
  279.        *
  280.        * I am not sure if the PRM explicitly states that VF and VS share VUE
  281.        * handles.  But here is a citation that implies so:
  282.        *
  283.        * From the Sandy Bridge PRM, volume 2 part 1, page 44:
  284.        *
  285.        *     "Once a FF stage that spawn threads has sufficient input to
  286.        *      initiate a thread, it must guarantee that it is safe to request
  287.        *      the thread initiation. For all these FF stages, this check is
  288.        *      based on :
  289.        *
  290.        *      - The availability of output URB entries:
  291.        *        - VS: As the input URB entries are overwritten with the
  292.        *          VS-generated output data, output URB availability isn't a
  293.        *          factor."
  294.        */
  295.       if (vs_entry_size < ilo->ve->count)
  296.          vs_entry_size = ilo->ve->count;
  297.  
  298.       gs_entry_size = (ilo->gs) ?
  299.          ilo_shader_get_kernel_param(ilo->gs, ILO_KERNEL_OUTPUT_COUNT) :
  300.          (gs_active) ? vs_entry_size : 0;
  301.  
  302.       /* in bytes */
  303.       vs_entry_size *= sizeof(float) * 4;
  304.       gs_entry_size *= sizeof(float) * 4;
  305.       vs_total_size = ilo->dev->urb_size;
  306.  
  307.       if (gs_active) {
  308.          vs_total_size /= 2;
  309.          gs_total_size = vs_total_size;
  310.       }
  311.       else {
  312.          gs_total_size = 0;
  313.       }
  314.  
  315.       p->gen6_3DSTATE_URB(p->dev, vs_total_size, gs_total_size,
  316.             vs_entry_size, gs_entry_size, p->cp);
  317.  
  318.       /*
  319.        * From the Sandy Bridge PRM, volume 2 part 1, page 27:
  320.        *
  321.        *     "Because of a urb corruption caused by allocating a previous
  322.        *      gsunit's urb entry to vsunit software is required to send a
  323.        *      "GS NULL Fence" (Send URB fence with VS URB size == 1 and GS URB
  324.        *      size == 0) plus a dummy DRAW call before any case where VS will
  325.        *      be taking over GS URB space."
  326.        */
  327.       if (p->state.gs.active && !gs_active)
  328.          ilo_3d_pipeline_emit_flush_gen6(p);
  329.  
  330.       p->state.gs.active = gs_active;
  331.    }
  332. }
  333.  
  334. static void
  335. gen6_pipeline_common_pointers_1(struct ilo_3d_pipeline *p,
  336.                                 const struct ilo_context *ilo,
  337.                                 struct gen6_pipeline_session *session)
  338. {
  339.    /* 3DSTATE_VIEWPORT_STATE_POINTERS */
  340.    if (session->viewport_state_changed) {
  341.       p->gen6_3DSTATE_VIEWPORT_STATE_POINTERS(p->dev,
  342.             p->state.CLIP_VIEWPORT,
  343.             p->state.SF_VIEWPORT,
  344.             p->state.CC_VIEWPORT, p->cp);
  345.    }
  346. }
  347.  
  348. static void
  349. gen6_pipeline_common_pointers_2(struct ilo_3d_pipeline *p,
  350.                                 const struct ilo_context *ilo,
  351.                                 struct gen6_pipeline_session *session)
  352. {
  353.    /* 3DSTATE_CC_STATE_POINTERS */
  354.    if (session->cc_state_blend_changed ||
  355.        session->cc_state_dsa_changed ||
  356.        session->cc_state_cc_changed) {
  357.       p->gen6_3DSTATE_CC_STATE_POINTERS(p->dev,
  358.             p->state.BLEND_STATE,
  359.             p->state.DEPTH_STENCIL_STATE,
  360.             p->state.COLOR_CALC_STATE, p->cp);
  361.    }
  362.  
  363.    /* 3DSTATE_SAMPLER_STATE_POINTERS */
  364.    if (session->sampler_state_vs_changed ||
  365.        session->sampler_state_gs_changed ||
  366.        session->sampler_state_fs_changed) {
  367.       p->gen6_3DSTATE_SAMPLER_STATE_POINTERS(p->dev,
  368.             p->state.vs.SAMPLER_STATE,
  369.             0,
  370.             p->state.wm.SAMPLER_STATE, p->cp);
  371.    }
  372. }
  373.  
  374. static void
  375. gen6_pipeline_common_pointers_3(struct ilo_3d_pipeline *p,
  376.                                 const struct ilo_context *ilo,
  377.                                 struct gen6_pipeline_session *session)
  378. {
  379.    /* 3DSTATE_SCISSOR_STATE_POINTERS */
  380.    if (session->scissor_state_changed) {
  381.       p->gen6_3DSTATE_SCISSOR_STATE_POINTERS(p->dev,
  382.             p->state.SCISSOR_RECT, p->cp);
  383.    }
  384.  
  385.    /* 3DSTATE_BINDING_TABLE_POINTERS */
  386.    if (session->binding_table_vs_changed ||
  387.        session->binding_table_gs_changed ||
  388.        session->binding_table_fs_changed) {
  389.       p->gen6_3DSTATE_BINDING_TABLE_POINTERS(p->dev,
  390.             p->state.vs.BINDING_TABLE_STATE,
  391.             p->state.gs.BINDING_TABLE_STATE,
  392.             p->state.wm.BINDING_TABLE_STATE, p->cp);
  393.    }
  394. }
  395.  
  396. void
  397. gen6_pipeline_vf(struct ilo_3d_pipeline *p,
  398.                  const struct ilo_context *ilo,
  399.                  struct gen6_pipeline_session *session)
  400. {
  401.    /* 3DSTATE_INDEX_BUFFER */
  402.    if (DIRTY(IB) || session->primitive_restart_changed ||
  403.        session->batch_bo_changed) {
  404.       p->gen6_3DSTATE_INDEX_BUFFER(p->dev,
  405.             &ilo->ib, ilo->draw->primitive_restart, p->cp);
  406.    }
  407.  
  408.    /* 3DSTATE_VERTEX_BUFFERS */
  409.    if (DIRTY(VB) || DIRTY(VE) || session->batch_bo_changed) {
  410.       p->gen6_3DSTATE_VERTEX_BUFFERS(p->dev,
  411.             ilo->vb.states, ilo->vb.enabled_mask, ilo->ve, p->cp);
  412.    }
  413.  
  414.    /* 3DSTATE_VERTEX_ELEMENTS */
  415.    if (DIRTY(VE) || DIRTY(VS)) {
  416.       const struct ilo_ve_state *ve = ilo->ve;
  417.       bool last_velement_edgeflag = false;
  418.       bool prepend_generate_ids = false;
  419.  
  420.       if (ilo->vs) {
  421.          if (ilo_shader_get_kernel_param(ilo->vs,
  422.                   ILO_KERNEL_VS_INPUT_EDGEFLAG)) {
  423.             /* we rely on the state tracker here */
  424.             assert(ilo_shader_get_kernel_param(ilo->vs,
  425.                      ILO_KERNEL_INPUT_COUNT) == ve->count);
  426.  
  427.             last_velement_edgeflag = true;
  428.          }
  429.  
  430.          if (ilo_shader_get_kernel_param(ilo->vs,
  431.                   ILO_KERNEL_VS_INPUT_INSTANCEID) ||
  432.              ilo_shader_get_kernel_param(ilo->vs,
  433.                   ILO_KERNEL_VS_INPUT_VERTEXID))
  434.             prepend_generate_ids = true;
  435.       }
  436.  
  437.       p->gen6_3DSTATE_VERTEX_ELEMENTS(p->dev, ve,
  438.             last_velement_edgeflag, prepend_generate_ids, p->cp);
  439.    }
  440. }
  441.  
  442. void
  443. gen6_pipeline_vf_statistics(struct ilo_3d_pipeline *p,
  444.                             const struct ilo_context *ilo,
  445.                             struct gen6_pipeline_session *session)
  446. {
  447.    /* 3DSTATE_VF_STATISTICS */
  448.    if (session->hw_ctx_changed)
  449.       p->gen6_3DSTATE_VF_STATISTICS(p->dev, false, p->cp);
  450. }
  451.  
  452. void
  453. gen6_pipeline_vf_draw(struct ilo_3d_pipeline *p,
  454.                       const struct ilo_context *ilo,
  455.                       struct gen6_pipeline_session *session)
  456. {
  457.    /* 3DPRIMITIVE */
  458.    p->gen6_3DPRIMITIVE(p->dev, ilo->draw, &ilo->ib, false, p->cp);
  459.    p->state.has_gen6_wa_pipe_control = false;
  460. }
  461.  
  462. void
  463. gen6_pipeline_vs(struct ilo_3d_pipeline *p,
  464.                  const struct ilo_context *ilo,
  465.                  struct gen6_pipeline_session *session)
  466. {
  467.    const bool emit_3dstate_vs = (DIRTY(VS) || DIRTY(SAMPLER_VS) ||
  468.                                  session->kernel_bo_changed);
  469.    const bool emit_3dstate_constant_vs = session->pcb_state_vs_changed;
  470.  
  471.    /*
  472.     * the classic i965 does this in upload_vs_state(), citing a spec that I
  473.     * cannot find
  474.     */
  475.    if (emit_3dstate_vs && p->dev->gen == ILO_GEN(6))
  476.       gen6_wa_pipe_control_post_sync(p, false);
  477.  
  478.    /* 3DSTATE_CONSTANT_VS */
  479.    if (emit_3dstate_constant_vs) {
  480.       p->gen6_3DSTATE_CONSTANT_VS(p->dev,
  481.             &p->state.vs.PUSH_CONSTANT_BUFFER,
  482.             &p->state.vs.PUSH_CONSTANT_BUFFER_size,
  483.             1, p->cp);
  484.    }
  485.  
  486.    /* 3DSTATE_VS */
  487.    if (emit_3dstate_vs) {
  488.       const int num_samplers = ilo->sampler[PIPE_SHADER_VERTEX].count;
  489.  
  490.       p->gen6_3DSTATE_VS(p->dev, ilo->vs, num_samplers, p->cp);
  491.    }
  492.  
  493.    if (emit_3dstate_constant_vs && p->dev->gen == ILO_GEN(6))
  494.       gen6_wa_pipe_control_vs_const_flush(p);
  495. }
  496.  
  497. static void
  498. gen6_pipeline_gs(struct ilo_3d_pipeline *p,
  499.                  const struct ilo_context *ilo,
  500.                  struct gen6_pipeline_session *session)
  501. {
  502.    /* 3DSTATE_CONSTANT_GS */
  503.    if (session->pcb_state_gs_changed)
  504.       p->gen6_3DSTATE_CONSTANT_GS(p->dev, NULL, NULL, 0, p->cp);
  505.  
  506.    /* 3DSTATE_GS */
  507.    if (DIRTY(GS) || DIRTY(VS) ||
  508.        session->prim_changed || session->kernel_bo_changed) {
  509.       const int verts_per_prim = u_vertices_per_prim(session->reduced_prim);
  510.  
  511.       p->gen6_3DSTATE_GS(p->dev, ilo->gs, ilo->vs, verts_per_prim, p->cp);
  512.    }
  513. }
  514.  
  515. bool
  516. gen6_pipeline_update_max_svbi(struct ilo_3d_pipeline *p,
  517.                               const struct ilo_context *ilo,
  518.                               struct gen6_pipeline_session *session)
  519. {
  520.    if (DIRTY(VS) || DIRTY(GS) || DIRTY(SO)) {
  521.       const struct pipe_stream_output_info *so_info =
  522.          (ilo->gs) ? ilo_shader_get_kernel_so_info(ilo->gs) :
  523.          (ilo->vs) ? ilo_shader_get_kernel_so_info(ilo->vs) : NULL;
  524.       unsigned max_svbi = 0xffffffff;
  525.       int i;
  526.  
  527.       for (i = 0; i < so_info->num_outputs; i++) {
  528.          const int output_buffer = so_info->output[i].output_buffer;
  529.          const struct pipe_stream_output_target *so =
  530.             ilo->so.states[output_buffer];
  531.          const int struct_size = so_info->stride[output_buffer] * 4;
  532.          const int elem_size = so_info->output[i].num_components * 4;
  533.          int buf_size, count;
  534.  
  535.          if (!so) {
  536.             max_svbi = 0;
  537.             break;
  538.          }
  539.  
  540.          buf_size = so->buffer_size - so_info->output[i].dst_offset * 4;
  541.  
  542.          count = buf_size / struct_size;
  543.          if (buf_size % struct_size >= elem_size)
  544.             count++;
  545.  
  546.          if (count < max_svbi)
  547.             max_svbi = count;
  548.       }
  549.  
  550.       if (p->state.so_max_vertices != max_svbi) {
  551.          p->state.so_max_vertices = max_svbi;
  552.          return true;
  553.       }
  554.    }
  555.  
  556.    return false;
  557. }
  558.  
  559. static void
  560. gen6_pipeline_gs_svbi(struct ilo_3d_pipeline *p,
  561.                       const struct ilo_context *ilo,
  562.                       struct gen6_pipeline_session *session)
  563. {
  564.    const bool emit = gen6_pipeline_update_max_svbi(p, ilo, session);
  565.  
  566.    /* 3DSTATE_GS_SVB_INDEX */
  567.    if (emit) {
  568.       if (p->dev->gen == ILO_GEN(6))
  569.          gen6_wa_pipe_control_post_sync(p, false);
  570.  
  571.       p->gen6_3DSTATE_GS_SVB_INDEX(p->dev,
  572.             0, p->state.so_num_vertices, p->state.so_max_vertices,
  573.             false, p->cp);
  574.  
  575.       if (session->hw_ctx_changed) {
  576.          int i;
  577.  
  578.          /*
  579.           * From the Sandy Bridge PRM, volume 2 part 1, page 148:
  580.           *
  581.           *     "If a buffer is not enabled then the SVBI must be set to 0x0
  582.           *      in order to not cause overflow in that SVBI."
  583.           *
  584.           *     "If a buffer is not enabled then the MaxSVBI must be set to
  585.           *      0xFFFFFFFF in order to not cause overflow in that SVBI."
  586.           */
  587.          for (i = 1; i < 4; i++) {
  588.             p->gen6_3DSTATE_GS_SVB_INDEX(p->dev,
  589.                   i, 0, 0xffffffff, false, p->cp);
  590.          }
  591.       }
  592.    }
  593. }
  594.  
  595. void
  596. gen6_pipeline_clip(struct ilo_3d_pipeline *p,
  597.                    const struct ilo_context *ilo,
  598.                    struct gen6_pipeline_session *session)
  599. {
  600.    /* 3DSTATE_CLIP */
  601.    if (DIRTY(RASTERIZER) || DIRTY(FS) || DIRTY(VIEWPORT) || DIRTY(FB)) {
  602.       bool enable_guardband = true;
  603.       unsigned i;
  604.  
  605.       /*
  606.        * We do not do 2D clipping yet.  Guard band test should only be enabled
  607.        * when the viewport is larger than the framebuffer.
  608.        */
  609.       for (i = 0; i < ilo->viewport.count; i++) {
  610.          const struct ilo_viewport_cso *vp = &ilo->viewport.cso[i];
  611.  
  612.          if (vp->min_x > 0.0f || vp->max_x < ilo->fb.state.width ||
  613.              vp->min_y > 0.0f || vp->max_y < ilo->fb.state.height) {
  614.             enable_guardband = false;
  615.             break;
  616.          }
  617.       }
  618.  
  619.       p->gen6_3DSTATE_CLIP(p->dev, ilo->rasterizer,
  620.             ilo->fs, enable_guardband, 1, p->cp);
  621.    }
  622. }
  623.  
  624. static void
  625. gen6_pipeline_sf(struct ilo_3d_pipeline *p,
  626.                  const struct ilo_context *ilo,
  627.                  struct gen6_pipeline_session *session)
  628. {
  629.    /* 3DSTATE_SF */
  630.    if (DIRTY(RASTERIZER) || DIRTY(VS) || DIRTY(GS) || DIRTY(FS)) {
  631.       p->gen6_3DSTATE_SF(p->dev, ilo->rasterizer, ilo->fs,
  632.             (ilo->gs) ? ilo->gs : ilo->vs, p->cp);
  633.    }
  634. }
  635.  
  636. void
  637. gen6_pipeline_sf_rect(struct ilo_3d_pipeline *p,
  638.                       const struct ilo_context *ilo,
  639.                       struct gen6_pipeline_session *session)
  640. {
  641.    /* 3DSTATE_DRAWING_RECTANGLE */
  642.    if (DIRTY(FB)) {
  643.       if (p->dev->gen == ILO_GEN(6))
  644.          gen6_wa_pipe_control_post_sync(p, false);
  645.  
  646.       p->gen6_3DSTATE_DRAWING_RECTANGLE(p->dev, 0, 0,
  647.             ilo->fb.state.width, ilo->fb.state.height, p->cp);
  648.    }
  649. }
  650.  
  651. static void
  652. gen6_pipeline_wm(struct ilo_3d_pipeline *p,
  653.                  const struct ilo_context *ilo,
  654.                  struct gen6_pipeline_session *session)
  655. {
  656.    /* 3DSTATE_CONSTANT_PS */
  657.    if (session->pcb_state_fs_changed)
  658.       p->gen6_3DSTATE_CONSTANT_PS(p->dev, NULL, NULL, 0, p->cp);
  659.  
  660.    /* 3DSTATE_WM */
  661.    if (DIRTY(FS) || DIRTY(SAMPLER_FS) || DIRTY(BLEND) || DIRTY(DSA) ||
  662.        DIRTY(RASTERIZER) || session->kernel_bo_changed) {
  663.       const int num_samplers = ilo->sampler[PIPE_SHADER_FRAGMENT].count;
  664.       const bool dual_blend = ilo->blend->dual_blend;
  665.       const bool cc_may_kill = (ilo->dsa->alpha.enabled ||
  666.                                 ilo->blend->alpha_to_coverage);
  667.  
  668.       if (p->dev->gen == ILO_GEN(6) && session->hw_ctx_changed)
  669.          gen6_wa_pipe_control_wm_max_threads_stall(p);
  670.  
  671.       p->gen6_3DSTATE_WM(p->dev, ilo->fs, num_samplers,
  672.             ilo->rasterizer, dual_blend, cc_may_kill, p->cp);
  673.    }
  674. }
  675.  
  676. static void
  677. gen6_pipeline_wm_multisample(struct ilo_3d_pipeline *p,
  678.                              const struct ilo_context *ilo,
  679.                              struct gen6_pipeline_session *session)
  680. {
  681.    /* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
  682.    if (DIRTY(SAMPLE_MASK) || DIRTY(FB)) {
  683.       const uint32_t *packed_sample_pos;
  684.  
  685.       packed_sample_pos = (ilo->fb.num_samples > 1) ?
  686.          &p->packed_sample_position_4x : &p->packed_sample_position_1x;
  687.  
  688.       if (p->dev->gen == ILO_GEN(6)) {
  689.          gen6_wa_pipe_control_post_sync(p, false);
  690.          gen6_wa_pipe_control_wm_multisample_flush(p);
  691.       }
  692.  
  693.       p->gen6_3DSTATE_MULTISAMPLE(p->dev,
  694.             ilo->fb.num_samples, packed_sample_pos,
  695.             ilo->rasterizer->state.half_pixel_center, p->cp);
  696.  
  697.       p->gen6_3DSTATE_SAMPLE_MASK(p->dev,
  698.             (ilo->fb.num_samples > 1) ? ilo->sample_mask : 0x1, p->cp);
  699.    }
  700. }
  701.  
  702. static void
  703. gen6_pipeline_wm_depth(struct ilo_3d_pipeline *p,
  704.                        const struct ilo_context *ilo,
  705.                        struct gen6_pipeline_session *session)
  706. {
  707.    /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
  708.    if (DIRTY(FB) || session->batch_bo_changed) {
  709.       const struct ilo_zs_surface *zs;
  710.  
  711.       if (ilo->fb.state.zsbuf) {
  712.          const struct ilo_surface_cso *surface =
  713.             (const struct ilo_surface_cso *) ilo->fb.state.zsbuf;
  714.  
  715.          assert(!surface->is_rt);
  716.          zs = &surface->u.zs;
  717.       }
  718.       else {
  719.          zs = &ilo->fb.null_zs;
  720.       }
  721.  
  722.       if (p->dev->gen == ILO_GEN(6)) {
  723.          gen6_wa_pipe_control_post_sync(p, false);
  724.          gen6_wa_pipe_control_wm_depth_flush(p);
  725.       }
  726.  
  727.       p->gen6_3DSTATE_DEPTH_BUFFER(p->dev, zs, p->cp);
  728.  
  729.       /* TODO */
  730.       p->gen6_3DSTATE_CLEAR_PARAMS(p->dev, 0, p->cp);
  731.    }
  732. }
  733.  
  734. void
  735. gen6_pipeline_wm_raster(struct ilo_3d_pipeline *p,
  736.                         const struct ilo_context *ilo,
  737.                         struct gen6_pipeline_session *session)
  738. {
  739.    /* 3DSTATE_POLY_STIPPLE_PATTERN and 3DSTATE_POLY_STIPPLE_OFFSET */
  740.    if ((DIRTY(RASTERIZER) || DIRTY(POLY_STIPPLE)) &&
  741.        ilo->rasterizer->state.poly_stipple_enable) {
  742.       if (p->dev->gen == ILO_GEN(6))
  743.          gen6_wa_pipe_control_post_sync(p, false);
  744.  
  745.       p->gen6_3DSTATE_POLY_STIPPLE_PATTERN(p->dev,
  746.             &ilo->poly_stipple, p->cp);
  747.  
  748.       p->gen6_3DSTATE_POLY_STIPPLE_OFFSET(p->dev, 0, 0, p->cp);
  749.    }
  750.  
  751.    /* 3DSTATE_LINE_STIPPLE */
  752.    if (DIRTY(RASTERIZER) && ilo->rasterizer->state.line_stipple_enable) {
  753.       if (p->dev->gen == ILO_GEN(6))
  754.          gen6_wa_pipe_control_post_sync(p, false);
  755.  
  756.       p->gen6_3DSTATE_LINE_STIPPLE(p->dev,
  757.             ilo->rasterizer->state.line_stipple_pattern,
  758.             ilo->rasterizer->state.line_stipple_factor + 1, p->cp);
  759.    }
  760.  
  761.    /* 3DSTATE_AA_LINE_PARAMETERS */
  762.    if (DIRTY(RASTERIZER) && ilo->rasterizer->state.line_smooth) {
  763.       if (p->dev->gen == ILO_GEN(6))
  764.          gen6_wa_pipe_control_post_sync(p, false);
  765.  
  766.       p->gen6_3DSTATE_AA_LINE_PARAMETERS(p->dev, p->cp);
  767.    }
  768. }
  769.  
  770. static void
  771. gen6_pipeline_state_viewports(struct ilo_3d_pipeline *p,
  772.                               const struct ilo_context *ilo,
  773.                               struct gen6_pipeline_session *session)
  774. {
  775.    /* SF_CLIP_VIEWPORT and CC_VIEWPORT */
  776.    if (p->dev->gen >= ILO_GEN(7) && DIRTY(VIEWPORT)) {
  777.       p->state.SF_CLIP_VIEWPORT = p->gen7_SF_CLIP_VIEWPORT(p->dev,
  778.             ilo->viewport.cso, ilo->viewport.count, p->cp);
  779.  
  780.       p->state.CC_VIEWPORT = p->gen6_CC_VIEWPORT(p->dev,
  781.             ilo->viewport.cso, ilo->viewport.count, p->cp);
  782.  
  783.       session->viewport_state_changed = true;
  784.    }
  785.    /* SF_VIEWPORT, CLIP_VIEWPORT, and CC_VIEWPORT */
  786.    else if (DIRTY(VIEWPORT)) {
  787.       p->state.CLIP_VIEWPORT = p->gen6_CLIP_VIEWPORT(p->dev,
  788.             ilo->viewport.cso, ilo->viewport.count, p->cp);
  789.  
  790.       p->state.SF_VIEWPORT = p->gen6_SF_VIEWPORT(p->dev,
  791.             ilo->viewport.cso, ilo->viewport.count, p->cp);
  792.  
  793.       p->state.CC_VIEWPORT = p->gen6_CC_VIEWPORT(p->dev,
  794.             ilo->viewport.cso, ilo->viewport.count, p->cp);
  795.  
  796.       session->viewport_state_changed = true;
  797.    }
  798. }
  799.  
  800. static void
  801. gen6_pipeline_state_cc(struct ilo_3d_pipeline *p,
  802.                        const struct ilo_context *ilo,
  803.                        struct gen6_pipeline_session *session)
  804. {
  805.    /* BLEND_STATE */
  806.    if (DIRTY(BLEND) || DIRTY(FB) || DIRTY(DSA)) {
  807.       p->state.BLEND_STATE = p->gen6_BLEND_STATE(p->dev,
  808.             ilo->blend, &ilo->fb, &ilo->dsa->alpha, p->cp);
  809.  
  810.       session->cc_state_blend_changed = true;
  811.    }
  812.  
  813.    /* COLOR_CALC_STATE */
  814.    if (DIRTY(DSA) || DIRTY(STENCIL_REF) || DIRTY(BLEND_COLOR)) {
  815.       p->state.COLOR_CALC_STATE =
  816.          p->gen6_COLOR_CALC_STATE(p->dev, &ilo->stencil_ref,
  817.                ilo->dsa->alpha.ref_value, &ilo->blend_color, p->cp);
  818.  
  819.       session->cc_state_cc_changed = true;
  820.    }
  821.  
  822.    /* DEPTH_STENCIL_STATE */
  823.    if (DIRTY(DSA)) {
  824.       p->state.DEPTH_STENCIL_STATE =
  825.          p->gen6_DEPTH_STENCIL_STATE(p->dev, ilo->dsa, p->cp);
  826.  
  827.       session->cc_state_dsa_changed = true;
  828.    }
  829. }
  830.  
  831. static void
  832. gen6_pipeline_state_scissors(struct ilo_3d_pipeline *p,
  833.                              const struct ilo_context *ilo,
  834.                              struct gen6_pipeline_session *session)
  835. {
  836.    /* SCISSOR_RECT */
  837.    if (DIRTY(SCISSOR) || DIRTY(VIEWPORT)) {
  838.       /* there should be as many scissors as there are viewports */
  839.       p->state.SCISSOR_RECT = p->gen6_SCISSOR_RECT(p->dev,
  840.             &ilo->scissor, ilo->viewport.count, p->cp);
  841.  
  842.       session->scissor_state_changed = true;
  843.    }
  844. }
  845.  
  846. static void
  847. gen6_pipeline_state_surfaces_rt(struct ilo_3d_pipeline *p,
  848.                                 const struct ilo_context *ilo,
  849.                                 struct gen6_pipeline_session *session)
  850. {
  851.    /* SURFACE_STATEs for render targets */
  852.    if (DIRTY(FB)) {
  853.       const struct ilo_fb_state *fb = &ilo->fb;
  854.       const int offset = ILO_WM_DRAW_SURFACE(0);
  855.       uint32_t *surface_state = &p->state.wm.SURFACE_STATE[offset];
  856.       int i;
  857.  
  858.       for (i = 0; i < fb->state.nr_cbufs; i++) {
  859.          const struct ilo_surface_cso *surface =
  860.             (const struct ilo_surface_cso *) fb->state.cbufs[i];
  861.  
  862.          assert(surface && surface->is_rt);
  863.          surface_state[i] =
  864.             p->gen6_SURFACE_STATE(p->dev, &surface->u.rt, true, p->cp);
  865.       }
  866.  
  867.       /*
  868.        * Upload at least one render target, as
  869.        * brw_update_renderbuffer_surfaces() does.  I don't know why.
  870.        */
  871.       if (i == 0) {
  872.          struct ilo_view_surface null_surface;
  873.  
  874.          ilo_gpe_init_view_surface_null(p->dev,
  875.                fb->state.width, fb->state.height,
  876.                1, 0, &null_surface);
  877.  
  878.          surface_state[i] =
  879.             p->gen6_SURFACE_STATE(p->dev, &null_surface, true, p->cp);
  880.  
  881.          i++;
  882.       }
  883.  
  884.       memset(&surface_state[i], 0, (ILO_MAX_DRAW_BUFFERS - i) * 4);
  885.  
  886.       if (i && session->num_surfaces[PIPE_SHADER_FRAGMENT] < offset + i)
  887.          session->num_surfaces[PIPE_SHADER_FRAGMENT] = offset + i;
  888.  
  889.       session->binding_table_fs_changed = true;
  890.    }
  891. }
  892.  
  893. static void
  894. gen6_pipeline_state_surfaces_so(struct ilo_3d_pipeline *p,
  895.                                 const struct ilo_context *ilo,
  896.                                 struct gen6_pipeline_session *session)
  897. {
  898.    const struct ilo_so_state *so = &ilo->so;
  899.  
  900.    if (p->dev->gen != ILO_GEN(6))
  901.       return;
  902.  
  903.    /* SURFACE_STATEs for stream output targets */
  904.    if (DIRTY(VS) || DIRTY(GS) || DIRTY(SO)) {
  905.       const struct pipe_stream_output_info *so_info =
  906.          (ilo->gs) ? ilo_shader_get_kernel_so_info(ilo->gs) :
  907.          (ilo->vs) ? ilo_shader_get_kernel_so_info(ilo->vs) : NULL;
  908.       const int offset = ILO_GS_SO_SURFACE(0);
  909.       uint32_t *surface_state = &p->state.gs.SURFACE_STATE[offset];
  910.       int i;
  911.  
  912.       for (i = 0; so_info && i < so_info->num_outputs; i++) {
  913.          const int target = so_info->output[i].output_buffer;
  914.          const struct pipe_stream_output_target *so_target =
  915.             (target < so->count) ? so->states[target] : NULL;
  916.  
  917.          if (so_target) {
  918.             surface_state[i] = p->gen6_so_SURFACE_STATE(p->dev,
  919.                   so_target, so_info, i, p->cp);
  920.          }
  921.          else {
  922.             surface_state[i] = 0;
  923.          }
  924.       }
  925.  
  926.       memset(&surface_state[i], 0, (ILO_MAX_SO_BINDINGS - i) * 4);
  927.  
  928.       if (i && session->num_surfaces[PIPE_SHADER_GEOMETRY] < offset + i)
  929.          session->num_surfaces[PIPE_SHADER_GEOMETRY] = offset + i;
  930.  
  931.       session->binding_table_gs_changed = true;
  932.    }
  933. }
  934.  
  935. static void
  936. gen6_pipeline_state_surfaces_view(struct ilo_3d_pipeline *p,
  937.                                   const struct ilo_context *ilo,
  938.                                   int shader_type,
  939.                                   struct gen6_pipeline_session *session)
  940. {
  941.    const struct ilo_view_state *view = &ilo->view[shader_type];
  942.    uint32_t *surface_state;
  943.    int offset, i;
  944.    bool skip = false;
  945.  
  946.    /* SURFACE_STATEs for sampler views */
  947.    switch (shader_type) {
  948.    case PIPE_SHADER_VERTEX:
  949.       if (DIRTY(VIEW_VS)) {
  950.          offset = ILO_VS_TEXTURE_SURFACE(0);
  951.          surface_state = &p->state.vs.SURFACE_STATE[offset];
  952.  
  953.          session->binding_table_vs_changed = true;
  954.       }
  955.       else {
  956.          skip = true;
  957.       }
  958.       break;
  959.    case PIPE_SHADER_FRAGMENT:
  960.       if (DIRTY(VIEW_FS)) {
  961.          offset = ILO_WM_TEXTURE_SURFACE(0);
  962.          surface_state = &p->state.wm.SURFACE_STATE[offset];
  963.  
  964.          session->binding_table_fs_changed = true;
  965.       }
  966.       else {
  967.          skip = true;
  968.       }
  969.       break;
  970.    default:
  971.       skip = true;
  972.       break;
  973.    }
  974.  
  975.    if (skip)
  976.       return;
  977.  
  978.    for (i = 0; i < view->count; i++) {
  979.       if (view->states[i]) {
  980.          const struct ilo_view_cso *cso =
  981.             (const struct ilo_view_cso *) view->states[i];
  982.  
  983.          surface_state[i] =
  984.             p->gen6_SURFACE_STATE(p->dev, &cso->surface, false, p->cp);
  985.       }
  986.       else {
  987.          surface_state[i] = 0;
  988.       }
  989.    }
  990.  
  991.    memset(&surface_state[i], 0, (ILO_MAX_SAMPLER_VIEWS - i) * 4);
  992.  
  993.    if (i && session->num_surfaces[shader_type] < offset + i)
  994.       session->num_surfaces[shader_type] = offset + i;
  995. }
  996.  
  997. static void
  998. gen6_pipeline_state_surfaces_const(struct ilo_3d_pipeline *p,
  999.                                    const struct ilo_context *ilo,
  1000.                                    int shader_type,
  1001.                                    struct gen6_pipeline_session *session)
  1002. {
  1003.    const struct ilo_cbuf_state *cbuf = &ilo->cbuf[shader_type];
  1004.    uint32_t *surface_state;
  1005.    int offset, count, i;
  1006.    bool skip = false;
  1007.  
  1008.    /* SURFACE_STATEs for constant buffers */
  1009.    switch (shader_type) {
  1010.    case PIPE_SHADER_VERTEX:
  1011.       if (DIRTY(CBUF)) {
  1012.          offset = ILO_VS_CONST_SURFACE(0);
  1013.          surface_state = &p->state.vs.SURFACE_STATE[offset];
  1014.  
  1015.          session->binding_table_vs_changed = true;
  1016.       }
  1017.       else {
  1018.          skip = true;
  1019.       }
  1020.       break;
  1021.    case PIPE_SHADER_FRAGMENT:
  1022.       if (DIRTY(CBUF)) {
  1023.          offset = ILO_WM_CONST_SURFACE(0);
  1024.          surface_state = &p->state.wm.SURFACE_STATE[offset];
  1025.  
  1026.          session->binding_table_fs_changed = true;
  1027.       }
  1028.       else {
  1029.          skip = true;
  1030.       }
  1031.       break;
  1032.    default:
  1033.       skip = true;
  1034.       break;
  1035.    }
  1036.  
  1037.    if (skip)
  1038.       return;
  1039.  
  1040.    count = util_last_bit(cbuf->enabled_mask);
  1041.    for (i = 0; i < count; i++) {
  1042.       if (cbuf->cso[i].resource) {
  1043.          surface_state[i] = p->gen6_SURFACE_STATE(p->dev,
  1044.                &cbuf->cso[i].surface, false, p->cp);
  1045.       }
  1046.       else {
  1047.          surface_state[i] = 0;
  1048.       }
  1049.    }
  1050.  
  1051.    memset(&surface_state[count], 0, (ILO_MAX_CONST_BUFFERS - count) * 4);
  1052.  
  1053.    if (count && session->num_surfaces[shader_type] < offset + count)
  1054.       session->num_surfaces[shader_type] = offset + count;
  1055. }
  1056.  
  1057. static void
  1058. gen6_pipeline_state_binding_tables(struct ilo_3d_pipeline *p,
  1059.                                    const struct ilo_context *ilo,
  1060.                                    int shader_type,
  1061.                                    struct gen6_pipeline_session *session)
  1062. {
  1063.    uint32_t *binding_table_state, *surface_state;
  1064.    int *binding_table_state_size, size;
  1065.    bool skip = false;
  1066.  
  1067.    /* BINDING_TABLE_STATE */
  1068.    switch (shader_type) {
  1069.    case PIPE_SHADER_VERTEX:
  1070.       surface_state = p->state.vs.SURFACE_STATE;
  1071.       binding_table_state = &p->state.vs.BINDING_TABLE_STATE;
  1072.       binding_table_state_size = &p->state.vs.BINDING_TABLE_STATE_size;
  1073.  
  1074.       skip = !session->binding_table_vs_changed;
  1075.       break;
  1076.    case PIPE_SHADER_GEOMETRY:
  1077.       surface_state = p->state.gs.SURFACE_STATE;
  1078.       binding_table_state = &p->state.gs.BINDING_TABLE_STATE;
  1079.       binding_table_state_size = &p->state.gs.BINDING_TABLE_STATE_size;
  1080.  
  1081.       skip = !session->binding_table_gs_changed;
  1082.       break;
  1083.    case PIPE_SHADER_FRAGMENT:
  1084.       surface_state = p->state.wm.SURFACE_STATE;
  1085.       binding_table_state = &p->state.wm.BINDING_TABLE_STATE;
  1086.       binding_table_state_size = &p->state.wm.BINDING_TABLE_STATE_size;
  1087.  
  1088.       skip = !session->binding_table_fs_changed;
  1089.       break;
  1090.    default:
  1091.       skip = true;
  1092.       break;
  1093.    }
  1094.  
  1095.    if (skip)
  1096.       return;
  1097.  
  1098.    /*
  1099.     * If we have seemingly less SURFACE_STATEs than before, it could be that
  1100.     * we did not touch those reside at the tail in this upload.  Loop over
  1101.     * them to figure out the real number of SURFACE_STATEs.
  1102.     */
  1103.    for (size = *binding_table_state_size;
  1104.          size > session->num_surfaces[shader_type]; size--) {
  1105.       if (surface_state[size - 1])
  1106.          break;
  1107.    }
  1108.    if (size < session->num_surfaces[shader_type])
  1109.       size = session->num_surfaces[shader_type];
  1110.  
  1111.    *binding_table_state = p->gen6_BINDING_TABLE_STATE(p->dev,
  1112.          surface_state, size, p->cp);
  1113.    *binding_table_state_size = size;
  1114. }
  1115.  
  1116. static void
  1117. gen6_pipeline_state_samplers(struct ilo_3d_pipeline *p,
  1118.                              const struct ilo_context *ilo,
  1119.                              int shader_type,
  1120.                              struct gen6_pipeline_session *session)
  1121. {
  1122.    const struct ilo_sampler_cso * const *samplers =
  1123.       ilo->sampler[shader_type].cso;
  1124.    const struct pipe_sampler_view * const *views =
  1125.       (const struct pipe_sampler_view **) ilo->view[shader_type].states;
  1126.    const int num_samplers = ilo->sampler[shader_type].count;
  1127.    const int num_views = ilo->view[shader_type].count;
  1128.    uint32_t *sampler_state, *border_color_state;
  1129.    bool emit_border_color = false;
  1130.    bool skip = false;
  1131.  
  1132.    /* SAMPLER_BORDER_COLOR_STATE and SAMPLER_STATE */
  1133.    switch (shader_type) {
  1134.    case PIPE_SHADER_VERTEX:
  1135.       if (DIRTY(SAMPLER_VS) || DIRTY(VIEW_VS)) {
  1136.          sampler_state = &p->state.vs.SAMPLER_STATE;
  1137.          border_color_state = p->state.vs.SAMPLER_BORDER_COLOR_STATE;
  1138.  
  1139.          if (DIRTY(SAMPLER_VS))
  1140.             emit_border_color = true;
  1141.  
  1142.          session->sampler_state_vs_changed = true;
  1143.       }
  1144.       else {
  1145.          skip = true;
  1146.       }
  1147.       break;
  1148.    case PIPE_SHADER_FRAGMENT:
  1149.       if (DIRTY(SAMPLER_FS) || DIRTY(VIEW_FS)) {
  1150.          sampler_state = &p->state.wm.SAMPLER_STATE;
  1151.          border_color_state = p->state.wm.SAMPLER_BORDER_COLOR_STATE;
  1152.  
  1153.          if (DIRTY(SAMPLER_FS))
  1154.             emit_border_color = true;
  1155.  
  1156.          session->sampler_state_fs_changed = true;
  1157.       }
  1158.       else {
  1159.          skip = true;
  1160.       }
  1161.       break;
  1162.    default:
  1163.       skip = true;
  1164.       break;
  1165.    }
  1166.  
  1167.    if (skip)
  1168.       return;
  1169.  
  1170.    if (emit_border_color) {
  1171.       int i;
  1172.  
  1173.       for (i = 0; i < num_samplers; i++) {
  1174.          border_color_state[i] = (samplers[i]) ?
  1175.             p->gen6_SAMPLER_BORDER_COLOR_STATE(p->dev,
  1176.                   samplers[i], p->cp) : 0;
  1177.       }
  1178.    }
  1179.  
  1180.    /* should we take the minimum of num_samplers and num_views? */
  1181.    *sampler_state = p->gen6_SAMPLER_STATE(p->dev,
  1182.          samplers, views,
  1183.          border_color_state,
  1184.          MIN2(num_samplers, num_views), p->cp);
  1185. }
  1186.  
  1187. static void
  1188. gen6_pipeline_state_pcb(struct ilo_3d_pipeline *p,
  1189.                         const struct ilo_context *ilo,
  1190.                         struct gen6_pipeline_session *session)
  1191. {
  1192.    /* push constant buffer for VS */
  1193.    if (DIRTY(VS) || DIRTY(CLIP)) {
  1194.       const int clip_state_size = (ilo->vs) ?
  1195.             ilo_shader_get_kernel_param(ilo->vs,
  1196.                   ILO_KERNEL_VS_PCB_UCP_SIZE) : 0;
  1197.  
  1198.       if (clip_state_size) {
  1199.          void *pcb;
  1200.  
  1201.          p->state.vs.PUSH_CONSTANT_BUFFER_size = clip_state_size;
  1202.          p->state.vs.PUSH_CONSTANT_BUFFER =
  1203.             p->gen6_push_constant_buffer(p->dev,
  1204.                   p->state.vs.PUSH_CONSTANT_BUFFER_size, &pcb, p->cp);
  1205.  
  1206.          memcpy(pcb, &ilo->clip, clip_state_size);
  1207.       }
  1208.       else {
  1209.          p->state.vs.PUSH_CONSTANT_BUFFER_size = 0;
  1210.          p->state.vs.PUSH_CONSTANT_BUFFER = 0;
  1211.       }
  1212.  
  1213.       session->pcb_state_vs_changed = true;
  1214.    }
  1215. }
  1216.  
  1217. #undef DIRTY
  1218.  
  1219. static void
  1220. gen6_pipeline_commands(struct ilo_3d_pipeline *p,
  1221.                        const struct ilo_context *ilo,
  1222.                        struct gen6_pipeline_session *session)
  1223. {
  1224.    /*
  1225.     * We try to keep the order of the commands match, as closely as possible,
  1226.     * that of the classic i965 driver.  It allows us to compare the command
  1227.     * streams easily.
  1228.     */
  1229.    gen6_pipeline_common_select(p, ilo, session);
  1230.    gen6_pipeline_gs_svbi(p, ilo, session);
  1231.    gen6_pipeline_common_sip(p, ilo, session);
  1232.    gen6_pipeline_vf_statistics(p, ilo, session);
  1233.    gen6_pipeline_common_base_address(p, ilo, session);
  1234.    gen6_pipeline_common_pointers_1(p, ilo, session);
  1235.    gen6_pipeline_common_urb(p, ilo, session);
  1236.    gen6_pipeline_common_pointers_2(p, ilo, session);
  1237.    gen6_pipeline_wm_multisample(p, ilo, session);
  1238.    gen6_pipeline_vs(p, ilo, session);
  1239.    gen6_pipeline_gs(p, ilo, session);
  1240.    gen6_pipeline_clip(p, ilo, session);
  1241.    gen6_pipeline_sf(p, ilo, session);
  1242.    gen6_pipeline_wm(p, ilo, session);
  1243.    gen6_pipeline_common_pointers_3(p, ilo, session);
  1244.    gen6_pipeline_wm_depth(p, ilo, session);
  1245.    gen6_pipeline_wm_raster(p, ilo, session);
  1246.    gen6_pipeline_sf_rect(p, ilo, session);
  1247.    gen6_pipeline_vf(p, ilo, session);
  1248.    gen6_pipeline_vf_draw(p, ilo, session);
  1249. }
  1250.  
  1251. void
  1252. gen6_pipeline_states(struct ilo_3d_pipeline *p,
  1253.                      const struct ilo_context *ilo,
  1254.                      struct gen6_pipeline_session *session)
  1255. {
  1256.    int shader_type;
  1257.  
  1258.    gen6_pipeline_state_viewports(p, ilo, session);
  1259.    gen6_pipeline_state_cc(p, ilo, session);
  1260.    gen6_pipeline_state_scissors(p, ilo, session);
  1261.    gen6_pipeline_state_pcb(p, ilo, session);
  1262.  
  1263.    /*
  1264.     * upload all SURAFCE_STATEs together so that we know there are minimal
  1265.     * paddings
  1266.     */
  1267.    gen6_pipeline_state_surfaces_rt(p, ilo, session);
  1268.    gen6_pipeline_state_surfaces_so(p, ilo, session);
  1269.    for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
  1270.       gen6_pipeline_state_surfaces_view(p, ilo, shader_type, session);
  1271.       gen6_pipeline_state_surfaces_const(p, ilo, shader_type, session);
  1272.    }
  1273.  
  1274.    for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
  1275.       gen6_pipeline_state_samplers(p, ilo, shader_type, session);
  1276.       /* this must be called after all SURFACE_STATEs are uploaded */
  1277.       gen6_pipeline_state_binding_tables(p, ilo, shader_type, session);
  1278.    }
  1279. }
  1280.  
  1281. void
  1282. gen6_pipeline_prepare(const struct ilo_3d_pipeline *p,
  1283.                       const struct ilo_context *ilo,
  1284.                       struct gen6_pipeline_session *session)
  1285. {
  1286.    memset(session, 0, sizeof(*session));
  1287.    session->pipe_dirty = ilo->dirty;
  1288.    session->reduced_prim = u_reduced_prim(ilo->draw->mode);
  1289.  
  1290.    /* available space before the session */
  1291.    session->init_cp_space = ilo_cp_space(p->cp);
  1292.  
  1293.    session->hw_ctx_changed =
  1294.       (p->invalidate_flags & ILO_3D_PIPELINE_INVALIDATE_HW);
  1295.  
  1296.    if (session->hw_ctx_changed) {
  1297.       /* these should be enough to make everything uploaded */
  1298.       session->batch_bo_changed = true;
  1299.       session->state_bo_changed = true;
  1300.       session->kernel_bo_changed = true;
  1301.       session->prim_changed = true;
  1302.       session->primitive_restart_changed = true;
  1303.    }
  1304.    else {
  1305.       /*
  1306.        * Any state that involves resources needs to be re-emitted when the
  1307.        * batch bo changed.  This is because we do not pin the resources and
  1308.        * their offsets (or existence) may change between batch buffers.
  1309.        *
  1310.        * Since we messed around with ILO_3D_PIPELINE_INVALIDATE_BATCH_BO in
  1311.        * handle_invalid_batch_bo(), use ILO_3D_PIPELINE_INVALIDATE_STATE_BO as
  1312.        * a temporary workaround.
  1313.        */
  1314.       session->batch_bo_changed =
  1315.          (p->invalidate_flags & ILO_3D_PIPELINE_INVALIDATE_STATE_BO);
  1316.  
  1317.       session->state_bo_changed =
  1318.          (p->invalidate_flags & ILO_3D_PIPELINE_INVALIDATE_STATE_BO);
  1319.       session->kernel_bo_changed =
  1320.          (p->invalidate_flags & ILO_3D_PIPELINE_INVALIDATE_KERNEL_BO);
  1321.       session->prim_changed = (p->state.reduced_prim != session->reduced_prim);
  1322.       session->primitive_restart_changed =
  1323.          (p->state.primitive_restart != ilo->draw->primitive_restart);
  1324.    }
  1325. }
  1326.  
  1327. void
  1328. gen6_pipeline_draw(struct ilo_3d_pipeline *p,
  1329.                    const struct ilo_context *ilo,
  1330.                    struct gen6_pipeline_session *session)
  1331. {
  1332.    /* force all states to be uploaded if the state bo changed */
  1333.    if (session->state_bo_changed)
  1334.       session->pipe_dirty = ILO_DIRTY_ALL;
  1335.    else
  1336.       session->pipe_dirty = ilo->dirty;
  1337.  
  1338.    session->emit_draw_states(p, ilo, session);
  1339.  
  1340.    /* force all commands to be uploaded if the HW context changed */
  1341.    if (session->hw_ctx_changed)
  1342.       session->pipe_dirty = ILO_DIRTY_ALL;
  1343.    else
  1344.       session->pipe_dirty = ilo->dirty;
  1345.  
  1346.    session->emit_draw_commands(p, ilo, session);
  1347. }
  1348.  
  1349. void
  1350. gen6_pipeline_end(struct ilo_3d_pipeline *p,
  1351.                   const struct ilo_context *ilo,
  1352.                   struct gen6_pipeline_session *session)
  1353. {
  1354.    /* sanity check size estimation */
  1355.    assert(session->init_cp_space - ilo_cp_space(p->cp) <=
  1356.          ilo_3d_pipeline_estimate_size(p, ILO_3D_PIPELINE_DRAW, ilo));
  1357.  
  1358.    p->state.reduced_prim = session->reduced_prim;
  1359.    p->state.primitive_restart = ilo->draw->primitive_restart;
  1360. }
  1361.  
  1362. static void
  1363. ilo_3d_pipeline_emit_draw_gen6(struct ilo_3d_pipeline *p,
  1364.                                const struct ilo_context *ilo)
  1365. {
  1366.    struct gen6_pipeline_session session;
  1367.  
  1368.    gen6_pipeline_prepare(p, ilo, &session);
  1369.  
  1370.    session.emit_draw_states = gen6_pipeline_states;
  1371.    session.emit_draw_commands = gen6_pipeline_commands;
  1372.  
  1373.    gen6_pipeline_draw(p, ilo, &session);
  1374.    gen6_pipeline_end(p, ilo, &session);
  1375. }
  1376.  
  1377. void
  1378. ilo_3d_pipeline_emit_flush_gen6(struct ilo_3d_pipeline *p)
  1379. {
  1380.    if (p->dev->gen == ILO_GEN(6))
  1381.       gen6_wa_pipe_control_post_sync(p, false);
  1382.  
  1383.    p->gen6_PIPE_CONTROL(p->dev,
  1384.          PIPE_CONTROL_INSTRUCTION_FLUSH |
  1385.          PIPE_CONTROL_WRITE_FLUSH |
  1386.          PIPE_CONTROL_DEPTH_CACHE_FLUSH |
  1387.          PIPE_CONTROL_VF_CACHE_INVALIDATE |
  1388.          PIPE_CONTROL_TC_FLUSH |
  1389.          PIPE_CONTROL_NO_WRITE |
  1390.          PIPE_CONTROL_CS_STALL,
  1391.          0, 0, false, p->cp);
  1392. }
  1393.  
  1394. void
  1395. ilo_3d_pipeline_emit_write_timestamp_gen6(struct ilo_3d_pipeline *p,
  1396.                                           struct intel_bo *bo, int index)
  1397. {
  1398.    if (p->dev->gen == ILO_GEN(6))
  1399.       gen6_wa_pipe_control_post_sync(p, true);
  1400.  
  1401.    p->gen6_PIPE_CONTROL(p->dev,
  1402.          PIPE_CONTROL_WRITE_TIMESTAMP,
  1403.          bo, index * sizeof(uint64_t) | PIPE_CONTROL_GLOBAL_GTT_WRITE,
  1404.          true, p->cp);
  1405. }
  1406.  
  1407. void
  1408. ilo_3d_pipeline_emit_write_depth_count_gen6(struct ilo_3d_pipeline *p,
  1409.                                             struct intel_bo *bo, int index)
  1410. {
  1411.    if (p->dev->gen == ILO_GEN(6))
  1412.       gen6_wa_pipe_control_post_sync(p, false);
  1413.  
  1414.    p->gen6_PIPE_CONTROL(p->dev,
  1415.          PIPE_CONTROL_DEPTH_STALL |
  1416.          PIPE_CONTROL_WRITE_DEPTH_COUNT,
  1417.          bo, index * sizeof(uint64_t) | PIPE_CONTROL_GLOBAL_GTT_WRITE,
  1418.          true, p->cp);
  1419. }
  1420.  
  1421. static int
  1422. gen6_pipeline_estimate_commands(const struct ilo_3d_pipeline *p,
  1423.                                 const struct ilo_gpe_gen6 *gen6,
  1424.                                 const struct ilo_context *ilo)
  1425. {
  1426.    static int size;
  1427.    enum ilo_gpe_gen6_command cmd;
  1428.  
  1429.    if (size)
  1430.       return size;
  1431.  
  1432.    for (cmd = 0; cmd < ILO_GPE_GEN6_COMMAND_COUNT; cmd++) {
  1433.       int count;
  1434.  
  1435.       switch (cmd) {
  1436.       case ILO_GPE_GEN6_PIPE_CONTROL:
  1437.          /* for the workaround */
  1438.          count = 2;
  1439.          /* another one after 3DSTATE_URB */
  1440.          count += 1;
  1441.          /* and another one after 3DSTATE_CONSTANT_VS */
  1442.          count += 1;
  1443.          break;
  1444.       case ILO_GPE_GEN6_3DSTATE_GS_SVB_INDEX:
  1445.          /* there are 4 SVBIs */
  1446.          count = 4;
  1447.          break;
  1448.       case ILO_GPE_GEN6_3DSTATE_VERTEX_BUFFERS:
  1449.          count = 33;
  1450.          break;
  1451.       case ILO_GPE_GEN6_3DSTATE_VERTEX_ELEMENTS:
  1452.          count = 34;
  1453.          break;
  1454.       case ILO_GPE_GEN6_MEDIA_VFE_STATE:
  1455.       case ILO_GPE_GEN6_MEDIA_CURBE_LOAD:
  1456.       case ILO_GPE_GEN6_MEDIA_INTERFACE_DESCRIPTOR_LOAD:
  1457.       case ILO_GPE_GEN6_MEDIA_GATEWAY_STATE:
  1458.       case ILO_GPE_GEN6_MEDIA_STATE_FLUSH:
  1459.       case ILO_GPE_GEN6_MEDIA_OBJECT_WALKER:
  1460.          /* media commands */
  1461.          count = 0;
  1462.          break;
  1463.       default:
  1464.          count = 1;
  1465.          break;
  1466.       }
  1467.  
  1468.       if (count)
  1469.          size += gen6->estimate_command_size(p->dev, cmd, count);
  1470.    }
  1471.  
  1472.    return size;
  1473. }
  1474.  
  1475. static int
  1476. gen6_pipeline_estimate_states(const struct ilo_3d_pipeline *p,
  1477.                               const struct ilo_gpe_gen6 *gen6,
  1478.                               const struct ilo_context *ilo)
  1479. {
  1480.    static int static_size;
  1481.    int shader_type, count, size;
  1482.  
  1483.    if (!static_size) {
  1484.       struct {
  1485.          enum ilo_gpe_gen6_state state;
  1486.          int count;
  1487.       } static_states[] = {
  1488.          /* viewports */
  1489.          { ILO_GPE_GEN6_SF_VIEWPORT,                 1 },
  1490.          { ILO_GPE_GEN6_CLIP_VIEWPORT,               1 },
  1491.          { ILO_GPE_GEN6_CC_VIEWPORT,                 1 },
  1492.          /* cc */
  1493.          { ILO_GPE_GEN6_COLOR_CALC_STATE,            1 },
  1494.          { ILO_GPE_GEN6_BLEND_STATE,                 ILO_MAX_DRAW_BUFFERS },
  1495.          { ILO_GPE_GEN6_DEPTH_STENCIL_STATE,         1 },
  1496.          /* scissors */
  1497.          { ILO_GPE_GEN6_SCISSOR_RECT,                1 },
  1498.          /* binding table (vs, gs, fs) */
  1499.          { ILO_GPE_GEN6_BINDING_TABLE_STATE,         ILO_MAX_VS_SURFACES },
  1500.          { ILO_GPE_GEN6_BINDING_TABLE_STATE,         ILO_MAX_GS_SURFACES },
  1501.          { ILO_GPE_GEN6_BINDING_TABLE_STATE,         ILO_MAX_WM_SURFACES },
  1502.       };
  1503.       int i;
  1504.  
  1505.       for (i = 0; i < Elements(static_states); i++) {
  1506.          static_size += gen6->estimate_state_size(p->dev,
  1507.                static_states[i].state,
  1508.                static_states[i].count);
  1509.       }
  1510.    }
  1511.  
  1512.    size = static_size;
  1513.  
  1514.    /*
  1515.     * render targets (fs)
  1516.     * stream outputs (gs)
  1517.     * sampler views (vs, fs)
  1518.     * constant buffers (vs, fs)
  1519.     */
  1520.    count = ilo->fb.state.nr_cbufs;
  1521.  
  1522.    if (ilo->gs) {
  1523.       const struct pipe_stream_output_info *so_info =
  1524.          ilo_shader_get_kernel_so_info(ilo->gs);
  1525.  
  1526.       count += so_info->num_outputs;
  1527.    }
  1528.    else if (ilo->vs) {
  1529.       const struct pipe_stream_output_info *so_info =
  1530.          ilo_shader_get_kernel_so_info(ilo->vs);
  1531.  
  1532.       count += so_info->num_outputs;
  1533.    }
  1534.  
  1535.    for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
  1536.       count += ilo->view[shader_type].count;
  1537.       count += util_bitcount(ilo->cbuf[shader_type].enabled_mask);
  1538.    }
  1539.  
  1540.    if (count) {
  1541.       size += gen6->estimate_state_size(p->dev,
  1542.             ILO_GPE_GEN6_SURFACE_STATE, count);
  1543.    }
  1544.  
  1545.    /* samplers (vs, fs) */
  1546.    for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
  1547.       count = ilo->sampler[shader_type].count;
  1548.       if (count) {
  1549.          size += gen6->estimate_state_size(p->dev,
  1550.                ILO_GPE_GEN6_SAMPLER_BORDER_COLOR_STATE, count);
  1551.          size += gen6->estimate_state_size(p->dev,
  1552.                ILO_GPE_GEN6_SAMPLER_STATE, count);
  1553.       }
  1554.    }
  1555.  
  1556.    /* pcb (vs) */
  1557.    if (ilo->vs &&
  1558.        ilo_shader_get_kernel_param(ilo->vs, ILO_KERNEL_VS_PCB_UCP_SIZE)) {
  1559.       const int pcb_size =
  1560.          ilo_shader_get_kernel_param(ilo->vs, ILO_KERNEL_VS_PCB_UCP_SIZE);
  1561.  
  1562.       size += gen6->estimate_state_size(p->dev,
  1563.             ILO_GPE_GEN6_PUSH_CONSTANT_BUFFER, pcb_size);
  1564.    }
  1565.  
  1566.    return size;
  1567. }
  1568.  
  1569. static int
  1570. ilo_3d_pipeline_estimate_size_gen6(struct ilo_3d_pipeline *p,
  1571.                                    enum ilo_3d_pipeline_action action,
  1572.                                    const void *arg)
  1573. {
  1574.    const struct ilo_gpe_gen6 *gen6 = ilo_gpe_gen6_get();
  1575.    int size;
  1576.  
  1577.    switch (action) {
  1578.    case ILO_3D_PIPELINE_DRAW:
  1579.       {
  1580.          const struct ilo_context *ilo = arg;
  1581.  
  1582.          size = gen6_pipeline_estimate_commands(p, gen6, ilo) +
  1583.             gen6_pipeline_estimate_states(p, gen6, ilo);
  1584.       }
  1585.       break;
  1586.    case ILO_3D_PIPELINE_FLUSH:
  1587.       size = gen6->estimate_command_size(p->dev,
  1588.             ILO_GPE_GEN6_PIPE_CONTROL, 1) * 3;
  1589.       break;
  1590.    case ILO_3D_PIPELINE_WRITE_TIMESTAMP:
  1591.       size = gen6->estimate_command_size(p->dev,
  1592.             ILO_GPE_GEN6_PIPE_CONTROL, 1) * 2;
  1593.       break;
  1594.    case ILO_3D_PIPELINE_WRITE_DEPTH_COUNT:
  1595.       size = gen6->estimate_command_size(p->dev,
  1596.             ILO_GPE_GEN6_PIPE_CONTROL, 1) * 3;
  1597.       break;
  1598.    default:
  1599.       assert(!"unknown 3D pipeline action");
  1600.       size = 0;
  1601.       break;
  1602.    }
  1603.  
  1604.    return size;
  1605. }
  1606.  
  1607. void
  1608. ilo_3d_pipeline_init_gen6(struct ilo_3d_pipeline *p)
  1609. {
  1610.    const struct ilo_gpe_gen6 *gen6 = ilo_gpe_gen6_get();
  1611.  
  1612.    p->estimate_size = ilo_3d_pipeline_estimate_size_gen6;
  1613.    p->emit_draw = ilo_3d_pipeline_emit_draw_gen6;
  1614.    p->emit_flush = ilo_3d_pipeline_emit_flush_gen6;
  1615.    p->emit_write_timestamp = ilo_3d_pipeline_emit_write_timestamp_gen6;
  1616.    p->emit_write_depth_count = ilo_3d_pipeline_emit_write_depth_count_gen6;
  1617.  
  1618. #define GEN6_USE(p, name, from) \
  1619.    p->gen6_ ## name = from->emit_ ## name
  1620.    GEN6_USE(p, STATE_BASE_ADDRESS, gen6);
  1621.    GEN6_USE(p, STATE_SIP, gen6);
  1622.    GEN6_USE(p, PIPELINE_SELECT, gen6);
  1623.    GEN6_USE(p, 3DSTATE_BINDING_TABLE_POINTERS, gen6);
  1624.    GEN6_USE(p, 3DSTATE_SAMPLER_STATE_POINTERS, gen6);
  1625.    GEN6_USE(p, 3DSTATE_URB, gen6);
  1626.    GEN6_USE(p, 3DSTATE_VERTEX_BUFFERS, gen6);
  1627.    GEN6_USE(p, 3DSTATE_VERTEX_ELEMENTS, gen6);
  1628.    GEN6_USE(p, 3DSTATE_INDEX_BUFFER, gen6);
  1629.    GEN6_USE(p, 3DSTATE_VF_STATISTICS, gen6);
  1630.    GEN6_USE(p, 3DSTATE_VIEWPORT_STATE_POINTERS, gen6);
  1631.    GEN6_USE(p, 3DSTATE_CC_STATE_POINTERS, gen6);
  1632.    GEN6_USE(p, 3DSTATE_SCISSOR_STATE_POINTERS, gen6);
  1633.    GEN6_USE(p, 3DSTATE_VS, gen6);
  1634.    GEN6_USE(p, 3DSTATE_GS, gen6);
  1635.    GEN6_USE(p, 3DSTATE_CLIP, gen6);
  1636.    GEN6_USE(p, 3DSTATE_SF, gen6);
  1637.    GEN6_USE(p, 3DSTATE_WM, gen6);
  1638.    GEN6_USE(p, 3DSTATE_CONSTANT_VS, gen6);
  1639.    GEN6_USE(p, 3DSTATE_CONSTANT_GS, gen6);
  1640.    GEN6_USE(p, 3DSTATE_CONSTANT_PS, gen6);
  1641.    GEN6_USE(p, 3DSTATE_SAMPLE_MASK, gen6);
  1642.    GEN6_USE(p, 3DSTATE_DRAWING_RECTANGLE, gen6);
  1643.    GEN6_USE(p, 3DSTATE_DEPTH_BUFFER, gen6);
  1644.    GEN6_USE(p, 3DSTATE_POLY_STIPPLE_OFFSET, gen6);
  1645.    GEN6_USE(p, 3DSTATE_POLY_STIPPLE_PATTERN, gen6);
  1646.    GEN6_USE(p, 3DSTATE_LINE_STIPPLE, gen6);
  1647.    GEN6_USE(p, 3DSTATE_AA_LINE_PARAMETERS, gen6);
  1648.    GEN6_USE(p, 3DSTATE_GS_SVB_INDEX, gen6);
  1649.    GEN6_USE(p, 3DSTATE_MULTISAMPLE, gen6);
  1650.    GEN6_USE(p, 3DSTATE_STENCIL_BUFFER, gen6);
  1651.    GEN6_USE(p, 3DSTATE_HIER_DEPTH_BUFFER, gen6);
  1652.    GEN6_USE(p, 3DSTATE_CLEAR_PARAMS, gen6);
  1653.    GEN6_USE(p, PIPE_CONTROL, gen6);
  1654.    GEN6_USE(p, 3DPRIMITIVE, gen6);
  1655.    GEN6_USE(p, INTERFACE_DESCRIPTOR_DATA, gen6);
  1656.    GEN6_USE(p, SF_VIEWPORT, gen6);
  1657.    GEN6_USE(p, CLIP_VIEWPORT, gen6);
  1658.    GEN6_USE(p, CC_VIEWPORT, gen6);
  1659.    GEN6_USE(p, COLOR_CALC_STATE, gen6);
  1660.    GEN6_USE(p, BLEND_STATE, gen6);
  1661.    GEN6_USE(p, DEPTH_STENCIL_STATE, gen6);
  1662.    GEN6_USE(p, SCISSOR_RECT, gen6);
  1663.    GEN6_USE(p, BINDING_TABLE_STATE, gen6);
  1664.    GEN6_USE(p, SURFACE_STATE, gen6);
  1665.    GEN6_USE(p, so_SURFACE_STATE, gen6);
  1666.    GEN6_USE(p, SAMPLER_STATE, gen6);
  1667.    GEN6_USE(p, SAMPLER_BORDER_COLOR_STATE, gen6);
  1668.    GEN6_USE(p, push_constant_buffer, gen6);
  1669. #undef GEN6_USE
  1670. }
  1671.