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  1. /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
  2.  
  3. /*
  4.  * Copyright (C) 2012-2013 Rob Clark <robclark@freedesktop.org>
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice (including the next
  14.  * paragraph) shall be included in all copies or substantial portions of the
  15.  * Software.
  16.  *
  17.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22.  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23.  * SOFTWARE.
  24.  *
  25.  * Authors:
  26.  *    Rob Clark <robclark@freedesktop.org>
  27.  */
  28.  
  29. #include "pipe/p_state.h"
  30. #include "util/u_string.h"
  31. #include "util/u_memory.h"
  32. #include "util/u_prim.h"
  33. #include "util/u_pack_color.h"
  34.  
  35. #include "freedreno_state.h"
  36. #include "freedreno_resource.h"
  37.  
  38. #include "fd2_draw.h"
  39. #include "fd2_context.h"
  40. #include "fd2_emit.h"
  41. #include "fd2_program.h"
  42. #include "fd2_util.h"
  43. #include "fd2_zsa.h"
  44.  
  45.  
  46. static void
  47. emit_cacheflush(struct fd_ringbuffer *ring)
  48. {
  49.         unsigned i;
  50.  
  51.         for (i = 0; i < 12; i++) {
  52.                 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
  53.                 OUT_RING(ring, CACHE_FLUSH);
  54.         }
  55. }
  56.  
  57. static void
  58. emit_vertexbufs(struct fd_context *ctx)
  59. {
  60.         struct fd_vertex_stateobj *vtx = ctx->vtx;
  61.         struct fd_vertexbuf_stateobj *vertexbuf = &ctx->vertexbuf;
  62.         struct fd2_vertex_buf bufs[PIPE_MAX_ATTRIBS];
  63.         unsigned i;
  64.  
  65.         if (!vtx->num_elements)
  66.                 return;
  67.  
  68.         for (i = 0; i < vtx->num_elements; i++) {
  69.                 struct pipe_vertex_element *elem = &vtx->pipe[i];
  70.                 struct pipe_vertex_buffer *vb =
  71.                                 &vertexbuf->vb[elem->vertex_buffer_index];
  72.                 bufs[i].offset = vb->buffer_offset;
  73.                 bufs[i].size = fd_bo_size(fd_resource(vb->buffer)->bo);
  74.                 bufs[i].prsc = vb->buffer;
  75.         }
  76.  
  77.         // NOTE I believe the 0x78 (or 0x9c in solid_vp) relates to the
  78.         // CONST(20,0) (or CONST(26,0) in soliv_vp)
  79.  
  80.         fd2_emit_vertex_bufs(ctx->ring, 0x78, bufs, vtx->num_elements);
  81. }
  82.  
  83. static void
  84. fd2_draw(struct fd_context *ctx, const struct pipe_draw_info *info)
  85. {
  86.         struct fd_ringbuffer *ring = ctx->ring;
  87.  
  88.         if (ctx->dirty & FD_DIRTY_VTXBUF)
  89.                 emit_vertexbufs(ctx);
  90.  
  91.         fd2_emit_state(ctx, ctx->dirty);
  92.  
  93.         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  94.         OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
  95.         OUT_RING(ring, info->start);
  96.  
  97.         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  98.         OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
  99.         OUT_RING(ring, 0x0000003b);
  100.  
  101.         OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1);
  102.         OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE);
  103.  
  104.         OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
  105.         OUT_RING(ring, 0x0000000);
  106.  
  107.         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
  108.         OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
  109.         OUT_RING(ring, info->max_index);        /* VGT_MAX_VTX_INDX */
  110.         OUT_RING(ring, info->min_index);        /* VGT_MIN_VTX_INDX */
  111.  
  112.         fd_draw_emit(ctx, info);
  113.  
  114.         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  115.         OUT_RING(ring, CP_REG(REG_A2XX_UNKNOWN_2010));
  116.         OUT_RING(ring, 0x00000000);
  117.  
  118.         emit_cacheflush(ring);
  119. }
  120.  
  121.  
  122. static uint32_t
  123. pack_rgba(enum pipe_format format, const float *rgba)
  124. {
  125.         union util_color uc;
  126.         util_pack_color(rgba, format, &uc);
  127.         return uc.ui;
  128. }
  129.  
  130. static void
  131. fd2_clear(struct fd_context *ctx, unsigned buffers,
  132.                 const union pipe_color_union *color, double depth, unsigned stencil)
  133. {
  134.         struct fd2_context *fd2_ctx = fd2_context(ctx);
  135.         struct fd_ringbuffer *ring = ctx->ring;
  136.         struct pipe_framebuffer_state *fb = &ctx->framebuffer;
  137.         uint32_t reg, colr = 0;
  138.  
  139.         if ((buffers & PIPE_CLEAR_COLOR) && fb->nr_cbufs)
  140.                 colr  = pack_rgba(fb->cbufs[0]->format, color->f);
  141.  
  142.         /* emit generic state now: */
  143.         fd2_emit_state(ctx, ctx->dirty &
  144.                         (FD_DIRTY_BLEND | FD_DIRTY_VIEWPORT |
  145.                                         FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR));
  146.  
  147.         fd2_emit_vertex_bufs(ring, 0x9c, (struct fd2_vertex_buf[]) {
  148.                         { .prsc = fd2_ctx->solid_vertexbuf, .size = 48 },
  149.                 }, 1);
  150.  
  151.         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  152.         OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
  153.         OUT_RING(ring, 0);
  154.  
  155.         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  156.         OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
  157.         OUT_RING(ring, 0x0000028f);
  158.  
  159.         fd2_program_emit(ring, &ctx->solid_prog);
  160.  
  161.         OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1);
  162.         OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE);
  163.  
  164.         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  165.         OUT_RING(ring, CP_REG(REG_A2XX_CLEAR_COLOR));
  166.         OUT_RING(ring, colr);
  167.  
  168.         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  169.         OUT_RING(ring, CP_REG(REG_A2XX_A220_RB_LRZ_VSC_CONTROL));
  170.         OUT_RING(ring, 0x00000084);
  171.  
  172.         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  173.         OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
  174.         reg = 0;
  175.         if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
  176.                 reg |= A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE;
  177.                 switch (fd_pipe2depth(fb->zsbuf->format)) {
  178.                 case DEPTHX_24_8:
  179.                         if (buffers & PIPE_CLEAR_DEPTH)
  180.                                 reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0xe);
  181.                         if (buffers & PIPE_CLEAR_STENCIL)
  182.                                 reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0x1);
  183.                         break;
  184.                 case DEPTHX_16:
  185.                         if (buffers & PIPE_CLEAR_DEPTH)
  186.                                 reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0xf);
  187.                         break;
  188.                 default:
  189.                         assert(1);
  190.                         break;
  191.                 }
  192.         }
  193.         OUT_RING(ring, reg);
  194.  
  195.         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  196.         OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTH_CLEAR));
  197.         reg = 0;
  198.         if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
  199.                 switch (fd_pipe2depth(fb->zsbuf->format)) {
  200.                 case DEPTHX_24_8:
  201.                         reg = (((uint32_t)(0xffffff * depth)) << 8) |
  202.                                 (stencil & 0xff);
  203.                         break;
  204.                 case DEPTHX_16:
  205.                         reg = (uint32_t)(0xffffffff * depth);
  206.                         break;
  207.                 }
  208.         }
  209.         OUT_RING(ring, reg);
  210.  
  211.         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  212.         OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
  213.         reg = 0;
  214.         if (buffers & PIPE_CLEAR_DEPTH) {
  215.                 reg |= A2XX_RB_DEPTHCONTROL_ZFUNC(FUNC_ALWAYS) |
  216.                                 A2XX_RB_DEPTHCONTROL_Z_ENABLE |
  217.                                 A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE |
  218.                                 A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE;
  219.         }
  220.         if (buffers & PIPE_CLEAR_STENCIL) {
  221.                 reg |= A2XX_RB_DEPTHCONTROL_STENCILFUNC(FUNC_ALWAYS) |
  222.                                 A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE |
  223.                                 A2XX_RB_DEPTHCONTROL_STENCILZPASS(STENCIL_REPLACE);
  224.         }
  225.         OUT_RING(ring, reg);
  226.  
  227.         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
  228.         OUT_RING(ring, CP_REG(REG_A2XX_RB_STENCILREFMASK_BF));
  229.         OUT_RING(ring, 0xff000000 | A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0xff));
  230.         OUT_RING(ring, 0xff000000 | A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
  231.  
  232.         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  233.         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL));
  234.         OUT_RING(ring, A2XX_RB_COLORCONTROL_ALPHA_FUNC(FUNC_ALWAYS) |
  235.                         A2XX_RB_COLORCONTROL_BLEND_DISABLE |
  236.                         A2XX_RB_COLORCONTROL_ROP_CODE(12) |
  237.                         A2XX_RB_COLORCONTROL_DITHER_MODE(DITHER_DISABLE) |
  238.                         A2XX_RB_COLORCONTROL_DITHER_TYPE(DITHER_PIXEL));
  239.  
  240.         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
  241.         OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
  242.         OUT_RING(ring, 0x00000000);        /* PA_CL_CLIP_CNTL */
  243.         OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST |  /* PA_SU_SC_MODE_CNTL */
  244.                         A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
  245.                         A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES));
  246.  
  247.         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  248.         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
  249.         OUT_RING(ring, 0x0000ffff);
  250.  
  251.         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
  252.         OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
  253.         OUT_RING(ring, xy2d(0,0));              /* PA_SC_WINDOW_SCISSOR_TL */
  254.         OUT_RING(ring, xy2d(fb->width,      /* PA_SC_WINDOW_SCISSOR_BR */
  255.                         fb->height));
  256.  
  257.         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  258.         OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK));
  259.         if (buffers & PIPE_CLEAR_COLOR) {
  260.                 OUT_RING(ring, A2XX_RB_COLOR_MASK_WRITE_RED |
  261.                                 A2XX_RB_COLOR_MASK_WRITE_GREEN |
  262.                                 A2XX_RB_COLOR_MASK_WRITE_BLUE |
  263.                                 A2XX_RB_COLOR_MASK_WRITE_ALPHA);
  264.         } else {
  265.                 OUT_RING(ring, 0x0);
  266.         }
  267.  
  268.         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
  269.         OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
  270.         OUT_RING(ring, 3);                 /* VGT_MAX_VTX_INDX */
  271.         OUT_RING(ring, 0);                 /* VGT_MIN_VTX_INDX */
  272.  
  273.         OUT_PKT3(ring, CP_DRAW_INDX, 3);
  274.         OUT_RING(ring, 0x00000000);
  275.         OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_AUTO_INDEX,
  276.                         INDEX_SIZE_IGN, IGNORE_VISIBILITY));
  277.         OUT_RING(ring, 3);                                      /* NumIndices */
  278.  
  279.         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  280.         OUT_RING(ring, CP_REG(REG_A2XX_A220_RB_LRZ_VSC_CONTROL));
  281.         OUT_RING(ring, 0x00000000);
  282.  
  283.         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  284.         OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
  285.         OUT_RING(ring, 0x00000000);
  286. }
  287.  
  288. void
  289. fd2_draw_init(struct pipe_context *pctx)
  290. {
  291.         struct fd_context *ctx = fd_context(pctx);
  292.         ctx->draw = fd2_draw;
  293.         ctx->clear = fd2_clear;
  294. }
  295.