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  1. /**************************************************************************
  2.  *
  3.  * Copyright 2003 VMware, Inc.
  4.  * All Rights Reserved.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the
  8.  * "Software"), to deal in the Software without restriction, including
  9.  * without limitation the rights to use, copy, modify, merge, publish,
  10.  * distribute, sub license, and/or sell copies of the Software, and to
  11.  * permit persons to whom the Software is furnished to do so, subject to
  12.  * the following conditions:
  13.  *
  14.  * The above copyright notice and this permission notice (including the
  15.  * next paragraph) shall be included in all copies or substantial portions
  16.  * of the Software.
  17.  *
  18.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21.  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  22.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25.  *
  26.  **************************************************************************/
  27.  
  28. #define CMD_MI                          (0x0 << 29)
  29. #define CMD_2D                          (0x2 << 29)
  30. #define CMD_3D                          (0x3 << 29)
  31.  
  32. #define MI_NOOP                         (CMD_MI | 0)
  33.  
  34. #define MI_BATCH_BUFFER_END             (CMD_MI | 0xA << 23)
  35.  
  36. #define MI_FLUSH                        (CMD_MI | (4 << 23))
  37. #define FLUSH_MAP_CACHE                         (1 << 0)
  38. #define INHIBIT_FLUSH_RENDER_CACHE              (1 << 2)
  39.  
  40. #define MI_LOAD_REGISTER_IMM            (CMD_MI | (0x22 << 23))
  41.  
  42. #define MI_FLUSH_DW                     (CMD_MI | (0x26 << 23) | 2)
  43.  
  44. #define MI_STORE_REGISTER_MEM           (CMD_MI | (0x24 << 23))
  45. # define MI_STORE_REGISTER_MEM_USE_GGTT         (1 << 22)
  46.  
  47. /* Load a value from memory into a register.  Only available on Gen7+. */
  48. #define GEN7_MI_LOAD_REGISTER_MEM       (CMD_MI | (0x29 << 23))
  49. # define MI_LOAD_REGISTER_MEM_USE_GGTT          (1 << 22)
  50.  
  51. /* Manipulate the predicate bit based on some register values. Only on Gen7+ */
  52. #define GEN7_MI_PREDICATE               (CMD_MI | (0xC << 23))
  53. # define MI_PREDICATE_LOADOP_KEEP               (0 << 6)
  54. # define MI_PREDICATE_LOADOP_LOAD               (2 << 6)
  55. # define MI_PREDICATE_LOADOP_LOADINV            (3 << 6)
  56. # define MI_PREDICATE_COMBINEOP_SET             (0 << 3)
  57. # define MI_PREDICATE_COMBINEOP_AND             (1 << 3)
  58. # define MI_PREDICATE_COMBINEOP_OR              (2 << 3)
  59. # define MI_PREDICATE_COMBINEOP_XOR             (3 << 3)
  60. # define MI_PREDICATE_COMPAREOP_TRUE            (0 << 0)
  61. # define MI_PREDICATE_COMPAREOP_FALSE           (1 << 0)
  62. # define MI_PREDICATE_COMPAREOP_SRCS_EQUAL      (2 << 0)
  63. # define MI_PREDICATE_COMPAREOP_DELTAS_EQUAL    (3 << 0)
  64.  
  65. /** @{
  66.  *
  67.  * PIPE_CONTROL operation, a combination MI_FLUSH and register write with
  68.  * additional flushing control.
  69.  */
  70. #define _3DSTATE_PIPE_CONTROL           (CMD_3D | (3 << 27) | (2 << 24))
  71. #define PIPE_CONTROL_CS_STALL           (1 << 20)
  72. #define PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET        (1 << 19)
  73. #define PIPE_CONTROL_TLB_INVALIDATE     (1 << 18)
  74. #define PIPE_CONTROL_SYNC_GFDT          (1 << 17)
  75. #define PIPE_CONTROL_MEDIA_STATE_CLEAR  (1 << 16)
  76. #define PIPE_CONTROL_NO_WRITE           (0 << 14)
  77. #define PIPE_CONTROL_WRITE_IMMEDIATE    (1 << 14)
  78. #define PIPE_CONTROL_WRITE_DEPTH_COUNT  (2 << 14)
  79. #define PIPE_CONTROL_WRITE_TIMESTAMP    (3 << 14)
  80. #define PIPE_CONTROL_DEPTH_STALL        (1 << 13)
  81. #define PIPE_CONTROL_RENDER_TARGET_FLUSH (1 << 12)
  82. #define PIPE_CONTROL_INSTRUCTION_INVALIDATE (1 << 11)
  83. #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE   (1 << 10) /* GM45+ only */
  84. #define PIPE_CONTROL_ISP_DIS            (1 << 9)
  85. #define PIPE_CONTROL_INTERRUPT_ENABLE   (1 << 8)
  86. #define PIPE_CONTROL_FLUSH_ENABLE       (1 << 7) /* Gen7+ only */
  87. /* GT */
  88. #define PIPE_CONTROL_DATA_CACHE_INVALIDATE      (1 << 5)
  89. #define PIPE_CONTROL_VF_CACHE_INVALIDATE        (1 << 4)
  90. #define PIPE_CONTROL_CONST_CACHE_INVALIDATE     (1 << 3)
  91. #define PIPE_CONTROL_STATE_CACHE_INVALIDATE     (1 << 2)
  92. #define PIPE_CONTROL_STALL_AT_SCOREBOARD        (1 << 1)
  93. #define PIPE_CONTROL_DEPTH_CACHE_FLUSH          (1 << 0)
  94. #define PIPE_CONTROL_PPGTT_WRITE        (0 << 2)
  95. #define PIPE_CONTROL_GLOBAL_GTT_WRITE   (1 << 2)
  96.  
  97. /** @} */
  98.  
  99. #define XY_SETUP_BLT_CMD                (CMD_2D | (0x01 << 22))
  100.  
  101. #define XY_COLOR_BLT_CMD                (CMD_2D | (0x50 << 22))
  102.  
  103. #define XY_SRC_COPY_BLT_CMD             (CMD_2D | (0x53 << 22))
  104.  
  105. #define XY_TEXT_IMMEDIATE_BLIT_CMD      (CMD_2D | (0x31 << 22))
  106. # define XY_TEXT_BYTE_PACKED            (1 << 16)
  107.  
  108. /* BR00 */
  109. #define XY_BLT_WRITE_ALPHA      (1 << 21)
  110. #define XY_BLT_WRITE_RGB        (1 << 20)
  111. #define XY_SRC_TILED            (1 << 15)
  112. #define XY_DST_TILED            (1 << 11)
  113.  
  114. /* BR13 */
  115. #define BR13_8                  (0x0 << 24)
  116. #define BR13_565                (0x1 << 24)
  117. #define BR13_8888               (0x3 << 24)
  118.  
  119. /* Pipeline Statistics Counter Registers */
  120. #define IA_VERTICES_COUNT               0x2310
  121. #define IA_PRIMITIVES_COUNT             0x2318
  122. #define VS_INVOCATION_COUNT             0x2320
  123. #define HS_INVOCATION_COUNT             0x2300
  124. #define DS_INVOCATION_COUNT             0x2308
  125. #define GS_INVOCATION_COUNT             0x2328
  126. #define GS_PRIMITIVES_COUNT             0x2330
  127. #define CL_INVOCATION_COUNT             0x2338
  128. #define CL_PRIMITIVES_COUNT             0x2340
  129. #define PS_INVOCATION_COUNT             0x2348
  130. #define CS_INVOCATION_COUNT             0x2290
  131. #define PS_DEPTH_COUNT                  0x2350
  132.  
  133. #define GEN6_SO_PRIM_STORAGE_NEEDED     0x2280
  134. #define GEN7_SO_PRIM_STORAGE_NEEDED(n)  (0x5240 + (n) * 8)
  135.  
  136. #define GEN6_SO_NUM_PRIMS_WRITTEN       0x2288
  137. #define GEN7_SO_NUM_PRIMS_WRITTEN(n)    (0x5200 + (n) * 8)
  138.  
  139. #define GEN7_SO_WRITE_OFFSET(n)         (0x5280 + (n) * 4)
  140.  
  141. #define TIMESTAMP                       0x2358
  142.  
  143. #define BCS_SWCTRL                      0x22200
  144. # define BCS_SWCTRL_SRC_Y               (1 << 0)
  145. # define BCS_SWCTRL_DST_Y               (1 << 1)
  146.  
  147. #define OACONTROL                       0x2360
  148. # define OACONTROL_COUNTER_SELECT_SHIFT  2
  149. # define OACONTROL_ENABLE_COUNTERS       (1 << 0)
  150.  
  151. /* Auto-Draw / Indirect Registers */
  152. #define GEN7_3DPRIM_END_OFFSET          0x2420
  153. #define GEN7_3DPRIM_START_VERTEX        0x2430
  154. #define GEN7_3DPRIM_VERTEX_COUNT        0x2434
  155. #define GEN7_3DPRIM_INSTANCE_COUNT      0x2438
  156. #define GEN7_3DPRIM_START_INSTANCE      0x243C
  157. #define GEN7_3DPRIM_BASE_VERTEX         0x2440
  158.  
  159. #define GEN7_CACHE_MODE_1               0x7004
  160. # define GEN8_HIZ_NP_PMA_FIX_ENABLE        (1 << 11)
  161. # define GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE (1 << 13)
  162. # define GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC (1 << 1)
  163. # define GEN8_HIZ_PMA_MASK_BITS \
  164.    ((GEN8_HIZ_NP_PMA_FIX_ENABLE | GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE) << 16)
  165.  
  166. /* Predicate registers */
  167. #define MI_PREDICATE_SRC0               0x2400
  168. #define MI_PREDICATE_SRC1               0x2408
  169. #define MI_PREDICATE_DATA               0x2410
  170. #define MI_PREDICATE_RESULT             0x2418
  171. #define MI_PREDICATE_RESULT_1           0x241C
  172. #define MI_PREDICATE_RESULT_2           0x2214
  173.