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  1. /**************************************************************************
  2.  *
  3.  * Copyright 2003 VMware, Inc.
  4.  * All Rights Reserved.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the
  8.  * "Software"), to deal in the Software without restriction, including
  9.  * without limitation the rights to use, copy, modify, merge, publish,
  10.  * distribute, sub license, and/or sell copies of the Software, and to
  11.  * permit persons to whom the Software is furnished to do so, subject to
  12.  * the following conditions:
  13.  *
  14.  * The above copyright notice and this permission notice (including the
  15.  * next paragraph) shall be included in all copies or substantial portions
  16.  * of the Software.
  17.  *
  18.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21.  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  22.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25.  *
  26.  **************************************************************************/
  27.  
  28. #include "main/version.h"
  29.  
  30. #include "brw_context.h"
  31. #include "intel_batchbuffer.h"
  32. #include "intel_reg.h"
  33. #include "utils.h"
  34.  
  35. /**
  36.  * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
  37.  *
  38.  * Some combinations of hardware and kernel versions allow this feature,
  39.  * while others don't.  Instead of trying to enumerate every case, just
  40.  * try and write a register and see if works.
  41.  */
  42. static bool
  43. can_do_pipelined_register_writes(struct brw_context *brw)
  44. {
  45.    /* Supposedly, Broadwell just works. */
  46.    if (brw->gen >= 8)
  47.       return true;
  48.  
  49.    static int result = -1;
  50.    if (result != -1)
  51.       return result;
  52.  
  53.    /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
  54.     * statistics registers), and we already reset it to zero before using it.
  55.     */
  56.    const int reg = GEN7_SO_WRITE_OFFSET(0);
  57.    const int expected_value = 0x1337d0d0;
  58.    const int offset = 100;
  59.  
  60.    /* The register we picked only exists on Gen7+. */
  61.    assert(brw->gen == 7);
  62.  
  63.    uint32_t *data;
  64.    /* Set a value in a BO to a known quantity.  The workaround BO already
  65.     * exists and doesn't contain anything important, so we may as well use it.
  66.     */
  67.    drm_intel_bo_map(brw->batch.workaround_bo, true);
  68.    data = brw->batch.workaround_bo->virtual;
  69.    data[offset] = 0xffffffff;
  70.    drm_intel_bo_unmap(brw->batch.workaround_bo);
  71.  
  72.    /* Write the register. */
  73.    BEGIN_BATCH(3);
  74.    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
  75.    OUT_BATCH(reg);
  76.    OUT_BATCH(expected_value);
  77.    ADVANCE_BATCH();
  78.  
  79.    intel_batchbuffer_emit_mi_flush(brw);
  80.  
  81.    /* Save the register's value back to the buffer. */
  82.    BEGIN_BATCH(3);
  83.    OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
  84.    OUT_BATCH(reg);
  85.    OUT_RELOC(brw->batch.workaround_bo,
  86.              I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
  87.              offset * sizeof(uint32_t));
  88.    ADVANCE_BATCH();
  89.  
  90.    intel_batchbuffer_flush(brw);
  91.  
  92.    /* Check whether the value got written. */
  93.    drm_intel_bo_map(brw->batch.workaround_bo, false);
  94.    data = brw->batch.workaround_bo->virtual;
  95.    bool success = data[offset] == expected_value;
  96.    drm_intel_bo_unmap(brw->batch.workaround_bo);
  97.  
  98.    result = success;
  99.  
  100.    return success;
  101. }
  102.  
  103. static bool
  104. can_write_oacontrol(struct brw_context *brw)
  105. {
  106.    if (brw->gen < 6 || brw->gen >= 8)
  107.       return false;
  108.  
  109.    static int result = -1;
  110.    if (result != -1)
  111.       return result;
  112.  
  113.    /* Set "Select Context ID" to a particular address (which is likely not a
  114.     * context), but leave all counting disabled.  This should be harmless.
  115.     */
  116.    const int expected_value = 0x31337000;
  117.    const int offset = 110;
  118.  
  119.    uint32_t *data;
  120.    /* Set a value in a BO to a known quantity.  The workaround BO already
  121.     * exists and doesn't contain anything important, so we may as well use it.
  122.     */
  123.    drm_intel_bo_map(brw->batch.workaround_bo, true);
  124.    data = brw->batch.workaround_bo->virtual;
  125.    data[offset] = 0xffffffff;
  126.    drm_intel_bo_unmap(brw->batch.workaround_bo);
  127.  
  128.    /* Write OACONTROL. */
  129.    BEGIN_BATCH(3);
  130.    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
  131.    OUT_BATCH(OACONTROL);
  132.    OUT_BATCH(expected_value);
  133.    ADVANCE_BATCH();
  134.  
  135.    intel_batchbuffer_emit_mi_flush(brw);
  136.  
  137.    /* Save the register's value back to the buffer. */
  138.    BEGIN_BATCH(3);
  139.    OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
  140.    OUT_BATCH(OACONTROL);
  141.    OUT_RELOC(brw->batch.workaround_bo,
  142.              I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
  143.              offset * sizeof(uint32_t));
  144.    ADVANCE_BATCH();
  145.  
  146.    intel_batchbuffer_emit_mi_flush(brw);
  147.  
  148.    /* Set OACONTROL back to zero (everything off). */
  149.    BEGIN_BATCH(3);
  150.    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
  151.    OUT_BATCH(OACONTROL);
  152.    OUT_BATCH(0);
  153.    ADVANCE_BATCH();
  154.  
  155.    intel_batchbuffer_flush(brw);
  156.  
  157.    /* Check whether the value got written. */
  158.    drm_intel_bo_map(brw->batch.workaround_bo, false);
  159.    data = brw->batch.workaround_bo->virtual;
  160.    bool success = data[offset] == expected_value;
  161.    drm_intel_bo_unmap(brw->batch.workaround_bo);
  162.  
  163.    result = success;
  164.  
  165.    return success;
  166. }
  167.  
  168. /**
  169.  * Initializes potential list of extensions if ctx == NULL, or actually enables
  170.  * extensions for a context.
  171.  */
  172. void
  173. intelInitExtensions(struct gl_context *ctx)
  174. {
  175.    struct brw_context *brw = brw_context(ctx);
  176.  
  177.    assert(brw->gen >= 4);
  178.  
  179.    ctx->Extensions.ARB_buffer_storage = true;
  180.    ctx->Extensions.ARB_clear_texture = true;
  181.    ctx->Extensions.ARB_clip_control = true;
  182.    ctx->Extensions.ARB_copy_image = true;
  183.    ctx->Extensions.ARB_depth_buffer_float = true;
  184.    ctx->Extensions.ARB_depth_clamp = true;
  185.    ctx->Extensions.ARB_depth_texture = true;
  186.    ctx->Extensions.ARB_direct_state_access = true;
  187.    ctx->Extensions.ARB_draw_elements_base_vertex = true;
  188.    ctx->Extensions.ARB_draw_instanced = true;
  189.    ctx->Extensions.ARB_ES2_compatibility = true;
  190.    ctx->Extensions.ARB_explicit_attrib_location = true;
  191.    ctx->Extensions.ARB_explicit_uniform_location = true;
  192.    ctx->Extensions.ARB_fragment_coord_conventions = true;
  193.    ctx->Extensions.ARB_fragment_program = true;
  194.    ctx->Extensions.ARB_fragment_program_shadow = true;
  195.    ctx->Extensions.ARB_fragment_shader = true;
  196.    ctx->Extensions.ARB_framebuffer_object = true;
  197.    ctx->Extensions.ARB_half_float_vertex = true;
  198.    ctx->Extensions.ARB_instanced_arrays = true;
  199.    ctx->Extensions.ARB_internalformat_query = true;
  200.    ctx->Extensions.ARB_map_buffer_range = true;
  201.    ctx->Extensions.ARB_occlusion_query = true;
  202.    ctx->Extensions.ARB_occlusion_query2 = true;
  203.    ctx->Extensions.ARB_pipeline_statistics_query = true;
  204.    ctx->Extensions.ARB_point_sprite = true;
  205.    ctx->Extensions.ARB_seamless_cube_map = true;
  206.    ctx->Extensions.ARB_shader_bit_encoding = true;
  207.    ctx->Extensions.ARB_shader_texture_lod = true;
  208.    ctx->Extensions.ARB_shadow = true;
  209.    ctx->Extensions.ARB_sync = true;
  210.    ctx->Extensions.ARB_texture_border_clamp = true;
  211.    ctx->Extensions.ARB_texture_compression_rgtc = true;
  212.    ctx->Extensions.ARB_texture_cube_map = true;
  213.    ctx->Extensions.ARB_texture_env_combine = true;
  214.    ctx->Extensions.ARB_texture_env_crossbar = true;
  215.    ctx->Extensions.ARB_texture_env_dot3 = true;
  216.    ctx->Extensions.ARB_texture_float = true;
  217.    ctx->Extensions.ARB_texture_mirror_clamp_to_edge = true;
  218.    ctx->Extensions.ARB_texture_non_power_of_two = true;
  219.    ctx->Extensions.ARB_texture_rg = true;
  220.    ctx->Extensions.ARB_texture_rgb10_a2ui = true;
  221.    ctx->Extensions.ARB_vertex_program = true;
  222.    ctx->Extensions.ARB_vertex_shader = true;
  223.    ctx->Extensions.ARB_vertex_type_2_10_10_10_rev = true;
  224.    ctx->Extensions.ARB_vertex_type_10f_11f_11f_rev = true;
  225.    ctx->Extensions.EXT_blend_color = true;
  226.    ctx->Extensions.EXT_blend_equation_separate = true;
  227.    ctx->Extensions.EXT_blend_func_separate = true;
  228.    ctx->Extensions.EXT_blend_minmax = true;
  229.    ctx->Extensions.EXT_draw_buffers2 = true;
  230.    ctx->Extensions.EXT_framebuffer_sRGB = true;
  231.    ctx->Extensions.EXT_gpu_program_parameters = true;
  232.    ctx->Extensions.EXT_packed_float = true;
  233.    ctx->Extensions.EXT_pixel_buffer_object = true;
  234.    ctx->Extensions.EXT_point_parameters = true;
  235.    ctx->Extensions.EXT_provoking_vertex = true;
  236.    ctx->Extensions.EXT_stencil_two_side = true;
  237.    ctx->Extensions.EXT_texture_array = true;
  238.    ctx->Extensions.EXT_texture_env_dot3 = true;
  239.    ctx->Extensions.EXT_texture_filter_anisotropic = true;
  240.    ctx->Extensions.EXT_texture_integer = true;
  241.    ctx->Extensions.EXT_texture_shared_exponent = true;
  242.    ctx->Extensions.EXT_texture_snorm = true;
  243.    ctx->Extensions.EXT_texture_sRGB = true;
  244.    ctx->Extensions.EXT_texture_sRGB_decode = true;
  245.    ctx->Extensions.EXT_texture_swizzle = true;
  246.    ctx->Extensions.EXT_vertex_array_bgra = true;
  247.    ctx->Extensions.AMD_seamless_cubemap_per_texture = true;
  248.    ctx->Extensions.APPLE_object_purgeable = true;
  249.    ctx->Extensions.ATI_separate_stencil = true;
  250.    ctx->Extensions.ATI_texture_env_combine3 = true;
  251.    ctx->Extensions.MESA_pack_invert = true;
  252.    ctx->Extensions.NV_conditional_render = true;
  253.    ctx->Extensions.NV_primitive_restart = true;
  254.    ctx->Extensions.NV_texture_env_combine4 = true;
  255.    ctx->Extensions.NV_texture_rectangle = true;
  256.    ctx->Extensions.TDFX_texture_compression_FXT1 = true;
  257.    ctx->Extensions.OES_compressed_ETC1_RGB8_texture = true;
  258.    ctx->Extensions.OES_draw_texture = true;
  259.    ctx->Extensions.OES_EGL_image = true;
  260.    ctx->Extensions.OES_EGL_image_external = true;
  261.    ctx->Extensions.OES_standard_derivatives = true;
  262.    ctx->Extensions.OES_texture_float = true;
  263.    ctx->Extensions.OES_texture_float_linear = true;
  264.    ctx->Extensions.OES_texture_half_float = true;
  265.    ctx->Extensions.OES_texture_half_float_linear = true;
  266.  
  267.    if (brw->gen >= 6)
  268.       ctx->Const.GLSLVersion = 330;
  269.    else
  270.       ctx->Const.GLSLVersion = 120;
  271.    _mesa_override_glsl_version(&ctx->Const);
  272.  
  273.    if (brw->gen >= 5) {
  274.       ctx->Extensions.ARB_texture_query_levels = ctx->Const.GLSLVersion >= 130;
  275.       ctx->Extensions.ARB_texture_query_lod = true;
  276.       ctx->Extensions.EXT_shader_integer_mix = ctx->Const.GLSLVersion >= 130;
  277.       ctx->Extensions.EXT_timer_query = true;
  278.  
  279.       if (brw->gen == 5 || can_write_oacontrol(brw)) {
  280.          ctx->Extensions.AMD_performance_monitor = true;
  281.          ctx->Extensions.INTEL_performance_query = true;
  282.       }
  283.    }
  284.  
  285.    if (brw->gen >= 6) {
  286.       uint64_t dummy;
  287.  
  288.       ctx->Extensions.ARB_blend_func_extended =
  289.          !driQueryOptionb(&brw->optionCache, "disable_blend_func_extended");
  290.       ctx->Extensions.ARB_conditional_render_inverted = true;
  291.       ctx->Extensions.ARB_draw_buffers_blend = true;
  292.       ctx->Extensions.ARB_ES3_compatibility = true;
  293.       ctx->Extensions.ARB_sample_shading = true;
  294.       ctx->Extensions.ARB_shading_language_420pack = true;
  295.       ctx->Extensions.ARB_shading_language_packing = true;
  296.       ctx->Extensions.ARB_texture_buffer_object = true;
  297.       ctx->Extensions.ARB_texture_buffer_object_rgb32 = true;
  298.       ctx->Extensions.ARB_texture_buffer_range = true;
  299.       ctx->Extensions.ARB_texture_cube_map_array = true;
  300.       ctx->Extensions.ARB_texture_gather = true;
  301.       ctx->Extensions.ARB_texture_multisample = true;
  302.       ctx->Extensions.ARB_uniform_buffer_object = true;
  303.  
  304.       ctx->Extensions.AMD_vertex_shader_layer = true;
  305.       ctx->Extensions.EXT_framebuffer_multisample = true;
  306.       ctx->Extensions.EXT_framebuffer_multisample_blit_scaled = true;
  307.       ctx->Extensions.EXT_polygon_offset_clamp = true;
  308.       ctx->Extensions.EXT_transform_feedback = true;
  309.       ctx->Extensions.OES_depth_texture_cube_map = true;
  310.  
  311.       /* Test if the kernel has the ioctl. */
  312.       if (drm_intel_reg_read(brw->bufmgr, TIMESTAMP, &dummy) == 0)
  313.          ctx->Extensions.ARB_timer_query = true;
  314.  
  315.       /* Only enable this in core profile because other parts of Mesa behave
  316.        * slightly differently when the extension is enabled.
  317.        */
  318.       if (ctx->API == API_OPENGL_CORE) {
  319.          ctx->Extensions.ARB_viewport_array = true;
  320.          ctx->Extensions.AMD_vertex_shader_viewport_index = true;
  321.       }
  322.    }
  323.  
  324.    brw->predicate.supported = false;
  325.  
  326.    if (brw->gen >= 7) {
  327.       ctx->Extensions.ARB_conservative_depth = true;
  328.       ctx->Extensions.ARB_derivative_control = true;
  329.       ctx->Extensions.ARB_gpu_shader5 = true;
  330.       ctx->Extensions.ARB_shader_atomic_counters = true;
  331.       ctx->Extensions.ARB_texture_compression_bptc = true;
  332.       ctx->Extensions.ARB_texture_view = true;
  333.  
  334.       if (can_do_pipelined_register_writes(brw)) {
  335.          ctx->Extensions.ARB_draw_indirect = true;
  336.          ctx->Extensions.ARB_transform_feedback2 = true;
  337.          ctx->Extensions.ARB_transform_feedback3 = true;
  338.          ctx->Extensions.ARB_transform_feedback_instanced = true;
  339.  
  340.          if (brw->intelScreen->cmd_parser_version >= 2)
  341.             brw->predicate.supported = true;
  342.       }
  343.  
  344.       /* Only enable this in core profile because other parts of Mesa behave
  345.        * slightly differently when the extension is enabled.
  346.        */
  347.       if (ctx->API == API_OPENGL_CORE) {
  348.          ctx->Extensions.ARB_viewport_array = true;
  349.          ctx->Extensions.AMD_vertex_shader_viewport_index = true;
  350.       }
  351.    }
  352.  
  353.    if (brw->gen >= 8) {
  354.       ctx->Extensions.ARB_stencil_texturing = true;
  355.    }
  356.  
  357.    if (ctx->API == API_OPENGL_CORE)
  358.       ctx->Extensions.ARB_base_instance = true;
  359.    if (ctx->API != API_OPENGL_CORE)
  360.       ctx->Extensions.ARB_color_buffer_float = true;
  361.  
  362.    if (ctx->Mesa_DXTn || driQueryOptionb(&brw->optionCache, "force_s3tc_enable"))
  363.       ctx->Extensions.EXT_texture_compression_s3tc = true;
  364.  
  365.    ctx->Extensions.ANGLE_texture_compression_dxt = true;
  366. }
  367.