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  1. /*
  2.  * Copyright © 2012 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21.  * IN THE SOFTWARE.
  22.  */
  23.  
  24. #include "main/blend.h"
  25. #include "main/mtypes.h"
  26. #include "main/samplerobj.h"
  27. #include "main/texformat.h"
  28. #include "main/teximage.h"
  29. #include "program/prog_parameter.h"
  30.  
  31. #include "intel_mipmap_tree.h"
  32. #include "intel_batchbuffer.h"
  33. #include "intel_tex.h"
  34. #include "intel_fbo.h"
  35. #include "intel_buffer_objects.h"
  36.  
  37. #include "brw_context.h"
  38. #include "brw_state.h"
  39. #include "brw_defines.h"
  40. #include "brw_wm.h"
  41.  
  42. /**
  43.  * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
  44.  * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED).  The mappings are
  45.  *
  46.  * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
  47.  *         0          1          2          3             4            5
  48.  *         4          5          6          7             0            1
  49.  *   SCS_RED, SCS_GREEN,  SCS_BLUE, SCS_ALPHA,     SCS_ZERO,     SCS_ONE
  50.  *
  51.  * which is simply adding 4 then modding by 8 (or anding with 7).
  52.  */
  53. static unsigned
  54. swizzle_to_scs(unsigned swizzle)
  55. {
  56.    return (swizzle + 4) & 7;
  57. }
  58.  
  59. static uint32_t
  60. surface_tiling_mode(uint32_t tiling)
  61. {
  62.    switch (tiling) {
  63.    case I915_TILING_X:
  64.       return GEN8_SURFACE_TILING_X;
  65.    case I915_TILING_Y:
  66.       return GEN8_SURFACE_TILING_Y;
  67.    default:
  68.       return GEN8_SURFACE_TILING_NONE;
  69.    }
  70. }
  71.  
  72. static unsigned
  73. vertical_alignment(const struct intel_mipmap_tree *mt)
  74. {
  75.    switch (mt->align_h) {
  76.    case 4:
  77.       return GEN8_SURFACE_VALIGN_4;
  78.    case 8:
  79.       return GEN8_SURFACE_VALIGN_8;
  80.    case 16:
  81.       return GEN8_SURFACE_VALIGN_16;
  82.    default:
  83.       unreachable("Unsupported vertical surface alignment.");
  84.    }
  85. }
  86.  
  87. static unsigned
  88. horizontal_alignment(const struct intel_mipmap_tree *mt)
  89. {
  90.    switch (mt->align_w) {
  91.    case 4:
  92.       return GEN8_SURFACE_HALIGN_4;
  93.    case 8:
  94.       return GEN8_SURFACE_HALIGN_8;
  95.    case 16:
  96.       return GEN8_SURFACE_HALIGN_16;
  97.    default:
  98.       unreachable("Unsupported horizontal surface alignment.");
  99.    }
  100. }
  101.  
  102. static uint32_t *
  103. allocate_surface_state(struct brw_context *brw, uint32_t *out_offset, int index)
  104. {
  105.    int dwords = brw->gen >= 9 ? 16 : 13;
  106.    uint32_t *surf = __brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
  107.                                       dwords * 4, 64, index, out_offset);
  108.    memset(surf, 0, dwords * 4);
  109.    return surf;
  110. }
  111.  
  112. static void
  113. gen8_emit_buffer_surface_state(struct brw_context *brw,
  114.                                uint32_t *out_offset,
  115.                                drm_intel_bo *bo,
  116.                                unsigned buffer_offset,
  117.                                unsigned surface_format,
  118.                                unsigned buffer_size,
  119.                                unsigned pitch,
  120.                                bool rw)
  121. {
  122.    const unsigned mocs = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
  123.    uint32_t *surf = allocate_surface_state(brw, out_offset, -1);
  124.  
  125.    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
  126.              surface_format << BRW_SURFACE_FORMAT_SHIFT |
  127.              BRW_SURFACE_RC_READ_WRITE;
  128.    surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS);
  129.  
  130.    surf[2] = SET_FIELD((buffer_size - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
  131.              SET_FIELD(((buffer_size - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
  132.    if (surface_format == BRW_SURFACEFORMAT_RAW)
  133.       surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3ff, BRW_SURFACE_DEPTH);
  134.    else
  135.       surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH);
  136.    surf[3] |= (pitch - 1);
  137.    surf[7] = SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
  138.              SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
  139.              SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
  140.              SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
  141.    /* reloc */
  142.    *((uint64_t *) &surf[8]) = (bo ? bo->offset64 : 0) + buffer_offset;
  143.  
  144.    /* Emit relocation to surface contents. */
  145.    if (bo) {
  146.       drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 8 * 4,
  147.                               bo, buffer_offset, I915_GEM_DOMAIN_SAMPLER,
  148.                               rw ? I915_GEM_DOMAIN_SAMPLER : 0);
  149.    }
  150. }
  151.  
  152. static void
  153. gen8_emit_texture_surface_state(struct brw_context *brw,
  154.                                 struct intel_mipmap_tree *mt,
  155.                                 GLenum target,
  156.                                 unsigned min_layer, unsigned max_layer,
  157.                                 unsigned min_level, unsigned max_level,
  158.                                 unsigned format,
  159.                                 unsigned swizzle,
  160.                                 uint32_t *surf_offset,
  161.                                 bool rw, bool for_gather)
  162. {
  163.    const unsigned depth = max_layer - min_layer;
  164.    struct intel_mipmap_tree *aux_mt = NULL;
  165.    uint32_t aux_mode = 0;
  166.    uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
  167.    int surf_index = surf_offset - &brw->wm.base.surf_offset[0];
  168.    unsigned tiling_mode, pitch;
  169.  
  170.    if (mt->format == MESA_FORMAT_S_UINT8) {
  171.       tiling_mode = GEN8_SURFACE_TILING_W;
  172.       pitch = 2 * mt->pitch;
  173.    } else {
  174.       tiling_mode = surface_tiling_mode(mt->tiling);
  175.       pitch = mt->pitch;
  176.    }
  177.  
  178.    if (mt->mcs_mt) {
  179.       aux_mt = mt->mcs_mt;
  180.       aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
  181.    }
  182.  
  183.    uint32_t *surf = allocate_surface_state(brw, surf_offset, surf_index);
  184.  
  185.    surf[0] = translate_tex_target(target) << BRW_SURFACE_TYPE_SHIFT |
  186.              format << BRW_SURFACE_FORMAT_SHIFT |
  187.              vertical_alignment(mt) |
  188.              horizontal_alignment(mt) |
  189.              tiling_mode;
  190.  
  191.    if (target == GL_TEXTURE_CUBE_MAP ||
  192.        target == GL_TEXTURE_CUBE_MAP_ARRAY) {
  193.       surf[0] |= BRW_SURFACE_CUBEFACE_ENABLES;
  194.    }
  195.  
  196.    if (_mesa_is_array_texture(target) || target == GL_TEXTURE_CUBE_MAP)
  197.       surf[0] |= GEN8_SURFACE_IS_ARRAY;
  198.  
  199.    surf[1] = SET_FIELD(mocs_wb, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
  200.  
  201.    surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
  202.              SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
  203.  
  204.    surf[3] = SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) | (pitch - 1);
  205.  
  206.    surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout) |
  207.              SET_FIELD(min_layer, GEN7_SURFACE_MIN_ARRAY_ELEMENT) |
  208.              SET_FIELD(depth - 1, GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT);
  209.  
  210.    surf[5] = SET_FIELD(min_level - mt->first_level, GEN7_SURFACE_MIN_LOD) |
  211.              (max_level - min_level - 1); /* mip count */
  212.  
  213.    if (aux_mt) {
  214.       surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
  215.                 SET_FIELD((aux_mt->pitch / 128) - 1, GEN8_SURFACE_AUX_PITCH) |
  216.                 aux_mode;
  217.    } else {
  218.       surf[6] = 0;
  219.    }
  220.  
  221.    surf[7] = mt->fast_clear_color_value |
  222.       SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 0)), GEN7_SURFACE_SCS_R) |
  223.       SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 1)), GEN7_SURFACE_SCS_G) |
  224.       SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2)), GEN7_SURFACE_SCS_B) |
  225.       SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 3)), GEN7_SURFACE_SCS_A);
  226.  
  227.    *((uint64_t *) &surf[8]) = mt->bo->offset64 + mt->offset; /* reloc */
  228.  
  229.    if (aux_mt) {
  230.       *((uint64_t *) &surf[10]) = aux_mt->bo->offset64;
  231.       drm_intel_bo_emit_reloc(brw->batch.bo, *surf_offset + 10 * 4,
  232.                               aux_mt->bo, 0,
  233.                               I915_GEM_DOMAIN_SAMPLER,
  234.                               (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
  235.    } else {
  236.       surf[10] = 0;
  237.       surf[11] = 0;
  238.    }
  239.    surf[12] = 0;
  240.  
  241.    /* Emit relocation to surface contents */
  242.    drm_intel_bo_emit_reloc(brw->batch.bo,
  243.                            *surf_offset + 8 * 4,
  244.                            mt->bo,
  245.                            mt->offset,
  246.                            I915_GEM_DOMAIN_SAMPLER,
  247.                            (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
  248. }
  249.  
  250. static void
  251. gen8_update_texture_surface(struct gl_context *ctx,
  252.                             unsigned unit,
  253.                             uint32_t *surf_offset,
  254.                             bool for_gather)
  255. {
  256.    struct brw_context *brw = brw_context(ctx);
  257.    struct gl_texture_object *obj = ctx->Texture.Unit[unit]._Current;
  258.  
  259.    if (obj->Target == GL_TEXTURE_BUFFER) {
  260.       brw_update_buffer_texture_surface(ctx, unit, surf_offset);
  261.  
  262.    } else {
  263.       struct gl_texture_image *firstImage = obj->Image[0][obj->BaseLevel];
  264.       struct intel_texture_object *intel_obj = intel_texture_object(obj);
  265.       struct intel_mipmap_tree *mt = intel_obj->mt;
  266.       struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
  267.       /* If this is a view with restricted NumLayers, then our effective depth
  268.        * is not just the miptree depth.
  269.        */
  270.       const unsigned depth = (obj->Immutable && obj->Target != GL_TEXTURE_3D ?
  271.                               obj->NumLayers : mt->logical_depth0);
  272.  
  273.       /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
  274.        * texturing functions that return a float, as our code generation always
  275.        * selects the .x channel (which would always be 0).
  276.        */
  277.       const bool alpha_depth = obj->DepthMode == GL_ALPHA &&
  278.          (firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
  279.           firstImage->_BaseFormat == GL_DEPTH_STENCIL);
  280.       const unsigned swizzle = (unlikely(alpha_depth) ? SWIZZLE_XYZW :
  281.                                 brw_get_texture_swizzle(&brw->ctx, obj));
  282.  
  283.       unsigned format = translate_tex_format(brw, intel_obj->_Format,
  284.                                              sampler->sRGBDecode);
  285.       if (obj->StencilSampling && firstImage->_BaseFormat == GL_DEPTH_STENCIL) {
  286.          mt = mt->stencil_mt;
  287.          format = BRW_SURFACEFORMAT_R8_UINT;
  288.       }
  289.  
  290.       gen8_emit_texture_surface_state(brw, mt, obj->Target,
  291.                                       obj->MinLayer, obj->MinLayer + depth,
  292.                                       obj->MinLevel + obj->BaseLevel,
  293.                                       obj->MinLevel + intel_obj->_MaxLevel + 1,
  294.                                       format, swizzle, surf_offset,
  295.                                       false, for_gather);
  296.    }
  297. }
  298.  
  299. /**
  300.  * Creates a null surface.
  301.  *
  302.  * This is used when the shader doesn't write to any color output.  An FB
  303.  * write to target 0 will still be emitted, because that's how the thread is
  304.  * terminated (and computed depth is returned), so we need to have the
  305.  * hardware discard the target 0 color output..
  306.  */
  307. static void
  308. gen8_emit_null_surface_state(struct brw_context *brw,
  309.                              unsigned width,
  310.                              unsigned height,
  311.                              unsigned samples,
  312.                              uint32_t *out_offset)
  313. {
  314.    uint32_t *surf = allocate_surface_state(brw, out_offset, -1);
  315.  
  316.    surf[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
  317.              BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT |
  318.              GEN8_SURFACE_TILING_Y;
  319.    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
  320.              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
  321. }
  322.  
  323. /**
  324.  * Sets up a surface state structure to point at the given region.
  325.  * While it is only used for the front/back buffer currently, it should be
  326.  * usable for further buffers when doing ARB_draw_buffer support.
  327.  */
  328. static uint32_t
  329. gen8_update_renderbuffer_surface(struct brw_context *brw,
  330.                                  struct gl_renderbuffer *rb,
  331.                                  bool layered, unsigned unit /* unused */,
  332.                                  uint32_t surf_index)
  333. {
  334.    struct gl_context *ctx = &brw->ctx;
  335.    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
  336.    struct intel_mipmap_tree *mt = irb->mt;
  337.    struct intel_mipmap_tree *aux_mt = NULL;
  338.    uint32_t aux_mode = 0;
  339.    unsigned width = mt->logical_width0;
  340.    unsigned height = mt->logical_height0;
  341.    unsigned pitch = mt->pitch;
  342.    uint32_t tiling = mt->tiling;
  343.    uint32_t format = 0;
  344.    uint32_t surf_type;
  345.    uint32_t offset;
  346.    bool is_array = false;
  347.    int depth = MAX2(irb->layer_count, 1);
  348.    const int min_array_element = (mt->format == MESA_FORMAT_S_UINT8) ?
  349.       irb->mt_layer : (irb->mt_layer / MAX2(mt->num_samples, 1));
  350.    GLenum gl_target =
  351.       rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
  352.    /* FINISHME: Use PTE MOCS on Skylake. */
  353.    uint32_t mocs = brw->gen >= 9 ? SKL_MOCS_WT : BDW_MOCS_PTE;
  354.  
  355.    intel_miptree_used_for_rendering(mt);
  356.  
  357.    switch (gl_target) {
  358.    case GL_TEXTURE_CUBE_MAP_ARRAY:
  359.    case GL_TEXTURE_CUBE_MAP:
  360.       surf_type = BRW_SURFACE_2D;
  361.       is_array = true;
  362.       depth *= 6;
  363.       break;
  364.    case GL_TEXTURE_3D:
  365.       depth = MAX2(irb->mt->logical_depth0, 1);
  366.       /* fallthrough */
  367.    default:
  368.       surf_type = translate_tex_target(gl_target);
  369.       is_array = _mesa_tex_target_is_array(gl_target);
  370.       break;
  371.    }
  372.  
  373.    /* _NEW_BUFFERS */
  374.    /* Render targets can't use IMS layout. Stencil in turn gets configured as
  375.     * single sampled and indexed manually by the program.
  376.     */
  377.    if (mt->format == MESA_FORMAT_S_UINT8) {
  378.       brw_configure_w_tiled(mt, true, &width, &height, &pitch,
  379.                             &tiling, &format);
  380.    } else {
  381.       assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
  382.       assert(brw_render_target_supported(brw, rb));
  383.       mesa_format rb_format = _mesa_get_render_format(ctx,
  384.                                                       intel_rb_format(irb));
  385.       format = brw->render_target_format[rb_format];
  386.       if (unlikely(!brw->format_supported_as_render_target[rb_format]))
  387.          _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
  388.                        __func__, _mesa_get_format_name(rb_format));
  389.    }
  390.  
  391.    if (mt->mcs_mt) {
  392.       aux_mt = mt->mcs_mt;
  393.       aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
  394.    }
  395.  
  396.    uint32_t *surf = allocate_surface_state(brw, &offset, surf_index);
  397.  
  398.    surf[0] = (surf_type << BRW_SURFACE_TYPE_SHIFT) |
  399.              (is_array ? GEN7_SURFACE_IS_ARRAY : 0) |
  400.              (format << BRW_SURFACE_FORMAT_SHIFT) |
  401.              vertical_alignment(mt) |
  402.              horizontal_alignment(mt) |
  403.              surface_tiling_mode(tiling);
  404.  
  405.    surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
  406.  
  407.    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
  408.              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
  409.  
  410.    surf[3] = (depth - 1) << BRW_SURFACE_DEPTH_SHIFT |
  411.              (pitch - 1); /* Surface Pitch */
  412.  
  413.    surf[4] = min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
  414.              (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT;
  415.  
  416.    if (mt->format != MESA_FORMAT_S_UINT8)
  417.       surf[4] |= gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
  418.  
  419.    surf[5] = irb->mt_level - irb->mt->first_level;
  420.  
  421.    if (aux_mt) {
  422.       surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
  423.                 SET_FIELD((aux_mt->pitch / 128) - 1, GEN8_SURFACE_AUX_PITCH) |
  424.                 aux_mode;
  425.    } else {
  426.       surf[6] = 0;
  427.    }
  428.  
  429.    surf[7] = mt->fast_clear_color_value |
  430.              SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
  431.              SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
  432.              SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
  433.              SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
  434.  
  435.    assert(mt->offset % mt->cpp == 0);
  436.    *((uint64_t *) &surf[8]) = mt->bo->offset64 + mt->offset; /* reloc */
  437.  
  438.    if (aux_mt) {
  439.       *((uint64_t *) &surf[10]) = aux_mt->bo->offset64;
  440.       drm_intel_bo_emit_reloc(brw->batch.bo,
  441.                               offset + 10 * 4,
  442.                               aux_mt->bo, 0,
  443.                               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
  444.    } else {
  445.       surf[10] = 0;
  446.       surf[11] = 0;
  447.    }
  448.    surf[12] = 0;
  449.  
  450.    drm_intel_bo_emit_reloc(brw->batch.bo,
  451.                            offset + 8 * 4,
  452.                            mt->bo,
  453.                            mt->offset,
  454.                            I915_GEM_DOMAIN_RENDER,
  455.                            I915_GEM_DOMAIN_RENDER);
  456.  
  457.    return offset;
  458. }
  459.  
  460. void
  461. gen8_init_vtable_surface_functions(struct brw_context *brw)
  462. {
  463.    brw->vtbl.update_texture_surface = gen8_update_texture_surface;
  464.    brw->vtbl.update_renderbuffer_surface = gen8_update_renderbuffer_surface;
  465.    brw->vtbl.emit_null_surface_state = gen8_emit_null_surface_state;
  466.    brw->vtbl.emit_texture_surface_state = gen8_emit_texture_surface_state;
  467.    brw->vtbl.emit_buffer_surface_state = gen8_emit_buffer_surface_state;
  468. }
  469.