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  1. /*
  2.  * Copyright © 2011 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21.  * IN THE SOFTWARE.
  22.  */
  23.  
  24. #include <assert.h>
  25.  
  26. #include "intel_batchbuffer.h"
  27. #include "intel_fbo.h"
  28. #include "intel_mipmap_tree.h"
  29.  
  30. #include "brw_context.h"
  31. #include "brw_defines.h"
  32. #include "brw_state.h"
  33.  
  34. #include "brw_blorp.h"
  35. #include "gen6_blorp.h"
  36.  
  37. /**
  38.  * \name Constants for BLORP VBO
  39.  * \{
  40.  */
  41. #define GEN6_BLORP_NUM_VERTICES 3
  42. #define GEN6_BLORP_NUM_VUE_ELEMS 8
  43. #define GEN6_BLORP_VBO_SIZE (GEN6_BLORP_NUM_VERTICES \
  44.                              * GEN6_BLORP_NUM_VUE_ELEMS \
  45.                              * sizeof(float))
  46. /** \} */
  47.  
  48. /**
  49.  * CMD_STATE_BASE_ADDRESS
  50.  *
  51.  * From the Sandy Bridge PRM, Volume 1, Part 1, Table STATE_BASE_ADDRESS:
  52.  *     The following commands must be reissued following any change to the
  53.  *     base addresses:
  54.  *         3DSTATE_CC_POINTERS
  55.  *         3DSTATE_BINDING_TABLE_POINTERS
  56.  *         3DSTATE_SAMPLER_STATE_POINTERS
  57.  *         3DSTATE_VIEWPORT_STATE_POINTERS
  58.  *         MEDIA_STATE_POINTERS
  59.  */
  60. void
  61. gen6_blorp_emit_state_base_address(struct brw_context *brw,
  62.                                    const brw_blorp_params *params)
  63. {
  64.    uint8_t mocs = brw->gen == 7 ? GEN7_MOCS_L3 : 0;
  65.  
  66.    BEGIN_BATCH(10);
  67.    OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
  68.    OUT_BATCH(mocs << 8 | /* GeneralStateMemoryObjectControlState */
  69.              mocs << 4 | /* StatelessDataPortAccessMemoryObjectControlState */
  70.              1); /* GeneralStateBaseAddressModifyEnable */
  71.  
  72.    /* SurfaceStateBaseAddress */
  73.    OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
  74.    /* DynamicStateBaseAddress */
  75.    OUT_RELOC(brw->batch.bo, (I915_GEM_DOMAIN_RENDER |
  76.                                I915_GEM_DOMAIN_INSTRUCTION), 0, 1);
  77.    OUT_BATCH(1); /* IndirectObjectBaseAddress */
  78.    if (params->use_wm_prog) {
  79.       OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
  80.                 1); /* Instruction base address: shader kernels */
  81.    } else {
  82.       OUT_BATCH(1); /* InstructionBaseAddress */
  83.    }
  84.    OUT_BATCH(1); /* GeneralStateUpperBound */
  85.    /* Dynamic state upper bound.  Although the documentation says that
  86.     * programming it to zero will cause it to be ignored, that is a lie.
  87.     * If this isn't programmed to a real bound, the sampler border color
  88.     * pointer is rejected, causing border color to mysteriously fail.
  89.     */
  90.    OUT_BATCH(0xfffff001);
  91.    OUT_BATCH(1); /* IndirectObjectUpperBound*/
  92.    OUT_BATCH(1); /* InstructionAccessUpperBound */
  93.    ADVANCE_BATCH();
  94. }
  95.  
  96. static void
  97. gen6_blorp_emit_vertex_buffer_state(struct brw_context *brw,
  98.                                     unsigned num_elems,
  99.                                     unsigned vbo_size,
  100.                                     uint32_t vertex_offset)
  101. {
  102.    /* 3DSTATE_VERTEX_BUFFERS */
  103.    const int num_buffers = 1;
  104.    const int batch_length = 1 + 4 * num_buffers;
  105.  
  106.    uint32_t dw0 = GEN6_VB0_ACCESS_VERTEXDATA |
  107.                   (num_elems * sizeof(float)) << BRW_VB0_PITCH_SHIFT;
  108.  
  109.    if (brw->gen >= 7)
  110.       dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
  111.  
  112.    if (brw->gen == 7)
  113.       dw0 |= GEN7_MOCS_L3 << 16;
  114.  
  115.    BEGIN_BATCH(batch_length);
  116.    OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (batch_length - 2));
  117.    OUT_BATCH(dw0);
  118.    /* start address */
  119.    OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
  120.              vertex_offset);
  121.    /* end address */
  122.    OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
  123.              vertex_offset + vbo_size - 1);
  124.    OUT_BATCH(0);
  125.    ADVANCE_BATCH();
  126. }
  127.  
  128. void
  129. gen6_blorp_emit_vertices(struct brw_context *brw,
  130.                          const brw_blorp_params *params)
  131. {
  132.    uint32_t vertex_offset;
  133.  
  134.    /* Setup VBO for the rectangle primitive..
  135.     *
  136.     * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
  137.     * vertices. The vertices reside in screen space with DirectX coordinates
  138.     * (that is, (0, 0) is the upper left corner).
  139.     *
  140.     *   v2 ------ implied
  141.     *    |        |
  142.     *    |        |
  143.     *   v0 ----- v1
  144.     *
  145.     * Since the VS is disabled, the clipper loads each VUE directly from
  146.     * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
  147.     * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
  148.     *   dw0: Reserved, MBZ.
  149.     *   dw1: Render Target Array Index. The HiZ op does not use indexed
  150.     *        vertices, so set the dword to 0.
  151.     *   dw2: Viewport Index. The HiZ op disables viewport mapping and
  152.     *        scissoring, so set the dword to 0.
  153.     *   dw3: Point Width: The HiZ op does not emit the POINTLIST primitive, so
  154.     *        set the dword to 0.
  155.     *   dw4: Vertex Position X.
  156.     *   dw5: Vertex Position Y.
  157.     *   dw6: Vertex Position Z.
  158.     *   dw7: Vertex Position W.
  159.     *
  160.     * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
  161.     * "Vertex URB Entry (VUE) Formats".
  162.     */
  163.    {
  164.       float *vertex_data;
  165.  
  166.       const float vertices[GEN6_BLORP_VBO_SIZE] = {
  167.          /* v0 */ 0, 0, 0, 0,     (float) params->x0, (float) params->y1, 0, 1,
  168.          /* v1 */ 0, 0, 0, 0,     (float) params->x1, (float) params->y1, 0, 1,
  169.          /* v2 */ 0, 0, 0, 0,     (float) params->x0, (float) params->y0, 0, 1,
  170.       };
  171.  
  172.       vertex_data = (float *) brw_state_batch(brw, AUB_TRACE_VERTEX_BUFFER,
  173.                                               GEN6_BLORP_VBO_SIZE, 32,
  174.                                               &vertex_offset);
  175.       memcpy(vertex_data, vertices, GEN6_BLORP_VBO_SIZE);
  176.    }
  177.  
  178.    gen6_blorp_emit_vertex_buffer_state(brw, GEN6_BLORP_NUM_VUE_ELEMS,
  179.                                        GEN6_BLORP_VBO_SIZE,
  180.                                        vertex_offset);
  181.  
  182.    /* 3DSTATE_VERTEX_ELEMENTS
  183.     *
  184.     * Fetch dwords 0 - 7 from each VUE. See the comments above where
  185.     * the vertex_bo is filled with data.
  186.     */
  187.    {
  188.       const int num_elements = 2;
  189.       const int batch_length = 1 + 2 * num_elements;
  190.  
  191.       BEGIN_BATCH(batch_length);
  192.       OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | (batch_length - 2));
  193.       /* Element 0 */
  194.       OUT_BATCH(GEN6_VE0_VALID |
  195.                 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT |
  196.                 0 << BRW_VE0_SRC_OFFSET_SHIFT);
  197.       OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_0_SHIFT |
  198.                 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_1_SHIFT |
  199.                 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_2_SHIFT |
  200.                 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_3_SHIFT);
  201.       /* Element 1 */
  202.       OUT_BATCH(GEN6_VE0_VALID |
  203.                 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT |
  204.                 16 << BRW_VE0_SRC_OFFSET_SHIFT);
  205.       OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_0_SHIFT |
  206.                 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_1_SHIFT |
  207.                 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_2_SHIFT |
  208.                 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_3_SHIFT);
  209.       ADVANCE_BATCH();
  210.    }
  211. }
  212.  
  213.  
  214. /* 3DSTATE_URB
  215.  *
  216.  * Assign the entire URB to the VS. Even though the VS disabled, URB space
  217.  * is still needed because the clipper loads the VUE's from the URB. From
  218.  * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
  219.  * Dword 1.15:0 "VS Number of URB Entries":
  220.  *     This field is always used (even if VS Function Enable is DISABLED).
  221.  *
  222.  * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
  223.  * safely ignore it because this batch contains only one draw call.
  224.  *     Because of URB corruption caused by allocating a previous GS unit
  225.  *     URB entry to the VS unit, software is required to send a “GS NULL
  226.  *     Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
  227.  *     plus a dummy DRAW call before any case where VS will be taking over
  228.  *     GS URB space.
  229.  */
  230. static void
  231. gen6_blorp_emit_urb_config(struct brw_context *brw,
  232.                            const brw_blorp_params *params)
  233. {
  234.    BEGIN_BATCH(3);
  235.    OUT_BATCH(_3DSTATE_URB << 16 | (3 - 2));
  236.    OUT_BATCH(brw->urb.max_vs_entries << GEN6_URB_VS_ENTRIES_SHIFT);
  237.    OUT_BATCH(0);
  238.    ADVANCE_BATCH();
  239. }
  240.  
  241.  
  242. /* BLEND_STATE */
  243. uint32_t
  244. gen6_blorp_emit_blend_state(struct brw_context *brw,
  245.                             const brw_blorp_params *params)
  246. {
  247.    uint32_t cc_blend_state_offset;
  248.  
  249.    assume(params->num_draw_buffers);
  250.  
  251.    const unsigned size = params->num_draw_buffers *
  252.                          sizeof(struct gen6_blend_state);
  253.    struct gen6_blend_state *blend = (struct gen6_blend_state *)
  254.       brw_state_batch(brw, AUB_TRACE_BLEND_STATE, size, 64,
  255.                       &cc_blend_state_offset);
  256.  
  257.    memset(blend, 0, size);
  258.  
  259.    for (unsigned i = 0; i < params->num_draw_buffers; ++i) {
  260.       blend[i].blend1.pre_blend_clamp_enable = 1;
  261.       blend[i].blend1.post_blend_clamp_enable = 1;
  262.       blend[i].blend1.clamp_range = BRW_RENDERTARGET_CLAMPRANGE_FORMAT;
  263.    }
  264.  
  265.    return cc_blend_state_offset;
  266. }
  267.  
  268.  
  269. /* CC_STATE */
  270. uint32_t
  271. gen6_blorp_emit_cc_state(struct brw_context *brw)
  272. {
  273.    uint32_t cc_state_offset;
  274.  
  275.    struct gen6_color_calc_state *cc = (struct gen6_color_calc_state *)
  276.       brw_state_batch(brw, AUB_TRACE_CC_STATE,
  277.                       sizeof(gen6_color_calc_state), 64,
  278.                       &cc_state_offset);
  279.    memset(cc, 0, sizeof(*cc));
  280.  
  281.    return cc_state_offset;
  282. }
  283.  
  284.  
  285. /**
  286.  * \param out_offset is relative to
  287.  *        CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
  288.  */
  289. uint32_t
  290. gen6_blorp_emit_depth_stencil_state(struct brw_context *brw,
  291.                                     const brw_blorp_params *params)
  292. {
  293.    uint32_t depthstencil_offset;
  294.  
  295.    struct gen6_depth_stencil_state *state;
  296.    state = (struct gen6_depth_stencil_state *)
  297.       brw_state_batch(brw, AUB_TRACE_DEPTH_STENCIL_STATE,
  298.                       sizeof(*state), 64,
  299.                       &depthstencil_offset);
  300.    memset(state, 0, sizeof(*state));
  301.  
  302.    /* See the following sections of the Sandy Bridge PRM, Volume 1, Part2:
  303.     *   - 7.5.3.1 Depth Buffer Clear
  304.     *   - 7.5.3.2 Depth Buffer Resolve
  305.     *   - 7.5.3.3 Hierarchical Depth Buffer Resolve
  306.     */
  307.    state->ds2.depth_write_enable = 1;
  308.    if (params->hiz_op == GEN6_HIZ_OP_DEPTH_RESOLVE) {
  309.       state->ds2.depth_test_enable = 1;
  310.       state->ds2.depth_test_func = BRW_COMPAREFUNCTION_NEVER;
  311.    }
  312.  
  313.    return depthstencil_offset;
  314. }
  315.  
  316.  
  317. /* 3DSTATE_CC_STATE_POINTERS
  318.  *
  319.  * The pointer offsets are relative to
  320.  * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
  321.  *
  322.  * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
  323.  */
  324. static void
  325. gen6_blorp_emit_cc_state_pointers(struct brw_context *brw,
  326.                                   const brw_blorp_params *params,
  327.                                   uint32_t cc_blend_state_offset,
  328.                                   uint32_t depthstencil_offset,
  329.                                   uint32_t cc_state_offset)
  330. {
  331.    BEGIN_BATCH(4);
  332.    OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
  333.    OUT_BATCH(cc_blend_state_offset | 1); /* BLEND_STATE offset */
  334.    OUT_BATCH(depthstencil_offset | 1); /* DEPTH_STENCIL_STATE offset */
  335.    OUT_BATCH(cc_state_offset | 1); /* COLOR_CALC_STATE offset */
  336.    ADVANCE_BATCH();
  337. }
  338.  
  339.  
  340. /* WM push constants */
  341. uint32_t
  342. gen6_blorp_emit_wm_constants(struct brw_context *brw,
  343.                              const brw_blorp_params *params)
  344. {
  345.    uint32_t wm_push_const_offset;
  346.  
  347.    void *constants = brw_state_batch(brw, AUB_TRACE_WM_CONSTANTS,
  348.                                      sizeof(params->wm_push_consts),
  349.                                      32, &wm_push_const_offset);
  350.    memcpy(constants, &params->wm_push_consts,
  351.           sizeof(params->wm_push_consts));
  352.  
  353.    return wm_push_const_offset;
  354. }
  355.  
  356.  
  357. /* SURFACE_STATE for renderbuffer or texture surface (see
  358.  * brw_update_renderbuffer_surface and brw_update_texture_surface)
  359.  */
  360. static uint32_t
  361. gen6_blorp_emit_surface_state(struct brw_context *brw,
  362.                               const brw_blorp_params *params,
  363.                               const brw_blorp_surface_info *surface,
  364.                               uint32_t read_domains, uint32_t write_domain)
  365. {
  366.    uint32_t wm_surf_offset;
  367.    uint32_t width = surface->width;
  368.    uint32_t height = surface->height;
  369.    if (surface->num_samples > 1) {
  370.       /* Since gen6 uses INTEL_MSAA_LAYOUT_IMS, width and height are measured
  371.        * in samples.  But SURFACE_STATE wants them in pixels, so we need to
  372.        * divide them each by 2.
  373.        */
  374.       width /= 2;
  375.       height /= 2;
  376.    }
  377.    struct intel_mipmap_tree *mt = surface->mt;
  378.    uint32_t tile_x, tile_y;
  379.  
  380.    uint32_t *surf = (uint32_t *)
  381.       brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
  382.                       &wm_surf_offset);
  383.  
  384.    surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
  385.               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
  386.               BRW_SURFACE_CUBEFACE_ENABLES |
  387.               surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT);
  388.  
  389.    /* reloc */
  390.    surf[1] = (surface->compute_tile_offsets(&tile_x, &tile_y) +
  391.               mt->bo->offset64);
  392.  
  393.    surf[2] = (0 << BRW_SURFACE_LOD_SHIFT |
  394.               (width - 1) << BRW_SURFACE_WIDTH_SHIFT |
  395.               (height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
  396.  
  397.    uint32_t tiling = surface->map_stencil_as_y_tiled
  398.       ? BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y
  399.       : brw_get_surface_tiling_bits(mt->tiling);
  400.    uint32_t pitch_bytes = mt->pitch;
  401.    if (surface->map_stencil_as_y_tiled)
  402.       pitch_bytes *= 2;
  403.    surf[3] = (tiling |
  404.               0 << BRW_SURFACE_DEPTH_SHIFT |
  405.               (pitch_bytes - 1) << BRW_SURFACE_PITCH_SHIFT);
  406.  
  407.    surf[4] = brw_get_surface_num_multisamples(surface->num_samples);
  408.  
  409.    /* Note that the low bits of these fields are missing, so
  410.     * there's the possibility of getting in trouble.
  411.     */
  412.    assert(tile_x % 4 == 0);
  413.    assert(tile_y % 2 == 0);
  414.    surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
  415.               (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
  416.               (surface->mt->align_h == 4 ?
  417.                BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
  418.  
  419.    /* Emit relocation to surface contents */
  420.    drm_intel_bo_emit_reloc(brw->batch.bo,
  421.                            wm_surf_offset + 4,
  422.                            mt->bo,
  423.                            surf[1] - mt->bo->offset64,
  424.                            read_domains, write_domain);
  425.  
  426.    return wm_surf_offset;
  427. }
  428.  
  429.  
  430. /* BINDING_TABLE.  See brw_wm_binding_table(). */
  431. uint32_t
  432. gen6_blorp_emit_binding_table(struct brw_context *brw,
  433.                               uint32_t wm_surf_offset_renderbuffer,
  434.                               uint32_t wm_surf_offset_texture)
  435. {
  436.    uint32_t wm_bind_bo_offset;
  437.    uint32_t *bind = (uint32_t *)
  438.       brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
  439.                       sizeof(uint32_t) *
  440.                       BRW_BLORP_NUM_BINDING_TABLE_ENTRIES,
  441.                       32, /* alignment */
  442.                       &wm_bind_bo_offset);
  443.    bind[BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX] =
  444.       wm_surf_offset_renderbuffer;
  445.    bind[BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX] = wm_surf_offset_texture;
  446.  
  447.    return wm_bind_bo_offset;
  448. }
  449.  
  450.  
  451. /**
  452.  * SAMPLER_STATE.  See brw_update_sampler_state().
  453.  */
  454. uint32_t
  455. gen6_blorp_emit_sampler_state(struct brw_context *brw,
  456.                               unsigned tex_filter, unsigned max_lod,
  457.                               bool non_normalized_coords)
  458. {
  459.    uint32_t sampler_offset;
  460.    uint32_t *sampler_state = (uint32_t *)
  461.       brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE, 16, 32, &sampler_offset);
  462.  
  463.    unsigned address_rounding = BRW_ADDRESS_ROUNDING_ENABLE_U_MIN |
  464.                                BRW_ADDRESS_ROUNDING_ENABLE_V_MIN |
  465.                                BRW_ADDRESS_ROUNDING_ENABLE_R_MIN |
  466.                                BRW_ADDRESS_ROUNDING_ENABLE_U_MAG |
  467.                                BRW_ADDRESS_ROUNDING_ENABLE_V_MAG |
  468.                                BRW_ADDRESS_ROUNDING_ENABLE_R_MAG;
  469.  
  470.    /* XXX: I don't think that using firstLevel, lastLevel works,
  471.     * because we always setup the surface state as if firstLevel ==
  472.     * level zero.  Probably have to subtract firstLevel from each of
  473.     * these:
  474.     */
  475.    brw_emit_sampler_state(brw,
  476.                           sampler_state,
  477.                           sampler_offset,
  478.                           tex_filter, /* min filter */
  479.                           tex_filter, /* mag filter */
  480.                           BRW_MIPFILTER_NONE,
  481.                           BRW_ANISORATIO_2,
  482.                           address_rounding,
  483.                           BRW_TEXCOORDMODE_CLAMP,
  484.                           BRW_TEXCOORDMODE_CLAMP,
  485.                           BRW_TEXCOORDMODE_CLAMP,
  486.                           0, /* min LOD */
  487.                           max_lod,
  488.                           0, /* LOD bias */
  489.                           0, /* base miplevel */
  490.                           0, /* shadow function */
  491.                           non_normalized_coords,
  492.                           0); /* border color offset - unused */
  493.  
  494.    return sampler_offset;
  495. }
  496.  
  497.  
  498. /**
  499.  * 3DSTATE_SAMPLER_STATE_POINTERS.  See upload_sampler_state_pointers().
  500.  */
  501. static void
  502. gen6_blorp_emit_sampler_state_pointers(struct brw_context *brw,
  503.                                        uint32_t sampler_offset)
  504. {
  505.    BEGIN_BATCH(4);
  506.    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS << 16 |
  507.              VS_SAMPLER_STATE_CHANGE |
  508.              GS_SAMPLER_STATE_CHANGE |
  509.              PS_SAMPLER_STATE_CHANGE |
  510.              (4 - 2));
  511.    OUT_BATCH(0); /* VS */
  512.    OUT_BATCH(0); /* GS */
  513.    OUT_BATCH(sampler_offset);
  514.    ADVANCE_BATCH();
  515. }
  516.  
  517.  
  518. /* 3DSTATE_VS
  519.  *
  520.  * Disable vertex shader.
  521.  */
  522. void
  523. gen6_blorp_emit_vs_disable(struct brw_context *brw,
  524.                            const brw_blorp_params *params)
  525. {
  526.    /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
  527.     * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
  528.     *
  529.     *   [DevSNB] A pipeline flush must be programmed prior to a
  530.     *   3DSTATE_VS command that causes the VS Function Enable to
  531.     *   toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
  532.     *   command with CS stall bit set and a post sync operation.
  533.     *
  534.     * We've already done one at the start of the BLORP operation.
  535.     */
  536.  
  537.    /* Disable the push constant buffers. */
  538.    BEGIN_BATCH(5);
  539.    OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (5 - 2));
  540.    OUT_BATCH(0);
  541.    OUT_BATCH(0);
  542.    OUT_BATCH(0);
  543.    OUT_BATCH(0);
  544.    ADVANCE_BATCH();
  545.  
  546.    BEGIN_BATCH(6);
  547.    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
  548.    OUT_BATCH(0);
  549.    OUT_BATCH(0);
  550.    OUT_BATCH(0);
  551.    OUT_BATCH(0);
  552.    OUT_BATCH(0);
  553.    ADVANCE_BATCH();
  554. }
  555.  
  556.  
  557. /* 3DSTATE_GS
  558.  *
  559.  * Disable the geometry shader.
  560.  */
  561. void
  562. gen6_blorp_emit_gs_disable(struct brw_context *brw,
  563.                            const brw_blorp_params *params)
  564. {
  565.    /* Disable all the constant buffers. */
  566.    BEGIN_BATCH(5);
  567.    OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (5 - 2));
  568.    OUT_BATCH(0);
  569.    OUT_BATCH(0);
  570.    OUT_BATCH(0);
  571.    OUT_BATCH(0);
  572.    ADVANCE_BATCH();
  573.  
  574.    BEGIN_BATCH(7);
  575.    OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
  576.    OUT_BATCH(0);
  577.    OUT_BATCH(0);
  578.    OUT_BATCH(0);
  579.    OUT_BATCH(0);
  580.    OUT_BATCH(0);
  581.    OUT_BATCH(0);
  582.    ADVANCE_BATCH();
  583.    brw->gs.enabled = false;
  584. }
  585.  
  586.  
  587. /* 3DSTATE_CLIP
  588.  *
  589.  * Disable the clipper.
  590.  *
  591.  * The BLORP op emits a rectangle primitive, which requires clipping to
  592.  * be disabled. From page 10 of the Sandy Bridge PRM Volume 2 Part 1
  593.  * Section 1.3 "3D Primitives Overview":
  594.  *    RECTLIST:
  595.  *    Either the CLIP unit should be DISABLED, or the CLIP unit's Clip
  596.  *    Mode should be set to a value other than CLIPMODE_NORMAL.
  597.  *
  598.  * Also disable perspective divide. This doesn't change the clipper's
  599.  * output, but does spare a few electrons.
  600.  */
  601. void
  602. gen6_blorp_emit_clip_disable(struct brw_context *brw)
  603. {
  604.    BEGIN_BATCH(4);
  605.    OUT_BATCH(_3DSTATE_CLIP << 16 | (4 - 2));
  606.    OUT_BATCH(0);
  607.    OUT_BATCH(GEN6_CLIP_PERSPECTIVE_DIVIDE_DISABLE);
  608.    OUT_BATCH(0);
  609.    ADVANCE_BATCH();
  610. }
  611.  
  612.  
  613. /* 3DSTATE_SF
  614.  *
  615.  * Disable ViewportTransformEnable (dw2.1)
  616.  *
  617.  * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
  618.  * Primitives Overview":
  619.  *     RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
  620.  *     use of screen- space coordinates).
  621.  *
  622.  * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
  623.  * and BackFaceFillMode (dw2.5:6) to SOLID(0).
  624.  *
  625.  * From the Sandy Bridge PRM, Volume 2, Part 1, Section
  626.  * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
  627.  *     SOLID: Any triangle or rectangle object found to be front-facing
  628.  *     is rendered as a solid object. This setting is required when
  629.  *     (rendering rectangle (RECTLIST) objects.
  630.  */
  631. static void
  632. gen6_blorp_emit_sf_config(struct brw_context *brw,
  633.                           const brw_blorp_params *params)
  634. {
  635.    BEGIN_BATCH(20);
  636.    OUT_BATCH(_3DSTATE_SF << 16 | (20 - 2));
  637.    OUT_BATCH(params->num_varyings << GEN6_SF_NUM_OUTPUTS_SHIFT |
  638.              1 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT |
  639.              BRW_SF_URB_ENTRY_READ_OFFSET <<
  640.                 GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT);
  641.    OUT_BATCH(0); /* dw2 */
  642.    OUT_BATCH(params->dst.num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
  643.    for (int i = 0; i < 16; ++i)
  644.       OUT_BATCH(0);
  645.    ADVANCE_BATCH();
  646. }
  647.  
  648.  
  649. /**
  650.  * Enable or disable thread dispatch and set the HiZ op appropriately.
  651.  */
  652. static void
  653. gen6_blorp_emit_wm_config(struct brw_context *brw,
  654.                           const brw_blorp_params *params,
  655.                           uint32_t prog_offset,
  656.                           brw_blorp_prog_data *prog_data)
  657. {
  658.    uint32_t dw2, dw4, dw5, dw6;
  659.  
  660.    /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
  661.     * nonzero to prevent the GPU from hanging.  While the documentation doesn't
  662.     * mention this explicitly, it notes that the valid range for the field is
  663.     * [1,39] = [2,40] threads, which excludes zero.
  664.     *
  665.     * To be safe (and to minimize extraneous code) we go ahead and fully
  666.     * configure the WM state whether or not there is a WM program.
  667.     */
  668.  
  669.    dw2 = dw4 = dw5 = dw6 = 0;
  670.    switch (params->hiz_op) {
  671.    case GEN6_HIZ_OP_DEPTH_CLEAR:
  672.       dw4 |= GEN6_WM_DEPTH_CLEAR;
  673.       break;
  674.    case GEN6_HIZ_OP_DEPTH_RESOLVE:
  675.       dw4 |= GEN6_WM_DEPTH_RESOLVE;
  676.       break;
  677.    case GEN6_HIZ_OP_HIZ_RESOLVE:
  678.       dw4 |= GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE;
  679.       break;
  680.    case GEN6_HIZ_OP_NONE:
  681.       break;
  682.    default:
  683.       unreachable("not reached");
  684.    }
  685.    dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
  686.    dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5;
  687.    dw5 |= (brw->max_wm_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT;
  688.    dw6 |= 0 << GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
  689.    dw6 |= 0 << GEN6_WM_NUM_SF_OUTPUTS_SHIFT; /* No inputs from SF */
  690.    if (params->use_wm_prog) {
  691.       dw2 |= 1 << GEN6_WM_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
  692.       dw4 |= prog_data->first_curbe_grf << GEN6_WM_DISPATCH_START_GRF_SHIFT_0;
  693.       dw5 |= GEN6_WM_16_DISPATCH_ENABLE;
  694.       dw5 |= GEN6_WM_KILL_ENABLE; /* TODO: temporarily smash on */
  695.       dw5 |= GEN6_WM_DISPATCH_ENABLE; /* We are rendering */
  696.    }
  697.  
  698.    if (params->dst.num_samples > 1) {
  699.       dw6 |= GEN6_WM_MSRAST_ON_PATTERN;
  700.       if (prog_data && prog_data->persample_msaa_dispatch)
  701.          dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE;
  702.       else
  703.          dw6 |= GEN6_WM_MSDISPMODE_PERPIXEL;
  704.    } else {
  705.       dw6 |= GEN6_WM_MSRAST_OFF_PIXEL;
  706.       dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE;
  707.    }
  708.  
  709.    BEGIN_BATCH(9);
  710.    OUT_BATCH(_3DSTATE_WM << 16 | (9 - 2));
  711.    OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
  712.    OUT_BATCH(dw2);
  713.    OUT_BATCH(0); /* No scratch needed */
  714.    OUT_BATCH(dw4);
  715.    OUT_BATCH(dw5);
  716.    OUT_BATCH(dw6);
  717.    OUT_BATCH(0); /* No other programs */
  718.    OUT_BATCH(0); /* No other programs */
  719.    ADVANCE_BATCH();
  720. }
  721.  
  722.  
  723. static void
  724. gen6_blorp_emit_constant_ps(struct brw_context *brw,
  725.                             const brw_blorp_params *params,
  726.                             uint32_t wm_push_const_offset)
  727. {
  728.    /* Make sure the push constants fill an exact integer number of
  729.     * registers.
  730.     */
  731.    assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0);
  732.  
  733.    /* There must be at least one register worth of push constant data. */
  734.    assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0);
  735.  
  736.    /* Enable push constant buffer 0. */
  737.    BEGIN_BATCH(5);
  738.    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
  739.              GEN6_CONSTANT_BUFFER_0_ENABLE |
  740.              (5 - 2));
  741.    OUT_BATCH(wm_push_const_offset + (BRW_BLORP_NUM_PUSH_CONST_REGS - 1));
  742.    OUT_BATCH(0);
  743.    OUT_BATCH(0);
  744.    OUT_BATCH(0);
  745.    ADVANCE_BATCH();
  746. }
  747.  
  748. static void
  749. gen6_blorp_emit_constant_ps_disable(struct brw_context *brw,
  750.                                     const brw_blorp_params *params)
  751. {
  752.    /* Disable the push constant buffers. */
  753.    BEGIN_BATCH(5);
  754.    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (5 - 2));
  755.    OUT_BATCH(0);
  756.    OUT_BATCH(0);
  757.    OUT_BATCH(0);
  758.    OUT_BATCH(0);
  759.    ADVANCE_BATCH();
  760. }
  761.  
  762. /**
  763.  * 3DSTATE_BINDING_TABLE_POINTERS
  764.  */
  765. static void
  766. gen6_blorp_emit_binding_table_pointers(struct brw_context *brw,
  767.                                        uint32_t wm_bind_bo_offset)
  768. {
  769.    BEGIN_BATCH(4);
  770.    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 |
  771.              GEN6_BINDING_TABLE_MODIFY_PS |
  772.              (4 - 2));
  773.    OUT_BATCH(0); /* vs -- ignored */
  774.    OUT_BATCH(0); /* gs -- ignored */
  775.    OUT_BATCH(wm_bind_bo_offset); /* wm/ps */
  776.    ADVANCE_BATCH();
  777. }
  778.  
  779.  
  780. static void
  781. gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
  782.                                      const brw_blorp_params *params)
  783. {
  784.    uint32_t surfwidth, surfheight;
  785.    uint32_t surftype;
  786.    unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
  787.    GLenum gl_target = params->depth.mt->target;
  788.    unsigned int lod;
  789.  
  790.    switch (gl_target) {
  791.    case GL_TEXTURE_CUBE_MAP_ARRAY:
  792.    case GL_TEXTURE_CUBE_MAP:
  793.       /* The PRM claims that we should use BRW_SURFACE_CUBE for this
  794.        * situation, but experiments show that gl_Layer doesn't work when we do
  795.        * this.  So we use BRW_SURFACE_2D, since for rendering purposes this is
  796.        * equivalent.
  797.        */
  798.       surftype = BRW_SURFACE_2D;
  799.       depth *= 6;
  800.       break;
  801.    default:
  802.       surftype = translate_tex_target(gl_target);
  803.       break;
  804.    }
  805.  
  806.    const unsigned min_array_element = params->depth.layer;
  807.  
  808.    lod = params->depth.level - params->depth.mt->first_level;
  809.  
  810.    if (params->hiz_op != GEN6_HIZ_OP_NONE && lod == 0) {
  811.       /* HIZ ops for lod 0 may set the width & height a little
  812.        * larger to allow the fast depth clear to fit the hardware
  813.        * alignment requirements. (8x4)
  814.        */
  815.       surfwidth = params->depth.width;
  816.       surfheight = params->depth.height;
  817.    } else {
  818.       surfwidth = params->depth.mt->logical_width0;
  819.       surfheight = params->depth.mt->logical_height0;
  820.    }
  821.  
  822.    /* 3DSTATE_DEPTH_BUFFER */
  823.    {
  824.       intel_emit_depth_stall_flushes(brw);
  825.  
  826.       BEGIN_BATCH(7);
  827.       /* 3DSTATE_DEPTH_BUFFER dw0 */
  828.       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
  829.  
  830.       /* 3DSTATE_DEPTH_BUFFER dw1 */
  831.       OUT_BATCH((params->depth.mt->pitch - 1) |
  832.                 params->depth_format << 18 |
  833.                 1 << 21 | /* separate stencil enable */
  834.                 1 << 22 | /* hiz enable */
  835.                 BRW_TILEWALK_YMAJOR << 26 |
  836.                 1 << 27 | /* y-tiled */
  837.                 surftype << 29);
  838.  
  839.       /* 3DSTATE_DEPTH_BUFFER dw2 */
  840.       OUT_RELOC(params->depth.mt->bo,
  841.                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  842.                 0);
  843.  
  844.       /* 3DSTATE_DEPTH_BUFFER dw3 */
  845.       OUT_BATCH(BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1 |
  846.                 (surfwidth - 1) << 6 |
  847.                 (surfheight - 1) << 19 |
  848.                 lod << 2);
  849.  
  850.       /* 3DSTATE_DEPTH_BUFFER dw4 */
  851.       OUT_BATCH((depth - 1) << 21 |
  852.                 min_array_element << 10 |
  853.                 (depth - 1) << 1);
  854.  
  855.       /* 3DSTATE_DEPTH_BUFFER dw5 */
  856.       OUT_BATCH(0);
  857.  
  858.       /* 3DSTATE_DEPTH_BUFFER dw6 */
  859.       OUT_BATCH(0);
  860.       ADVANCE_BATCH();
  861.    }
  862.  
  863.    /* 3DSTATE_HIER_DEPTH_BUFFER */
  864.    {
  865.       struct intel_mipmap_tree *hiz_mt = params->depth.mt->hiz_buf->mt;
  866.       uint32_t offset = 0;
  867.  
  868.       if (hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
  869.          offset = intel_miptree_get_aligned_offset(hiz_mt,
  870.                                                    hiz_mt->level[lod].level_x,
  871.                                                    hiz_mt->level[lod].level_y,
  872.                                                    false);
  873.       }
  874.  
  875.       BEGIN_BATCH(3);
  876.       OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
  877.       OUT_BATCH(hiz_mt->pitch - 1);
  878.       OUT_RELOC(hiz_mt->bo,
  879.                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  880.                 offset);
  881.       ADVANCE_BATCH();
  882.    }
  883.  
  884.    /* 3DSTATE_STENCIL_BUFFER */
  885.    {
  886.       BEGIN_BATCH(3);
  887.       OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
  888.       OUT_BATCH(0);
  889.       OUT_BATCH(0);
  890.       ADVANCE_BATCH();
  891.    }
  892. }
  893.  
  894.  
  895. static void
  896. gen6_blorp_emit_depth_disable(struct brw_context *brw,
  897.                               const brw_blorp_params *params)
  898. {
  899.    intel_emit_depth_stall_flushes(brw);
  900.  
  901.    BEGIN_BATCH(7);
  902.    OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
  903.    OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
  904.              (BRW_SURFACE_NULL << 29));
  905.    OUT_BATCH(0);
  906.    OUT_BATCH(0);
  907.    OUT_BATCH(0);
  908.    OUT_BATCH(0);
  909.    OUT_BATCH(0);
  910.    ADVANCE_BATCH();
  911.  
  912.    BEGIN_BATCH(3);
  913.    OUT_BATCH(_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
  914.    OUT_BATCH(0);
  915.    OUT_BATCH(0);
  916.    ADVANCE_BATCH();
  917.  
  918.    BEGIN_BATCH(3);
  919.    OUT_BATCH(_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
  920.    OUT_BATCH(0);
  921.    OUT_BATCH(0);
  922.    ADVANCE_BATCH();
  923. }
  924.  
  925.  
  926. /* 3DSTATE_CLEAR_PARAMS
  927.  *
  928.  * From the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE_CLEAR_PARAMS:
  929.  *   [DevSNB] 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE
  930.  *   packet when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
  931.  */
  932. static void
  933. gen6_blorp_emit_clear_params(struct brw_context *brw,
  934.                              const brw_blorp_params *params)
  935. {
  936.    BEGIN_BATCH(2);
  937.    OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 |
  938.              GEN5_DEPTH_CLEAR_VALID |
  939.              (2 - 2));
  940.    OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0);
  941.    ADVANCE_BATCH();
  942. }
  943.  
  944.  
  945. /* 3DSTATE_DRAWING_RECTANGLE */
  946. void
  947. gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
  948.                                   const brw_blorp_params *params)
  949. {
  950.    BEGIN_BATCH(4);
  951.    OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
  952.    OUT_BATCH(0);
  953.    OUT_BATCH(((MAX2(params->x1, params->x0) - 1) & 0xffff) |
  954.              ((MAX2(params->y1, params->y0) - 1) << 16));
  955.    OUT_BATCH(0);
  956.    ADVANCE_BATCH();
  957. }
  958.  
  959. /* 3DSTATE_VIEWPORT_STATE_POINTERS */
  960. void
  961. gen6_blorp_emit_viewport_state(struct brw_context *brw,
  962.                                const brw_blorp_params *params)
  963. {
  964.    struct brw_cc_viewport *ccv;
  965.    uint32_t cc_vp_offset;
  966.  
  967.    ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
  968.                                                    sizeof(*ccv), 32,
  969.                                                    &cc_vp_offset);
  970.  
  971.    ccv->min_depth = 0.0;
  972.    ccv->max_depth = 1.0;
  973.  
  974.    BEGIN_BATCH(4);
  975.    OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS << 16 | (4 - 2) |
  976.              GEN6_CC_VIEWPORT_MODIFY);
  977.    OUT_BATCH(0); /* clip VP */
  978.    OUT_BATCH(0); /* SF VP */
  979.    OUT_BATCH(cc_vp_offset);
  980.    ADVANCE_BATCH();
  981. }
  982.  
  983.  
  984. /* 3DPRIMITIVE */
  985. static void
  986. gen6_blorp_emit_primitive(struct brw_context *brw,
  987.                           const brw_blorp_params *params)
  988. {
  989.    BEGIN_BATCH(6);
  990.    OUT_BATCH(CMD_3D_PRIM << 16 | (6 - 2) |
  991.              _3DPRIM_RECTLIST << GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT |
  992.              GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL);
  993.    OUT_BATCH(3); /* vertex count per instance */
  994.    OUT_BATCH(0);
  995.    OUT_BATCH(params->num_layers); /* instance count */
  996.    OUT_BATCH(0);
  997.    OUT_BATCH(0);
  998.    ADVANCE_BATCH();
  999. }
  1000.  
  1001. /**
  1002.  * \brief Execute a blit or render pass operation.
  1003.  *
  1004.  * To execute the operation, this function manually constructs and emits a
  1005.  * batch to draw a rectangle primitive. The batchbuffer is flushed before
  1006.  * constructing and after emitting the batch.
  1007.  *
  1008.  * This function alters no GL state.
  1009.  */
  1010. void
  1011. gen6_blorp_exec(struct brw_context *brw,
  1012.                 const brw_blorp_params *params)
  1013. {
  1014.    brw_blorp_prog_data *prog_data = NULL;
  1015.    uint32_t cc_blend_state_offset = 0;
  1016.    uint32_t cc_state_offset = 0;
  1017.    uint32_t depthstencil_offset;
  1018.    uint32_t wm_push_const_offset = 0;
  1019.    uint32_t wm_bind_bo_offset = 0;
  1020.  
  1021.    uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
  1022.  
  1023.    /* Emit workaround flushes when we switch from drawing to blorping. */
  1024.    intel_emit_post_sync_nonzero_flush(brw);
  1025.  
  1026.    gen6_emit_3dstate_multisample(brw, params->dst.num_samples);
  1027.    gen6_emit_3dstate_sample_mask(brw,
  1028.                                  params->dst.num_samples > 1 ?
  1029.                                  (1 << params->dst.num_samples) - 1 : 1);
  1030.    gen6_blorp_emit_state_base_address(brw, params);
  1031.    gen6_blorp_emit_vertices(brw, params);
  1032.    gen6_blorp_emit_urb_config(brw, params);
  1033.    if (params->use_wm_prog) {
  1034.       cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
  1035.       cc_state_offset = gen6_blorp_emit_cc_state(brw);
  1036.    }
  1037.    depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
  1038.    gen6_blorp_emit_cc_state_pointers(brw, params, cc_blend_state_offset,
  1039.                                      depthstencil_offset, cc_state_offset);
  1040.    if (params->use_wm_prog) {
  1041.       uint32_t wm_surf_offset_renderbuffer;
  1042.       uint32_t wm_surf_offset_texture = 0;
  1043.       uint32_t sampler_offset;
  1044.       wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
  1045.       intel_miptree_used_for_rendering(params->dst.mt);
  1046.       wm_surf_offset_renderbuffer =
  1047.          gen6_blorp_emit_surface_state(brw, params, &params->dst,
  1048.                                        I915_GEM_DOMAIN_RENDER,
  1049.                                        I915_GEM_DOMAIN_RENDER);
  1050.       if (params->src.mt) {
  1051.          wm_surf_offset_texture =
  1052.             gen6_blorp_emit_surface_state(brw, params, &params->src,
  1053.                                           I915_GEM_DOMAIN_SAMPLER, 0);
  1054.       }
  1055.       wm_bind_bo_offset =
  1056.          gen6_blorp_emit_binding_table(brw,
  1057.                                        wm_surf_offset_renderbuffer,
  1058.                                        wm_surf_offset_texture);
  1059.       sampler_offset =
  1060.          gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true);
  1061.       gen6_blorp_emit_sampler_state_pointers(brw, sampler_offset);
  1062.    }
  1063.    gen6_blorp_emit_vs_disable(brw, params);
  1064.    gen6_blorp_emit_gs_disable(brw, params);
  1065.    gen6_blorp_emit_clip_disable(brw);
  1066.    gen6_blorp_emit_sf_config(brw, params);
  1067.    if (params->use_wm_prog)
  1068.       gen6_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
  1069.    else
  1070.       gen6_blorp_emit_constant_ps_disable(brw, params);
  1071.    gen6_blorp_emit_wm_config(brw, params, prog_offset, prog_data);
  1072.    if (params->use_wm_prog)
  1073.       gen6_blorp_emit_binding_table_pointers(brw, wm_bind_bo_offset);
  1074.    gen6_blorp_emit_viewport_state(brw, params);
  1075.  
  1076.    if (params->depth.mt)
  1077.       gen6_blorp_emit_depth_stencil_config(brw, params);
  1078.    else
  1079.       gen6_blorp_emit_depth_disable(brw, params);
  1080.    gen6_blorp_emit_clear_params(brw, params);
  1081.    gen6_blorp_emit_drawing_rectangle(brw, params);
  1082.    gen6_blorp_emit_primitive(brw, params);
  1083. }
  1084.  
  1085.