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  1. /*
  2.  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * on the rights to use, copy, modify, merge, publish, distribute, sub
  8.  * license, and/or sell copies of the Software, and to permit persons to whom
  9.  * the Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18.  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19.  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20.  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21.  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22.  */
  23. #include "r600_pipe.h"
  24. #include "r600_public.h"
  25. #include "r600_isa.h"
  26. #include "evergreen_compute.h"
  27. #include "r600d.h"
  28.  
  29. #include "sb/sb_public.h"
  30.  
  31. #include <errno.h>
  32. #include "pipe/p_shader_tokens.h"
  33. #include "util/u_debug.h"
  34. #include "util/u_memory.h"
  35. #include "util/u_simple_shaders.h"
  36. #include "util/u_upload_mgr.h"
  37. #include "util/u_math.h"
  38. #include "vl/vl_decoder.h"
  39. #include "vl/vl_video_buffer.h"
  40. #include "radeon/radeon_video.h"
  41. #include "radeon/radeon_uvd.h"
  42. #include "os/os_time.h"
  43.  
  44. static const struct debug_named_value r600_debug_options[] = {
  45.         /* features */
  46. #if defined(R600_USE_LLVM)
  47.         { "llvm", DBG_LLVM, "Enable the LLVM shader compiler" },
  48. #endif
  49.         { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
  50.  
  51.         /* shader backend */
  52.         { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
  53.         { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
  54.         { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
  55.         { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
  56.         { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
  57.         { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
  58.         { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
  59.         { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
  60.  
  61.         DEBUG_NAMED_VALUE_END /* must be last */
  62. };
  63.  
  64. /*
  65.  * pipe_context
  66.  */
  67.  
  68. static void r600_destroy_context(struct pipe_context *context)
  69. {
  70.         struct r600_context *rctx = (struct r600_context *)context;
  71.  
  72.         r600_isa_destroy(rctx->isa);
  73.  
  74.         r600_sb_context_destroy(rctx->sb_context);
  75.  
  76.         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
  77.         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
  78.  
  79.         if (rctx->dummy_pixel_shader) {
  80.                 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
  81.         }
  82.         if (rctx->custom_dsa_flush) {
  83.                 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
  84.         }
  85.         if (rctx->custom_blend_resolve) {
  86.                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
  87.         }
  88.         if (rctx->custom_blend_decompress) {
  89.                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
  90.         }
  91.         if (rctx->custom_blend_fastclear) {
  92.                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
  93.         }
  94.         util_unreference_framebuffer_state(&rctx->framebuffer.state);
  95.  
  96.         if (rctx->blitter) {
  97.                 util_blitter_destroy(rctx->blitter);
  98.         }
  99.         if (rctx->allocator_fetch_shader) {
  100.                 u_suballocator_destroy(rctx->allocator_fetch_shader);
  101.         }
  102.  
  103.         r600_release_command_buffer(&rctx->start_cs_cmd);
  104.  
  105.         FREE(rctx->start_compute_cs_cmd.buf);
  106.  
  107.         r600_common_context_cleanup(&rctx->b);
  108.         FREE(rctx);
  109. }
  110.  
  111. static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
  112. {
  113.         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
  114.         struct r600_screen* rscreen = (struct r600_screen *)screen;
  115.         struct radeon_winsys *ws = rscreen->b.ws;
  116.  
  117.         if (rctx == NULL)
  118.                 return NULL;
  119.  
  120.         rctx->b.b.screen = screen;
  121.         rctx->b.b.priv = priv;
  122.         rctx->b.b.destroy = r600_destroy_context;
  123.  
  124.         if (!r600_common_context_init(&rctx->b, &rscreen->b))
  125.                 goto fail;
  126.  
  127.         rctx->screen = rscreen;
  128.         rctx->keep_tiling_flags = rscreen->b.info.drm_minor >= 12;
  129.  
  130.         r600_init_blit_functions(rctx);
  131.  
  132.         if (rscreen->b.info.has_uvd) {
  133.                 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
  134.                 rctx->b.b.create_video_buffer = r600_video_buffer_create;
  135.         } else {
  136.                 rctx->b.b.create_video_codec = vl_create_decoder;
  137.                 rctx->b.b.create_video_buffer = vl_video_buffer_create;
  138.         }
  139.  
  140.         r600_init_common_state_functions(rctx);
  141.  
  142.         switch (rctx->b.chip_class) {
  143.         case R600:
  144.         case R700:
  145.                 r600_init_state_functions(rctx);
  146.                 r600_init_atom_start_cs(rctx);
  147.                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
  148.                 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
  149.                                                                       : r600_create_resolve_blend(rctx);
  150.                 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
  151.                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
  152.                                            rctx->b.family == CHIP_RV620 ||
  153.                                            rctx->b.family == CHIP_RS780 ||
  154.                                            rctx->b.family == CHIP_RS880 ||
  155.                                            rctx->b.family == CHIP_RV710);
  156.                 break;
  157.         case EVERGREEN:
  158.         case CAYMAN:
  159.                 evergreen_init_state_functions(rctx);
  160.                 evergreen_init_atom_start_cs(rctx);
  161.                 evergreen_init_atom_start_compute_cs(rctx);
  162.                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
  163.                 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
  164.                 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
  165.                 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
  166.                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
  167.                                            rctx->b.family == CHIP_PALM ||
  168.                                            rctx->b.family == CHIP_SUMO ||
  169.                                            rctx->b.family == CHIP_SUMO2 ||
  170.                                            rctx->b.family == CHIP_CAICOS ||
  171.                                            rctx->b.family == CHIP_CAYMAN ||
  172.                                            rctx->b.family == CHIP_ARUBA);
  173.                 break;
  174.         default:
  175.                 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
  176.                 goto fail;
  177.         }
  178.  
  179.         rctx->b.rings.gfx.cs = ws->cs_create(ws, RING_GFX,
  180.                                              r600_context_gfx_flush, rctx,
  181.                                              rscreen->b.trace_bo ?
  182.                                                      rscreen->b.trace_bo->cs_buf : NULL);
  183.         rctx->b.rings.gfx.flush = r600_context_gfx_flush;
  184.  
  185.         rctx->allocator_fetch_shader = u_suballocator_create(&rctx->b.b, 64 * 1024, 256,
  186.                                                              0, PIPE_USAGE_DEFAULT, FALSE);
  187.         if (!rctx->allocator_fetch_shader)
  188.                 goto fail;
  189.  
  190.         rctx->isa = calloc(1, sizeof(struct r600_isa));
  191.         if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
  192.                 goto fail;
  193.  
  194.         if (rscreen->b.debug_flags & DBG_FORCE_DMA)
  195.                 rctx->b.b.resource_copy_region = rctx->b.dma_copy;
  196.  
  197.         rctx->blitter = util_blitter_create(&rctx->b.b);
  198.         if (rctx->blitter == NULL)
  199.                 goto fail;
  200.         util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
  201.         rctx->blitter->draw_rectangle = r600_draw_rectangle;
  202.  
  203.         r600_begin_new_cs(rctx);
  204.         r600_query_init_backend_mask(&rctx->b); /* this emits commands and must be last */
  205.  
  206.         rctx->dummy_pixel_shader =
  207.                 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
  208.                                                      TGSI_SEMANTIC_GENERIC,
  209.                                                      TGSI_INTERPOLATE_CONSTANT);
  210.         rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
  211.  
  212.         return &rctx->b.b;
  213.  
  214. fail:
  215.         r600_destroy_context(&rctx->b.b);
  216.         return NULL;
  217. }
  218.  
  219. /*
  220.  * pipe_screen
  221.  */
  222.  
  223. static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
  224. {
  225.         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
  226.         enum radeon_family family = rscreen->b.family;
  227.  
  228.         switch (param) {
  229.         /* Supported features (boolean caps). */
  230.         case PIPE_CAP_NPOT_TEXTURES:
  231.         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  232.         case PIPE_CAP_TWO_SIDED_STENCIL:
  233.         case PIPE_CAP_ANISOTROPIC_FILTER:
  234.         case PIPE_CAP_POINT_SPRITE:
  235.         case PIPE_CAP_OCCLUSION_QUERY:
  236.         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  237.         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  238.         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  239.         case PIPE_CAP_TEXTURE_SWIZZLE:
  240.         case PIPE_CAP_DEPTH_CLIP_DISABLE:
  241.         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  242.         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  243.         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  244.         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  245.         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  246.         case PIPE_CAP_SM3:
  247.         case PIPE_CAP_SEAMLESS_CUBE_MAP:
  248.         case PIPE_CAP_PRIMITIVE_RESTART:
  249.         case PIPE_CAP_CONDITIONAL_RENDER:
  250.         case PIPE_CAP_TEXTURE_BARRIER:
  251.         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  252.         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
  253.         case PIPE_CAP_TGSI_INSTANCEID:
  254.         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
  255.         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
  256.         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
  257.         case PIPE_CAP_USER_INDEX_BUFFERS:
  258.         case PIPE_CAP_USER_CONSTANT_BUFFERS:
  259.         case PIPE_CAP_START_INSTANCE:
  260.         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  261.         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  262.         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  263.         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
  264.         case PIPE_CAP_TEXTURE_MULTISAMPLE:
  265.         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  266.         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
  267.         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
  268.         case PIPE_CAP_SAMPLE_SHADING:
  269.         case PIPE_CAP_CLIP_HALFZ:
  270.         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
  271.                 return 1;
  272.  
  273.         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
  274.                 return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;
  275.  
  276.         case PIPE_CAP_COMPUTE:
  277.                 return rscreen->b.chip_class > R700;
  278.  
  279.         case PIPE_CAP_TGSI_TEXCOORD:
  280.                 return 0;
  281.  
  282.         case PIPE_CAP_FAKE_SW_MSAA:
  283.                 return 0;
  284.  
  285.         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
  286.                 return MIN2(rscreen->b.info.vram_size, 0xFFFFFFFF);
  287.  
  288.         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
  289.                 return R600_MAP_BUFFER_ALIGNMENT;
  290.  
  291.         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  292.                 return 256;
  293.  
  294.         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
  295.                 return 1;
  296.  
  297.         case PIPE_CAP_GLSL_FEATURE_LEVEL:
  298.                 if (family >= CHIP_CEDAR)
  299.                    return 330;
  300.                 /* pre-evergreen geom shaders need newer kernel */
  301.                 if (rscreen->b.info.drm_minor >= 37)
  302.                    return 330;
  303.                 return 140;
  304.  
  305.         /* Supported except the original R600. */
  306.         case PIPE_CAP_INDEP_BLEND_ENABLE:
  307.         case PIPE_CAP_INDEP_BLEND_FUNC:
  308.                 /* R600 doesn't support per-MRT blends */
  309.                 return family == CHIP_R600 ? 0 : 1;
  310.  
  311.         /* Supported on Evergreen. */
  312.         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  313.         case PIPE_CAP_CUBE_MAP_ARRAY:
  314.         case PIPE_CAP_TEXTURE_GATHER_SM5:
  315.         case PIPE_CAP_TEXTURE_QUERY_LOD:
  316.         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
  317.                 return family >= CHIP_CEDAR ? 1 : 0;
  318.         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
  319.                 return family >= CHIP_CEDAR ? 4 : 0;
  320.         case PIPE_CAP_DRAW_INDIRECT:
  321.                 /* kernel command checker support is also required */
  322.                 return family >= CHIP_CEDAR && rscreen->b.info.drm_minor >= 41;
  323.  
  324.         /* Unsupported features. */
  325.         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  326.         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  327.         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
  328.         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
  329.         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
  330.         case PIPE_CAP_USER_VERTEX_BUFFERS:
  331.         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
  332.         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
  333.         case PIPE_CAP_SAMPLER_VIEW_TARGET:
  334.         case PIPE_CAP_VERTEXID_NOBASE:
  335.         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
  336.                 return 0;
  337.  
  338.         /* Stream output. */
  339.         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
  340.                 return rscreen->b.has_streamout ? 4 : 0;
  341.         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
  342.                 return rscreen->b.has_streamout ? 1 : 0;
  343.         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
  344.         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
  345.                 return 32*4;
  346.  
  347.         /* Geometry shader output. */
  348.         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
  349.                 return 1024;
  350.         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
  351.                 return 16384;
  352.         case PIPE_CAP_MAX_VERTEX_STREAMS:
  353.                 return 1;
  354.  
  355.         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
  356.                 return 2047;
  357.  
  358.         /* Texturing. */
  359.         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  360.         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  361.                 if (family >= CHIP_CEDAR)
  362.                         return 15;
  363.                 else
  364.                         return 14;
  365.         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  366.                 /* textures support 8192, but layered rendering supports 2048 */
  367.                 return 12;
  368.         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  369.                 /* textures support 8192, but layered rendering supports 2048 */
  370.                 return rscreen->b.info.drm_minor >= 9 ? 2048 : 0;
  371.  
  372.         /* Render targets. */
  373.         case PIPE_CAP_MAX_RENDER_TARGETS:
  374.                 /* XXX some r6xx are buggy and can only do 4 */
  375.                 return 8;
  376.  
  377.         case PIPE_CAP_MAX_VIEWPORTS:
  378.                 return R600_MAX_VIEWPORTS;
  379.  
  380.         /* Timer queries, present when the clock frequency is non zero. */
  381.         case PIPE_CAP_QUERY_TIME_ELAPSED:
  382.                 return rscreen->b.info.r600_clock_crystal_freq != 0;
  383.         case PIPE_CAP_QUERY_TIMESTAMP:
  384.                 return rscreen->b.info.drm_minor >= 20 &&
  385.                        rscreen->b.info.r600_clock_crystal_freq != 0;
  386.  
  387.         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
  388.         case PIPE_CAP_MIN_TEXEL_OFFSET:
  389.                 return -8;
  390.  
  391.         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
  392.         case PIPE_CAP_MAX_TEXEL_OFFSET:
  393.                 return 7;
  394.  
  395.         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
  396.                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
  397.         case PIPE_CAP_ENDIANNESS:
  398.                 return PIPE_ENDIAN_LITTLE;
  399.  
  400.         case PIPE_CAP_VENDOR_ID:
  401.                 return 0x1002;
  402.         case PIPE_CAP_DEVICE_ID:
  403.                 return rscreen->b.info.pci_id;
  404.         case PIPE_CAP_ACCELERATED:
  405.                 return 1;
  406.         case PIPE_CAP_VIDEO_MEMORY:
  407.                 return rscreen->b.info.vram_size >> 20;
  408.         case PIPE_CAP_UMA:
  409.                 return 0;
  410.         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
  411.                 return rscreen->b.chip_class >= R700;
  412.         }
  413.         return 0;
  414. }
  415.  
  416. static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
  417. {
  418.         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
  419.  
  420.         switch(shader)
  421.         {
  422.         case PIPE_SHADER_FRAGMENT:
  423.         case PIPE_SHADER_VERTEX:
  424.         case PIPE_SHADER_COMPUTE:
  425.                 break;
  426.         case PIPE_SHADER_GEOMETRY:
  427.                 if (rscreen->b.family >= CHIP_CEDAR)
  428.                         break;
  429.                 /* pre-evergreen geom shaders need newer kernel */
  430.                 if (rscreen->b.info.drm_minor >= 37)
  431.                         break;
  432.                 return 0;
  433.         default:
  434.                 /* XXX: support tessellation on Evergreen */
  435.                 return 0;
  436.         }
  437.  
  438.         switch (param) {
  439.         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
  440.         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
  441.         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
  442.         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
  443.                 return 16384;
  444.         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
  445.                 return 32;
  446.         case PIPE_SHADER_CAP_MAX_INPUTS:
  447.                 return shader == PIPE_SHADER_VERTEX ? 16 : 32;
  448.         case PIPE_SHADER_CAP_MAX_OUTPUTS:
  449.                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
  450.         case PIPE_SHADER_CAP_MAX_TEMPS:
  451.                 return 256; /* Max native temporaries. */
  452.         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
  453.                 if (shader == PIPE_SHADER_COMPUTE) {
  454.                         uint64_t max_const_buffer_size;
  455.                         pscreen->get_compute_param(pscreen,
  456.                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
  457.                                 &max_const_buffer_size);
  458.                         return max_const_buffer_size;
  459.  
  460.                 } else {
  461.                         return R600_MAX_CONST_BUFFER_SIZE;
  462.                 }
  463.         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
  464.                 return R600_MAX_USER_CONST_BUFFERS;
  465.         case PIPE_SHADER_CAP_MAX_PREDS:
  466.                 return 0; /* nothing uses this */
  467.         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
  468.                 return 1;
  469.         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
  470.                 return 1;
  471.         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
  472.         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
  473.         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
  474.         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
  475.                 return 1;
  476.         case PIPE_SHADER_CAP_SUBROUTINES:
  477.                 return 0;
  478.         case PIPE_SHADER_CAP_INTEGERS:
  479.                 return 1;
  480.         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
  481.         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
  482.                 return 16;
  483.         case PIPE_SHADER_CAP_PREFERRED_IR:
  484.                 if (shader == PIPE_SHADER_COMPUTE) {
  485. #if HAVE_LLVM < 0x0306
  486.                         return PIPE_SHADER_IR_LLVM;
  487. #else
  488.                         return PIPE_SHADER_IR_NATIVE;
  489. #endif
  490.                 } else {
  491.                         return PIPE_SHADER_IR_TGSI;
  492.                 }
  493.         case PIPE_SHADER_CAP_DOUBLES:
  494.                 return 0;
  495.         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
  496.         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
  497.         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
  498.                 return 0;
  499.         }
  500.         return 0;
  501. }
  502.  
  503. static void r600_destroy_screen(struct pipe_screen* pscreen)
  504. {
  505.         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
  506.  
  507.         if (rscreen == NULL)
  508.                 return;
  509.  
  510.         if (!rscreen->b.ws->unref(rscreen->b.ws))
  511.                 return;
  512.  
  513.         if (rscreen->global_pool) {
  514.                 compute_memory_pool_delete(rscreen->global_pool);
  515.         }
  516.  
  517.         r600_destroy_common_screen(&rscreen->b);
  518. }
  519.  
  520. static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
  521.                                                   const struct pipe_resource *templ)
  522. {
  523.         if (templ->target == PIPE_BUFFER &&
  524.             (templ->bind & PIPE_BIND_GLOBAL))
  525.                 return r600_compute_global_buffer_create(screen, templ);
  526.  
  527.         return r600_resource_create_common(screen, templ);
  528. }
  529.  
  530. struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
  531. {
  532.         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
  533.  
  534.         if (rscreen == NULL) {
  535.                 return NULL;
  536.         }
  537.  
  538.         /* Set functions first. */
  539.         rscreen->b.b.context_create = r600_create_context;
  540.         rscreen->b.b.destroy = r600_destroy_screen;
  541.         rscreen->b.b.get_param = r600_get_param;
  542.         rscreen->b.b.get_shader_param = r600_get_shader_param;
  543.         rscreen->b.b.resource_create = r600_resource_create;
  544.  
  545.         if (!r600_common_screen_init(&rscreen->b, ws)) {
  546.                 FREE(rscreen);
  547.                 return NULL;
  548.         }
  549.  
  550.         if (rscreen->b.info.chip_class >= EVERGREEN) {
  551.                 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
  552.         } else {
  553.                 rscreen->b.b.is_format_supported = r600_is_format_supported;
  554.         }
  555.  
  556.         rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
  557.         if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
  558.                 rscreen->b.debug_flags |= DBG_COMPUTE;
  559.         if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
  560.                 rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
  561.         if (!debug_get_bool_option("R600_HYPERZ", TRUE))
  562.                 rscreen->b.debug_flags |= DBG_NO_HYPERZ;
  563.         if (debug_get_bool_option("R600_LLVM", FALSE))
  564.                 rscreen->b.debug_flags |= DBG_LLVM;
  565.  
  566.         if (rscreen->b.family == CHIP_UNKNOWN) {
  567.                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
  568.                 FREE(rscreen);
  569.                 return NULL;
  570.         }
  571.  
  572.         /* Figure out streamout kernel support. */
  573.         switch (rscreen->b.chip_class) {
  574.         case R600:
  575.                 if (rscreen->b.family < CHIP_RS780) {
  576.                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
  577.                 } else {
  578.                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
  579.                 }
  580.                 break;
  581.         case R700:
  582.                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
  583.                 break;
  584.         case EVERGREEN:
  585.         case CAYMAN:
  586.                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
  587.                 break;
  588.         default:
  589.                 rscreen->b.has_streamout = FALSE;
  590.                 break;
  591.         }
  592.  
  593.         /* MSAA support. */
  594.         switch (rscreen->b.chip_class) {
  595.         case R600:
  596.         case R700:
  597.                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
  598.                 rscreen->has_compressed_msaa_texturing = false;
  599.                 break;
  600.         case EVERGREEN:
  601.                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
  602.                 rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
  603.                 break;
  604.         case CAYMAN:
  605.                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
  606.                 rscreen->has_compressed_msaa_texturing = true;
  607.                 break;
  608.         default:
  609.                 rscreen->has_msaa = FALSE;
  610.                 rscreen->has_compressed_msaa_texturing = false;
  611.         }
  612.  
  613.         rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
  614.                               !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
  615.  
  616.         rscreen->global_pool = compute_memory_pool_new(rscreen);
  617.  
  618.         /* Create the auxiliary context. This must be done last. */
  619.         rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL);
  620.  
  621. #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
  622.         struct pipe_resource templ = {};
  623.  
  624.         templ.width0 = 4;
  625.         templ.height0 = 2048;
  626.         templ.depth0 = 1;
  627.         templ.array_size = 1;
  628.         templ.target = PIPE_TEXTURE_2D;
  629.         templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
  630.         templ.usage = PIPE_USAGE_DEFAULT;
  631.  
  632.         struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
  633.         unsigned char *map = ws->buffer_map(res->cs_buf, NULL, PIPE_TRANSFER_WRITE);
  634.  
  635.         memset(map, 0, 256);
  636.  
  637.         r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
  638.         r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
  639.         r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
  640.         r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
  641.         r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
  642.  
  643.         ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
  644.  
  645.         int i;
  646.         for (i = 0; i < 256; i++) {
  647.                 printf("%02X", map[i]);
  648.                 if (i % 16 == 15)
  649.                         printf("\n");
  650.         }
  651. #endif
  652.  
  653.         return &rscreen->b.b;
  654. }
  655.