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  1. /*
  2.  * Copyright 2010 Christoph Bumiller
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice shall be included in
  12.  * all copies or substantial portions of the Software.
  13.  *
  14.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20.  * OTHER DEALINGS IN THE SOFTWARE.
  21.  */
  22.  
  23. #define NVC0_PUSH_EXPLICIT_SPACE_CHECKING
  24.  
  25. #include "pipe/p_context.h"
  26. #include "pipe/p_state.h"
  27. #include "util/u_inlines.h"
  28. #include "util/u_format.h"
  29. #include "translate/translate.h"
  30.  
  31. #include "nvc0/nvc0_context.h"
  32. #include "nvc0/nvc0_resource.h"
  33.  
  34. #include "nvc0/nvc0_3d.xml.h"
  35.  
  36. void
  37. nvc0_vertex_state_delete(struct pipe_context *pipe,
  38.                          void *hwcso)
  39. {
  40.    struct nvc0_vertex_stateobj *so = hwcso;
  41.  
  42.    if (so->translate)
  43.       so->translate->release(so->translate);
  44.    FREE(hwcso);
  45. }
  46.  
  47. void *
  48. nvc0_vertex_state_create(struct pipe_context *pipe,
  49.                          unsigned num_elements,
  50.                          const struct pipe_vertex_element *elements)
  51. {
  52.     struct nvc0_vertex_stateobj *so;
  53.     struct translate_key transkey;
  54.     unsigned i;
  55.     unsigned src_offset_max = 0;
  56.  
  57.     so = MALLOC(sizeof(*so) +
  58.                 num_elements * sizeof(struct nvc0_vertex_element));
  59.     if (!so)
  60.         return NULL;
  61.     so->num_elements = num_elements;
  62.     so->instance_elts = 0;
  63.     so->instance_bufs = 0;
  64.     so->shared_slots = FALSE;
  65.     so->need_conversion = FALSE;
  66.  
  67.     memset(so->vb_access_size, 0, sizeof(so->vb_access_size));
  68.  
  69.     for (i = 0; i < PIPE_MAX_ATTRIBS; ++i)
  70.        so->min_instance_div[i] = 0xffffffff;
  71.  
  72.     transkey.nr_elements = 0;
  73.     transkey.output_stride = 0;
  74.  
  75.     for (i = 0; i < num_elements; ++i) {
  76.         const struct pipe_vertex_element *ve = &elements[i];
  77.         const unsigned vbi = ve->vertex_buffer_index;
  78.         unsigned size;
  79.         enum pipe_format fmt = ve->src_format;
  80.  
  81.         so->element[i].pipe = elements[i];
  82.         so->element[i].state = nvc0_format_table[fmt].vtx;
  83.  
  84.         if (!so->element[i].state) {
  85.             switch (util_format_get_nr_components(fmt)) {
  86.             case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
  87.             case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
  88.             case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
  89.             case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
  90.             default:
  91.                 assert(0);
  92.                 FREE(so);
  93.                 return NULL;
  94.             }
  95.             so->element[i].state = nvc0_format_table[fmt].vtx;
  96.             so->need_conversion = TRUE;
  97.         }
  98.         size = util_format_get_blocksize(fmt);
  99.  
  100.         src_offset_max = MAX2(src_offset_max, ve->src_offset);
  101.  
  102.         if (so->vb_access_size[vbi] < (ve->src_offset + size))
  103.            so->vb_access_size[vbi] = ve->src_offset + size;
  104.  
  105.         if (unlikely(ve->instance_divisor)) {
  106.            so->instance_elts |= 1 << i;
  107.            so->instance_bufs |= 1 << vbi;
  108.            if (ve->instance_divisor < so->min_instance_div[vbi])
  109.               so->min_instance_div[vbi] = ve->instance_divisor;
  110.         }
  111.  
  112.         if (1) {
  113.             unsigned ca;
  114.             unsigned j = transkey.nr_elements++;
  115.  
  116.             ca = util_format_description(fmt)->channel[0].size / 8;
  117.             if (ca != 1 && ca != 2)
  118.                ca = 4;
  119.  
  120.             transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
  121.             transkey.element[j].input_format = ve->src_format;
  122.             transkey.element[j].input_buffer = vbi;
  123.             transkey.element[j].input_offset = ve->src_offset;
  124.             transkey.element[j].instance_divisor = ve->instance_divisor;
  125.  
  126.             transkey.output_stride = align(transkey.output_stride, ca);
  127.             transkey.element[j].output_format = fmt;
  128.             transkey.element[j].output_offset = transkey.output_stride;
  129.             transkey.output_stride += size;
  130.  
  131.             so->element[i].state_alt = so->element[i].state;
  132.             so->element[i].state_alt |= transkey.element[j].output_offset << 7;
  133.         }
  134.  
  135.         so->element[i].state |= i << NVC0_3D_VERTEX_ATTRIB_FORMAT_BUFFER__SHIFT;
  136.     }
  137.     transkey.output_stride = align(transkey.output_stride, 4);
  138.  
  139.     so->size = transkey.output_stride;
  140.     so->translate = translate_create(&transkey);
  141.  
  142.     if (so->instance_elts || src_offset_max >= (1 << 14))
  143.        return so;
  144.     so->shared_slots = TRUE;
  145.  
  146.     for (i = 0; i < num_elements; ++i) {
  147.        const unsigned b = elements[i].vertex_buffer_index;
  148.        const unsigned s = elements[i].src_offset;
  149.        so->element[i].state &= ~NVC0_3D_VERTEX_ATTRIB_FORMAT_BUFFER__MASK;
  150.        so->element[i].state |= b << NVC0_3D_VERTEX_ATTRIB_FORMAT_BUFFER__SHIFT;
  151.        so->element[i].state |= s << NVC0_3D_VERTEX_ATTRIB_FORMAT_OFFSET__SHIFT;
  152.     }
  153.     return so;
  154. }
  155.  
  156. #define NVC0_3D_VERTEX_ATTRIB_INACTIVE                                       \
  157.    NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT |                                 \
  158.    NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32 | NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST
  159.  
  160. #define VTX_ATTR(a, c, t, s)                            \
  161.    ((NVC0_3D_VTX_ATTR_DEFINE_TYPE_##t) |                \
  162.     (NVC0_3D_VTX_ATTR_DEFINE_SIZE_##s) |                \
  163.     ((a) << NVC0_3D_VTX_ATTR_DEFINE_ATTR__SHIFT) |      \
  164.     ((c) << NVC0_3D_VTX_ATTR_DEFINE_COMP__SHIFT))
  165.  
  166. static void
  167. nvc0_set_constant_vertex_attrib(struct nvc0_context *nvc0, const unsigned a)
  168. {
  169.    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
  170.    struct pipe_vertex_element *ve = &nvc0->vertex->element[a].pipe;
  171.    struct pipe_vertex_buffer *vb = &nvc0->vtxbuf[ve->vertex_buffer_index];
  172.    uint32_t mode;
  173.    const struct util_format_description *desc;
  174.    void *dst;
  175.    const void *src = (const uint8_t *)vb->user_buffer + ve->src_offset;
  176.    assert(!vb->buffer);
  177.  
  178.    desc = util_format_description(ve->src_format);
  179.  
  180.    PUSH_SPACE(push, 6);
  181.    BEGIN_NVC0(push, NVC0_3D(VTX_ATTR_DEFINE), 5);
  182.    dst = &push->cur[1];
  183.    if (desc->channel[0].pure_integer) {
  184.       if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) {
  185.          mode = VTX_ATTR(a, 4, SINT, 32);
  186.          desc->unpack_rgba_sint(dst, 0, src, 0, 1, 1);
  187.       } else {
  188.          mode = VTX_ATTR(a, 4, UINT, 32);
  189.          desc->unpack_rgba_uint(dst, 0, src, 0, 1, 1);
  190.       }
  191.    } else {
  192.       mode = VTX_ATTR(a, 4, FLOAT, 32);
  193.       desc->unpack_rgba_float(dst, 0, src, 0, 1, 1);
  194.    }
  195.    push->cur[0] = mode;
  196.    push->cur += 5;
  197. }
  198.  
  199. static INLINE void
  200. nvc0_user_vbuf_range(struct nvc0_context *nvc0, int vbi,
  201.                      uint32_t *base, uint32_t *size)
  202. {
  203.    if (unlikely(nvc0->vertex->instance_bufs & (1 << vbi))) {
  204.       const uint32_t div = nvc0->vertex->min_instance_div[vbi];
  205.       *base = nvc0->instance_off * nvc0->vtxbuf[vbi].stride;
  206.       *size = (nvc0->instance_max / div) * nvc0->vtxbuf[vbi].stride +
  207.          nvc0->vertex->vb_access_size[vbi];
  208.    } else {
  209.       /* NOTE: if there are user buffers, we *must* have index bounds */
  210.       assert(nvc0->vb_elt_limit != ~0);
  211.       *base = nvc0->vb_elt_first * nvc0->vtxbuf[vbi].stride;
  212.       *size = nvc0->vb_elt_limit * nvc0->vtxbuf[vbi].stride +
  213.          nvc0->vertex->vb_access_size[vbi];
  214.    }
  215. }
  216.  
  217. static INLINE void
  218. nvc0_release_user_vbufs(struct nvc0_context *nvc0)
  219. {
  220.    if (nvc0->vbo_user) {
  221.       nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_VTX_TMP);
  222.       nouveau_scratch_done(&nvc0->base);
  223.    }
  224. }
  225.  
  226. static void
  227. nvc0_update_user_vbufs(struct nvc0_context *nvc0)
  228. {
  229.    uint64_t address[PIPE_MAX_ATTRIBS];
  230.    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
  231.    int i;
  232.    uint32_t written = 0;
  233.  
  234.    PUSH_SPACE(push, nvc0->vertex->num_elements * 8);
  235.    for (i = 0; i < nvc0->vertex->num_elements; ++i) {
  236.       struct pipe_vertex_element *ve = &nvc0->vertex->element[i].pipe;
  237.       const unsigned b = ve->vertex_buffer_index;
  238.       struct pipe_vertex_buffer *vb = &nvc0->vtxbuf[b];
  239.       uint32_t base, size;
  240.  
  241.       if (!(nvc0->vbo_user & (1 << b)))
  242.          continue;
  243.       if (nvc0->constant_vbos & (1 << b)) {
  244.          nvc0_set_constant_vertex_attrib(nvc0, i);
  245.          continue;
  246.       }
  247.       nvc0_user_vbuf_range(nvc0, b, &base, &size);
  248.  
  249.       if (!(written & (1 << b))) {
  250.          struct nouveau_bo *bo;
  251.          const uint32_t bo_flags = NOUVEAU_BO_RD | NOUVEAU_BO_GART;
  252.          written |= 1 << b;
  253.          address[b] = nouveau_scratch_data(&nvc0->base, vb->user_buffer,
  254.                                            base, size, &bo);
  255.          if (bo)
  256.             BCTX_REFN_bo(nvc0->bufctx_3d, VTX_TMP, bo_flags, bo);
  257.  
  258.          NOUVEAU_DRV_STAT(&nvc0->screen->base, user_buffer_upload_bytes, size);
  259.       }
  260.  
  261.       BEGIN_1IC0(push, NVC0_3D(MACRO_VERTEX_ARRAY_SELECT), 5);
  262.       PUSH_DATA (push, i);
  263.       PUSH_DATAh(push, address[b] + base + size - 1);
  264.       PUSH_DATA (push, address[b] + base + size - 1);
  265.       PUSH_DATAh(push, address[b] + ve->src_offset);
  266.       PUSH_DATA (push, address[b] + ve->src_offset);
  267.    }
  268.    nvc0->base.vbo_dirty = TRUE;
  269. }
  270.  
  271. static void
  272. nvc0_update_user_vbufs_shared(struct nvc0_context *nvc0)
  273. {
  274.    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
  275.    uint32_t mask = nvc0->vbo_user & ~nvc0->constant_vbos;
  276.  
  277.    PUSH_SPACE(push, nvc0->num_vtxbufs * 8);
  278.    while (mask) {
  279.       struct nouveau_bo *bo;
  280.       const uint32_t bo_flags = NOUVEAU_BO_RD | NOUVEAU_BO_GART;
  281.       uint64_t address;
  282.       uint32_t base, size;
  283.       const int b = ffs(mask) - 1;
  284.       mask &= ~(1 << b);
  285.  
  286.       nvc0_user_vbuf_range(nvc0, b, &base, &size);
  287.  
  288.       address = nouveau_scratch_data(&nvc0->base, nvc0->vtxbuf[b].user_buffer,
  289.                                      base, size, &bo);
  290.       if (bo)
  291.          BCTX_REFN_bo(nvc0->bufctx_3d, VTX_TMP, bo_flags, bo);
  292.  
  293.       BEGIN_1IC0(push, NVC0_3D(MACRO_VERTEX_ARRAY_SELECT), 5);
  294.       PUSH_DATA (push, b);
  295.       PUSH_DATAh(push, address + base + size - 1);
  296.       PUSH_DATA (push, address + base + size - 1);
  297.       PUSH_DATAh(push, address);
  298.       PUSH_DATA (push, address);
  299.  
  300.       NOUVEAU_DRV_STAT(&nvc0->screen->base, user_buffer_upload_bytes, size);
  301.    }
  302.  
  303.    mask = nvc0->state.constant_elts;
  304.    while (mask) {
  305.       int i = ffs(mask) - 1;
  306.       mask &= ~(1 << i);
  307.       nvc0_set_constant_vertex_attrib(nvc0, i);
  308.    }
  309. }
  310.  
  311. static void
  312. nvc0_validate_vertex_buffers(struct nvc0_context *nvc0)
  313. {
  314.    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
  315.    const struct nvc0_vertex_stateobj *vertex = nvc0->vertex;
  316.    uint32_t refd = 0;
  317.    unsigned i;
  318.  
  319.    PUSH_SPACE(push, vertex->num_elements * 8);
  320.    for (i = 0; i < vertex->num_elements; ++i) {
  321.       const struct nvc0_vertex_element *ve;
  322.       const struct pipe_vertex_buffer *vb;
  323.       struct nv04_resource *res;
  324.       unsigned b;
  325.       unsigned limit, offset;
  326.  
  327.       if (nvc0->state.constant_elts & (1 << i))
  328.          continue;
  329.       ve = &vertex->element[i];
  330.       b = ve->pipe.vertex_buffer_index;
  331.       vb = &nvc0->vtxbuf[b];
  332.  
  333.       if (!vb->buffer) {
  334.          if (!(nvc0->constant_vbos & (1 << b))) {
  335.             if (ve->pipe.instance_divisor) {
  336.                BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_DIVISOR(i)), 1);
  337.                PUSH_DATA (push, ve->pipe.instance_divisor);
  338.             }
  339.             BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 1);
  340.             PUSH_DATA (push, (1 << 12) | vb->stride);
  341.          }
  342.          /* address/value set in nvc0_update_user_vbufs */
  343.          continue;
  344.       }
  345.       res = nv04_resource(vb->buffer);
  346.       offset = ve->pipe.src_offset + vb->buffer_offset;
  347.       limit = vb->buffer->width0 - 1;
  348.  
  349.       if (unlikely(ve->pipe.instance_divisor)) {
  350.          BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 4);
  351.          PUSH_DATA (push, (1 << 12) | vb->stride);
  352.          PUSH_DATAh(push, res->address + offset);
  353.          PUSH_DATA (push, res->address + offset);
  354.          PUSH_DATA (push, ve->pipe.instance_divisor);
  355.       } else {
  356.          BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 3);
  357.          PUSH_DATA (push, (1 << 12) | vb->stride);
  358.          PUSH_DATAh(push, res->address + offset);
  359.          PUSH_DATA (push, res->address + offset);
  360.       }
  361.       BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
  362.       PUSH_DATAh(push, res->address + limit);
  363.       PUSH_DATA (push, res->address + limit);
  364.  
  365.       if (!(refd & (1 << b))) {
  366.          refd |= 1 << b;
  367.          BCTX_REFN(nvc0->bufctx_3d, VTX, res, RD);
  368.       }
  369.    }
  370.    if (nvc0->vbo_user)
  371.       nvc0_update_user_vbufs(nvc0);
  372. }
  373.  
  374. static void
  375. nvc0_validate_vertex_buffers_shared(struct nvc0_context *nvc0)
  376. {
  377.    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
  378.    unsigned b;
  379.    const uint32_t mask = nvc0->vbo_user;
  380.  
  381.    PUSH_SPACE(push, nvc0->num_vtxbufs * 8);
  382.    for (b = 0; b < nvc0->num_vtxbufs; ++b) {
  383.       struct pipe_vertex_buffer *vb = &nvc0->vtxbuf[b];
  384.       struct nv04_resource *buf;
  385.       uint32_t offset, limit;
  386.  
  387.       if (mask & (1 << b)) {
  388.          if (!(nvc0->constant_vbos & (1 << b))) {
  389.             BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(b)), 1);
  390.             PUSH_DATA (push, NVC0_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
  391.          }
  392.          /* address/value set in nvc0_update_user_vbufs_shared */
  393.          continue;
  394.       }
  395.       buf = nv04_resource(vb->buffer);
  396.       offset = vb->buffer_offset;
  397.       limit = buf->base.width0 - 1;
  398.  
  399.       BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(b)), 3);
  400.       PUSH_DATA (push, NVC0_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
  401.       PUSH_DATAh(push, buf->address + offset);
  402.       PUSH_DATA (push, buf->address + offset);
  403.       BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_LIMIT_HIGH(b)), 2);
  404.       PUSH_DATAh(push, buf->address + limit);
  405.       PUSH_DATA (push, buf->address + limit);
  406.  
  407.       BCTX_REFN(nvc0->bufctx_3d, VTX, buf, RD);
  408.    }
  409.    if (nvc0->vbo_user)
  410.       nvc0_update_user_vbufs_shared(nvc0);
  411. }
  412.  
  413. void
  414. nvc0_vertex_arrays_validate(struct nvc0_context *nvc0)
  415. {
  416.    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
  417.    struct nvc0_vertex_stateobj *vertex = nvc0->vertex;
  418.    struct nvc0_vertex_element *ve;
  419.    uint32_t const_vbos;
  420.    unsigned i;
  421.    uint8_t vbo_mode;
  422.    boolean update_vertex;
  423.  
  424.    nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_VTX);
  425.  
  426.    assert(vertex);
  427.    if (unlikely(vertex->need_conversion) ||
  428.        unlikely(nvc0->vertprog->vp.edgeflag < PIPE_MAX_ATTRIBS)) {
  429.       vbo_mode = 3;
  430.    } else {
  431.       vbo_mode = (nvc0->vbo_user && nvc0->vbo_push_hint) ? 1 : 0;
  432.    }
  433.    const_vbos = vbo_mode ? 0 : nvc0->constant_vbos;
  434.  
  435.    update_vertex = (nvc0->dirty & NVC0_NEW_VERTEX) ||
  436.       (const_vbos != nvc0->state.constant_vbos) ||
  437.       (vbo_mode != nvc0->state.vbo_mode);
  438.  
  439.    if (update_vertex) {
  440.       const unsigned n = MAX2(vertex->num_elements, nvc0->state.num_vtxelts);
  441.  
  442.       nvc0->state.constant_vbos = const_vbos;
  443.       nvc0->state.constant_elts = 0;
  444.       nvc0->state.num_vtxelts = vertex->num_elements;
  445.       nvc0->state.vbo_mode = vbo_mode;
  446.  
  447.       if (unlikely(vbo_mode)) {
  448.          if (unlikely(nvc0->state.instance_elts & 3)) {
  449.             /* translate mode uses only 2 vertex buffers */
  450.             nvc0->state.instance_elts &= ~3;
  451.             PUSH_SPACE(push, 3);
  452.             BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_PER_INSTANCE(0)), 2);
  453.             PUSH_DATA (push, 0);
  454.             PUSH_DATA (push, 0);
  455.          }
  456.  
  457.          PUSH_SPACE(push, n * 2 + 4);
  458.  
  459.          BEGIN_NVC0(push, NVC0_3D(VERTEX_ATTRIB_FORMAT(0)), n);
  460.          for (i = 0; i < vertex->num_elements; ++i)
  461.             PUSH_DATA(push, vertex->element[i].state_alt);
  462.          for (; i < n; ++i)
  463.             PUSH_DATA(push, NVC0_3D_VERTEX_ATTRIB_INACTIVE);
  464.  
  465.          BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(0)), 1);
  466.          PUSH_DATA (push, (1 << 12) | vertex->size);
  467.          for (i = 1; i < n; ++i)
  468.             IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 0);
  469.       } else {
  470.          uint32_t *restrict data;
  471.  
  472.          if (unlikely(vertex->instance_elts != nvc0->state.instance_elts)) {
  473.             nvc0->state.instance_elts = vertex->instance_elts;
  474.             assert(n); /* if (n == 0), both masks should be 0 */
  475.             PUSH_SPACE(push, 3);
  476.             BEGIN_NVC0(push, NVC0_3D(MACRO_VERTEX_ARRAY_PER_INSTANCE), 2);
  477.             PUSH_DATA (push, n);
  478.             PUSH_DATA (push, vertex->instance_elts);
  479.          }
  480.  
  481.          PUSH_SPACE(push, n * 2 + 1);
  482.          BEGIN_NVC0(push, NVC0_3D(VERTEX_ATTRIB_FORMAT(0)), n);
  483.          data = push->cur;
  484.          push->cur += n;
  485.          for (i = 0; i < vertex->num_elements; ++i) {
  486.             ve = &vertex->element[i];
  487.             data[i] = ve->state;
  488.             if (unlikely(const_vbos & (1 << ve->pipe.vertex_buffer_index))) {
  489.                nvc0->state.constant_elts |= 1 << i;
  490.                data[i] |= NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST;
  491.                IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 0);
  492.             }
  493.          }
  494.          for (; i < n; ++i) {
  495.             data[i] = NVC0_3D_VERTEX_ATTRIB_INACTIVE;
  496.             IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 0);
  497.          }
  498.       }
  499.    }
  500.    if (nvc0->state.vbo_mode) /* using translate, don't set up arrays here */
  501.       return;
  502.  
  503.    if (vertex->shared_slots)
  504.       nvc0_validate_vertex_buffers_shared(nvc0);
  505.    else
  506.       nvc0_validate_vertex_buffers(nvc0);
  507. }
  508.  
  509. void
  510. nvc0_idxbuf_validate(struct nvc0_context *nvc0)
  511. {
  512.    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
  513.    struct nv04_resource *buf = nv04_resource(nvc0->idxbuf.buffer);
  514.  
  515.    assert(buf);
  516.    assert(nouveau_resource_mapped_by_gpu(&buf->base));
  517.  
  518.    PUSH_SPACE(push, 6);
  519.    BEGIN_NVC0(push, NVC0_3D(INDEX_ARRAY_START_HIGH), 5);
  520.    PUSH_DATAh(push, buf->address + nvc0->idxbuf.offset);
  521.    PUSH_DATA (push, buf->address + nvc0->idxbuf.offset);
  522.    PUSH_DATAh(push, buf->address + buf->base.width0 - 1);
  523.    PUSH_DATA (push, buf->address + buf->base.width0 - 1);
  524.    PUSH_DATA (push, nvc0->idxbuf.index_size >> 1);
  525.  
  526.    BCTX_REFN(nvc0->bufctx_3d, IDX, buf, RD);
  527. }
  528.  
  529. #define NVC0_PRIM_GL_CASE(n) \
  530.    case PIPE_PRIM_##n: return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
  531.  
  532. static INLINE unsigned
  533. nvc0_prim_gl(unsigned prim)
  534. {
  535.    switch (prim) {
  536.    NVC0_PRIM_GL_CASE(POINTS);
  537.    NVC0_PRIM_GL_CASE(LINES);
  538.    NVC0_PRIM_GL_CASE(LINE_LOOP);
  539.    NVC0_PRIM_GL_CASE(LINE_STRIP);
  540.    NVC0_PRIM_GL_CASE(TRIANGLES);
  541.    NVC0_PRIM_GL_CASE(TRIANGLE_STRIP);
  542.    NVC0_PRIM_GL_CASE(TRIANGLE_FAN);
  543.    NVC0_PRIM_GL_CASE(QUADS);
  544.    NVC0_PRIM_GL_CASE(QUAD_STRIP);
  545.    NVC0_PRIM_GL_CASE(POLYGON);
  546.    NVC0_PRIM_GL_CASE(LINES_ADJACENCY);
  547.    NVC0_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
  548.    NVC0_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
  549.    NVC0_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
  550.    /*
  551.    NVC0_PRIM_GL_CASE(PATCHES); */
  552.    default:
  553.       return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
  554.    }
  555. }
  556.  
  557. static void
  558. nvc0_draw_vbo_kick_notify(struct nouveau_pushbuf *push)
  559. {
  560.    struct nvc0_screen *screen = push->user_priv;
  561.  
  562.    nouveau_fence_update(&screen->base, TRUE);
  563.  
  564.    NOUVEAU_DRV_STAT(&screen->base, pushbuf_count, 1);
  565. }
  566.  
  567. static void
  568. nvc0_draw_arrays(struct nvc0_context *nvc0,
  569.                  unsigned mode, unsigned start, unsigned count,
  570.                  unsigned instance_count)
  571. {
  572.    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
  573.    unsigned prim;
  574.  
  575.    if (nvc0->state.index_bias) {
  576.       /* index_bias is implied 0 if !info->indexed (really ?) */
  577.       /* TODO: can we deactivate it for the VERTEX_BUFFER_FIRST command ? */
  578.       PUSH_SPACE(push, 2);
  579.       IMMED_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 0);
  580.       IMMED_NVC0(push, NVC0_3D(VERTEX_ID_BASE), 0);
  581.       nvc0->state.index_bias = 0;
  582.    }
  583.  
  584.    prim = nvc0_prim_gl(mode);
  585.  
  586.    while (instance_count--) {
  587.       PUSH_SPACE(push, 6);
  588.       BEGIN_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), 1);
  589.       PUSH_DATA (push, prim);
  590.       BEGIN_NVC0(push, NVC0_3D(VERTEX_BUFFER_FIRST), 2);
  591.       PUSH_DATA (push, start);
  592.       PUSH_DATA (push, count);
  593.       IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
  594.  
  595.       prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
  596.    }
  597.    NOUVEAU_DRV_STAT(&nvc0->screen->base, draw_calls_array, 1);
  598. }
  599.  
  600. static void
  601. nvc0_draw_elements_inline_u08(struct nouveau_pushbuf *push, const uint8_t *map,
  602.                               unsigned start, unsigned count)
  603. {
  604.    map += start;
  605.  
  606.    if (count & 3) {
  607.       unsigned i;
  608.       PUSH_SPACE(push, 4);
  609.       BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U32), count & 3);
  610.       for (i = 0; i < (count & 3); ++i)
  611.          PUSH_DATA(push, *map++);
  612.       count &= ~3;
  613.    }
  614.    while (count) {
  615.       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
  616.  
  617.       PUSH_SPACE(push, nr + 1);
  618.       BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U8), nr);
  619.       for (i = 0; i < nr; ++i) {
  620.          PUSH_DATA(push,
  621.                   (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
  622.          map += 4;
  623.       }
  624.       count -= nr * 4;
  625.    }
  626. }
  627.  
  628. static void
  629. nvc0_draw_elements_inline_u16(struct nouveau_pushbuf *push, const uint16_t *map,
  630.                               unsigned start, unsigned count)
  631. {
  632.    map += start;
  633.  
  634.    if (count & 1) {
  635.       count &= ~1;
  636.       PUSH_SPACE(push, 2);
  637.       BEGIN_NVC0(push, NVC0_3D(VB_ELEMENT_U32), 1);
  638.       PUSH_DATA (push, *map++);
  639.    }
  640.    while (count) {
  641.       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
  642.  
  643.       PUSH_SPACE(push, nr + 1);
  644.       BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U16), nr);
  645.       for (i = 0; i < nr; ++i) {
  646.          PUSH_DATA(push, (map[1] << 16) | map[0]);
  647.          map += 2;
  648.       }
  649.       count -= nr * 2;
  650.    }
  651. }
  652.  
  653. static void
  654. nvc0_draw_elements_inline_u32(struct nouveau_pushbuf *push, const uint32_t *map,
  655.                               unsigned start, unsigned count)
  656. {
  657.    map += start;
  658.  
  659.    while (count) {
  660.       const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
  661.  
  662.       PUSH_SPACE(push, nr + 1);
  663.       BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U32), nr);
  664.       PUSH_DATAp(push, map, nr);
  665.  
  666.       map += nr;
  667.       count -= nr;
  668.    }
  669. }
  670.  
  671. static void
  672. nvc0_draw_elements_inline_u32_short(struct nouveau_pushbuf *push,
  673.                                     const uint32_t *map,
  674.                                     unsigned start, unsigned count)
  675. {
  676.    map += start;
  677.  
  678.    if (count & 1) {
  679.       count--;
  680.       PUSH_SPACE(push, 1);
  681.       BEGIN_NVC0(push, NVC0_3D(VB_ELEMENT_U32), 1);
  682.       PUSH_DATA (push, *map++);
  683.    }
  684.    while (count) {
  685.       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
  686.  
  687.       PUSH_SPACE(push, nr + 1);
  688.       BEGIN_NIC0(push, NVC0_3D(VB_ELEMENT_U16), nr);
  689.       for (i = 0; i < nr; ++i) {
  690.          PUSH_DATA(push, (map[1] << 16) | map[0]);
  691.          map += 2;
  692.       }
  693.       count -= nr * 2;
  694.    }
  695. }
  696.  
  697. static void
  698. nvc0_draw_elements(struct nvc0_context *nvc0, boolean shorten,
  699.                    unsigned mode, unsigned start, unsigned count,
  700.                    unsigned instance_count, int32_t index_bias)
  701. {
  702.    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
  703.    unsigned prim;
  704.    const unsigned index_size = nvc0->idxbuf.index_size;
  705.  
  706.    prim = nvc0_prim_gl(mode);
  707.  
  708.    if (index_bias != nvc0->state.index_bias) {
  709.       PUSH_SPACE(push, 4);
  710.       BEGIN_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 1);
  711.       PUSH_DATA (push, index_bias);
  712.       BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_BASE), 1);
  713.       PUSH_DATA (push, index_bias);
  714.       nvc0->state.index_bias = index_bias;
  715.    }
  716.  
  717.    if (nvc0->idxbuf.buffer) {
  718.       PUSH_SPACE(push, 1);
  719.       IMMED_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), prim);
  720.       do {
  721.          PUSH_SPACE(push, 7);
  722.          BEGIN_NVC0(push, NVC0_3D(INDEX_BATCH_FIRST), 2);
  723.          PUSH_DATA (push, start);
  724.          PUSH_DATA (push, count);
  725.          if (--instance_count) {
  726.             BEGIN_NVC0(push, NVC0_3D(VERTEX_END_GL), 2);
  727.             PUSH_DATA (push, 0);
  728.             PUSH_DATA (push, prim | NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT);
  729.          }
  730.       } while (instance_count);
  731.       IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
  732.    } else {
  733.       const void *data = nvc0->idxbuf.user_buffer;
  734.  
  735.       while (instance_count--) {
  736.          PUSH_SPACE(push, 2);
  737.          BEGIN_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), 1);
  738.          PUSH_DATA (push, prim);
  739.          switch (index_size) {
  740.          case 1:
  741.             nvc0_draw_elements_inline_u08(push, data, start, count);
  742.             break;
  743.          case 2:
  744.             nvc0_draw_elements_inline_u16(push, data, start, count);
  745.             break;
  746.          case 4:
  747.             if (shorten)
  748.                nvc0_draw_elements_inline_u32_short(push, data, start, count);
  749.             else
  750.                nvc0_draw_elements_inline_u32(push, data, start, count);
  751.             break;
  752.          default:
  753.             assert(0);
  754.             return;
  755.          }
  756.          PUSH_SPACE(push, 1);
  757.          IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
  758.  
  759.          prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
  760.       }
  761.    }
  762.    NOUVEAU_DRV_STAT(&nvc0->screen->base, draw_calls_indexed, 1);
  763. }
  764.  
  765. static void
  766. nvc0_draw_stream_output(struct nvc0_context *nvc0,
  767.                         const struct pipe_draw_info *info)
  768. {
  769.    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
  770.    struct nvc0_so_target *so = nvc0_so_target(info->count_from_stream_output);
  771.    struct nv04_resource *res = nv04_resource(so->pipe.buffer);
  772.    unsigned mode = nvc0_prim_gl(info->mode);
  773.    unsigned num_instances = info->instance_count;
  774.  
  775.    if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
  776.       res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
  777.       PUSH_SPACE(push, 2);
  778.       IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
  779.       nvc0_query_fifo_wait(push, so->pq);
  780.       if (nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
  781.          IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FLUSH), 0);
  782.  
  783.       NOUVEAU_DRV_STAT(&nvc0->screen->base, gpu_serialize_count, 1);
  784.    }
  785.  
  786.    while (num_instances--) {
  787.       PUSH_SPACE(push, 8);
  788.       BEGIN_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), 1);
  789.       PUSH_DATA (push, mode);
  790.       BEGIN_NVC0(push, NVC0_3D(DRAW_TFB_BASE), 1);
  791.       PUSH_DATA (push, 0);
  792.       BEGIN_NVC0(push, NVC0_3D(DRAW_TFB_STRIDE), 1);
  793.       PUSH_DATA (push, so->stride);
  794.       BEGIN_NVC0(push, NVC0_3D(DRAW_TFB_BYTES), 1);
  795.       nvc0_query_pushbuf_submit(push, so->pq, 0x4);
  796.       IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0);
  797.  
  798.       mode |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
  799.    }
  800. }
  801.  
  802. static void
  803. nvc0_draw_indirect(struct nvc0_context *nvc0, const struct pipe_draw_info *info)
  804. {
  805.    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
  806.    struct nv04_resource *buf = nv04_resource(info->indirect);
  807.    unsigned size;
  808.    const uint32_t offset = buf->offset + info->indirect_offset;
  809.  
  810.    /* must make FIFO wait for engines idle before continuing to process */
  811.    if (buf->fence_wr && !nouveau_fence_signalled(buf->fence_wr))
  812.       IMMED_NVC0(push, SUBC_3D(NV10_SUBCHAN_REF_CNT), 0);
  813.  
  814.    PUSH_SPACE(push, 8);
  815.    if (info->indexed) {
  816.       assert(nvc0->idxbuf.buffer);
  817.       assert(nouveau_resource_mapped_by_gpu(nvc0->idxbuf.buffer));
  818.       size = 5 * 4;
  819.       BEGIN_1IC0(push, NVC0_3D(MACRO_DRAW_ELEMENTS_INDIRECT), 1 + size / 4);
  820.    } else {
  821.       if (nvc0->state.index_bias) {
  822.          /* index_bias is implied 0 if !info->indexed (really ?) */
  823.          IMMED_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 0);
  824.          IMMED_NVC0(push, NVC0_3D(VERTEX_ID_BASE), 0);
  825.          nvc0->state.index_bias = 0;
  826.       }
  827.       size = 4 * 4;
  828.       BEGIN_1IC0(push, NVC0_3D(MACRO_DRAW_ARRAYS_INDIRECT), 1 + size / 4);
  829.    }
  830.    PUSH_DATA(push, nvc0_prim_gl(info->mode));
  831. #define NVC0_IB_ENTRY_1_NO_PREFETCH (1 << (31 - 8))
  832.    nouveau_pushbuf_space(push, 0, 0, 1);
  833.    nouveau_pushbuf_data(push,
  834.                         buf->bo, offset, NVC0_IB_ENTRY_1_NO_PREFETCH | size);
  835. }
  836.  
  837. static INLINE void
  838. nvc0_update_prim_restart(struct nvc0_context *nvc0, boolean en, uint32_t index)
  839. {
  840.    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
  841.  
  842.    if (en != nvc0->state.prim_restart) {
  843.       if (en) {
  844.          BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_ENABLE), 2);
  845.          PUSH_DATA (push, 1);
  846.          PUSH_DATA (push, index);
  847.       } else {
  848.          IMMED_NVC0(push, NVC0_3D(PRIM_RESTART_ENABLE), 0);
  849.       }
  850.       nvc0->state.prim_restart = en;
  851.    } else
  852.    if (en) {
  853.       BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_INDEX), 1);
  854.       PUSH_DATA (push, index);
  855.    }
  856. }
  857.  
  858. void
  859. nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
  860. {
  861.    struct nvc0_context *nvc0 = nvc0_context(pipe);
  862.    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
  863.    int i, s;
  864.  
  865.    /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */
  866.    nvc0->vb_elt_first = info->min_index + info->index_bias;
  867.    nvc0->vb_elt_limit = info->max_index - info->min_index;
  868.    nvc0->instance_off = info->start_instance;
  869.    nvc0->instance_max = info->instance_count - 1;
  870.  
  871.    /* For picking only a few vertices from a large user buffer, push is better,
  872.     * if index count is larger and we expect repeated vertices, suggest upload.
  873.     */
  874.    nvc0->vbo_push_hint =
  875.       info->indexed && (nvc0->vb_elt_limit >= (info->count * 2));
  876.  
  877.    /* Check whether we want to switch vertex-submission mode. */
  878.    if (nvc0->vbo_user && !(nvc0->dirty & (NVC0_NEW_ARRAYS | NVC0_NEW_VERTEX))) {
  879.       if (nvc0->vbo_push_hint != !!nvc0->state.vbo_mode)
  880.          if (nvc0->state.vbo_mode != 3)
  881.             nvc0->dirty |= NVC0_NEW_ARRAYS;
  882.  
  883.       if (!(nvc0->dirty & NVC0_NEW_ARRAYS) && nvc0->state.vbo_mode == 0) {
  884.          if (nvc0->vertex->shared_slots)
  885.             nvc0_update_user_vbufs_shared(nvc0);
  886.          else
  887.             nvc0_update_user_vbufs(nvc0);
  888.       }
  889.    }
  890.  
  891.    /* 8 as minimum to avoid immediate double validation of new buffers */
  892.    nvc0_state_validate(nvc0, ~0, 8);
  893.  
  894.    push->kick_notify = nvc0_draw_vbo_kick_notify;
  895.  
  896.    for (s = 0; s < 5 && !nvc0->cb_dirty; ++s) {
  897.       uint32_t valid = nvc0->constbuf_valid[s];
  898.  
  899.       while (valid && !nvc0->cb_dirty) {
  900.          const unsigned i = ffs(valid) - 1;
  901.          struct pipe_resource *res;
  902.  
  903.          valid &= ~(1 << i);
  904.          if (nvc0->constbuf[s][i].user)
  905.             continue;
  906.  
  907.          res = nvc0->constbuf[s][i].u.buf;
  908.          if (!res)
  909.             continue;
  910.  
  911.          if (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
  912.             nvc0->cb_dirty = TRUE;
  913.       }
  914.    }
  915.  
  916.    if (nvc0->cb_dirty) {
  917.       IMMED_NVC0(push, NVC0_3D(MEM_BARRIER), 0x1011);
  918.       nvc0->cb_dirty = FALSE;
  919.    }
  920.  
  921.    if (nvc0->state.vbo_mode) {
  922.       nvc0_push_vbo(nvc0, info);
  923.       push->kick_notify = nvc0_default_kick_notify;
  924.       nouveau_pushbuf_bufctx(push, NULL);
  925.       return;
  926.    }
  927.  
  928.    /* space for base instance, flush, and prim restart */
  929.    PUSH_SPACE(push, 8);
  930.  
  931.    if (nvc0->state.instance_base != info->start_instance) {
  932.       nvc0->state.instance_base = info->start_instance;
  933.       /* NOTE: this does not affect the shader input, should it ? */
  934.       BEGIN_NVC0(push, NVC0_3D(VB_INSTANCE_BASE), 1);
  935.       PUSH_DATA (push, info->start_instance);
  936.    }
  937.  
  938.    for (i = 0; i < nvc0->num_vtxbufs && !nvc0->base.vbo_dirty; ++i) {
  939.       if (!nvc0->vtxbuf[i].buffer)
  940.          continue;
  941.       if (nvc0->vtxbuf[i].buffer->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
  942.          nvc0->base.vbo_dirty = TRUE;
  943.    }
  944.  
  945.    if (!nvc0->base.vbo_dirty && nvc0->idxbuf.buffer &&
  946.        nvc0->idxbuf.buffer->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
  947.       nvc0->base.vbo_dirty = TRUE;
  948.  
  949.    nvc0_update_prim_restart(nvc0, info->primitive_restart, info->restart_index);
  950.  
  951.    if (nvc0->base.vbo_dirty) {
  952.       if (nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
  953.          IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FLUSH), 0);
  954.       nvc0->base.vbo_dirty = FALSE;
  955.    }
  956.  
  957.    if (unlikely(info->indirect)) {
  958.       nvc0_draw_indirect(nvc0, info);
  959.    } else
  960.    if (unlikely(info->count_from_stream_output)) {
  961.       nvc0_draw_stream_output(nvc0, info);
  962.    } else
  963.    if (info->indexed) {
  964.       boolean shorten = info->max_index <= 65535;
  965.  
  966.       if (info->primitive_restart && info->restart_index > 65535)
  967.          shorten = FALSE;
  968.  
  969.       nvc0_draw_elements(nvc0, shorten,
  970.                          info->mode, info->start, info->count,
  971.                          info->instance_count, info->index_bias);
  972.    } else {
  973.       nvc0_draw_arrays(nvc0,
  974.                        info->mode, info->start, info->count,
  975.                        info->instance_count);
  976.    }
  977.    push->kick_notify = nvc0_default_kick_notify;
  978.  
  979.    nvc0_release_user_vbufs(nvc0);
  980.  
  981.    nouveau_pushbuf_bufctx(push, NULL);
  982. }
  983.