Subversion Repositories Kolibri OS

Rev

Blame | Last modification | View Log | RSS feed

  1. /*
  2.  * Copyright 2010 Christoph Bumiller
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice shall be included in
  12.  * all copies or substantial portions of the Software.
  13.  *
  14.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20.  * OTHER DEALINGS IN THE SOFTWARE.
  21.  */
  22.  
  23. #include <xf86drm.h>
  24. #include <nouveau_drm.h>
  25. #include "util/u_format.h"
  26. #include "util/u_format_s3tc.h"
  27. #include "pipe/p_screen.h"
  28.  
  29. #include "vl/vl_decoder.h"
  30. #include "vl/vl_video_buffer.h"
  31.  
  32. #include "nouveau_vp3_video.h"
  33.  
  34. #include "nvc0/nvc0_context.h"
  35. #include "nvc0/nvc0_screen.h"
  36.  
  37. #include "nvc0/mme/com9097.mme.h"
  38.  
  39. static boolean
  40. nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
  41.                                 enum pipe_format format,
  42.                                 enum pipe_texture_target target,
  43.                                 unsigned sample_count,
  44.                                 unsigned bindings)
  45. {
  46.    if (sample_count > 8)
  47.       return FALSE;
  48.    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  49.       return FALSE;
  50.  
  51.    if (!util_format_is_supported(format, bindings))
  52.       return FALSE;
  53.  
  54.    if ((bindings & PIPE_BIND_SAMPLER_VIEW) && (target != PIPE_BUFFER))
  55.       if (util_format_get_blocksizebits(format) == 3 * 32)
  56.          return FALSE;
  57.  
  58.    /* transfers & shared are always supported */
  59.    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  60.                  PIPE_BIND_TRANSFER_WRITE |
  61.                  PIPE_BIND_SHARED);
  62.  
  63.    return (nvc0_format_table[format].usage & bindings) == bindings;
  64. }
  65.  
  66. static int
  67. nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  68. {
  69.    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  70.    struct nouveau_device *dev = nouveau_screen(pscreen)->device;
  71.  
  72.    switch (param) {
  73.    /* non-boolean caps */
  74.    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  75.    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  76.       return 15;
  77.    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  78.       return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
  79.    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  80.       return 2048;
  81.    case PIPE_CAP_MIN_TEXEL_OFFSET:
  82.       return -8;
  83.    case PIPE_CAP_MAX_TEXEL_OFFSET:
  84.       return 7;
  85.    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
  86.       return -32;
  87.    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
  88.       return 31;
  89.    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
  90.       return 65536;
  91.    case PIPE_CAP_GLSL_FEATURE_LEVEL:
  92.       return 410;
  93.    case PIPE_CAP_MAX_RENDER_TARGETS:
  94.       return 8;
  95.    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
  96.       return 1;
  97.    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
  98.       return 4;
  99.    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
  100.    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
  101.       return 128;
  102.    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
  103.    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
  104.       return 1024;
  105.    case PIPE_CAP_MAX_VERTEX_STREAMS:
  106.       return 4;
  107.    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
  108.       return 2048;
  109.    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
  110.       return 256;
  111.    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
  112.       return 1; /* 256 for binding as RT, but that's not possible in GL */
  113.    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
  114.       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
  115.    case PIPE_CAP_MAX_VIEWPORTS:
  116.       return NVC0_MAX_VIEWPORTS;
  117.    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
  118.       return 4;
  119.    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
  120.       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
  121.    case PIPE_CAP_ENDIANNESS:
  122.       return PIPE_ENDIAN_LITTLE;
  123.  
  124.    /* supported caps */
  125.    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  126.    case PIPE_CAP_TEXTURE_SWIZZLE:
  127.    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  128.    case PIPE_CAP_NPOT_TEXTURES:
  129.    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  130.    case PIPE_CAP_ANISOTROPIC_FILTER:
  131.    case PIPE_CAP_SEAMLESS_CUBE_MAP:
  132.    case PIPE_CAP_CUBE_MAP_ARRAY:
  133.    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
  134.    case PIPE_CAP_TEXTURE_MULTISAMPLE:
  135.    case PIPE_CAP_TWO_SIDED_STENCIL:
  136.    case PIPE_CAP_DEPTH_CLIP_DISABLE:
  137.    case PIPE_CAP_POINT_SPRITE:
  138.    case PIPE_CAP_TGSI_TEXCOORD:
  139.    case PIPE_CAP_SM3:
  140.    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
  141.    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  142.    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
  143.    case PIPE_CAP_QUERY_TIMESTAMP:
  144.    case PIPE_CAP_QUERY_TIME_ELAPSED:
  145.    case PIPE_CAP_OCCLUSION_QUERY:
  146.    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
  147.    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
  148.    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  149.    case PIPE_CAP_INDEP_BLEND_ENABLE:
  150.    case PIPE_CAP_INDEP_BLEND_FUNC:
  151.    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  152.    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  153.    case PIPE_CAP_PRIMITIVE_RESTART:
  154.    case PIPE_CAP_TGSI_INSTANCEID:
  155.    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  156.    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  157.    case PIPE_CAP_CONDITIONAL_RENDER:
  158.    case PIPE_CAP_TEXTURE_BARRIER:
  159.    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
  160.    case PIPE_CAP_START_INSTANCE:
  161.    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
  162.    case PIPE_CAP_DRAW_INDIRECT:
  163.    case PIPE_CAP_USER_CONSTANT_BUFFERS:
  164.    case PIPE_CAP_USER_INDEX_BUFFERS:
  165.    case PIPE_CAP_USER_VERTEX_BUFFERS:
  166.    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
  167.    case PIPE_CAP_TEXTURE_QUERY_LOD:
  168.    case PIPE_CAP_SAMPLE_SHADING:
  169.    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
  170.    case PIPE_CAP_TEXTURE_GATHER_SM5:
  171.    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
  172.    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
  173.    case PIPE_CAP_SAMPLER_VIEW_TARGET:
  174.    case PIPE_CAP_CLIP_HALFZ:
  175.    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
  176.    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
  177.       return 1;
  178.    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  179.       return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
  180.    case PIPE_CAP_COMPUTE:
  181.       return (class_3d == NVE4_3D_CLASS) ? 1 : 0;
  182.  
  183.    /* unsupported caps */
  184.    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  185.    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  186.    case PIPE_CAP_SHADER_STENCIL_EXPORT:
  187.    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
  188.    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
  189.    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
  190.    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
  191.    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
  192.    case PIPE_CAP_FAKE_SW_MSAA:
  193.    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
  194.    case PIPE_CAP_VERTEXID_NOBASE:
  195.    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
  196.    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
  197.       return 0;
  198.  
  199.    case PIPE_CAP_VENDOR_ID:
  200.       return 0x10de;
  201.    case PIPE_CAP_DEVICE_ID: {
  202.       uint64_t device_id;
  203.       if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
  204.          NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
  205.          return -1;
  206.       }
  207.       return device_id;
  208.    }
  209.    case PIPE_CAP_ACCELERATED:
  210.       return 1;
  211.    case PIPE_CAP_VIDEO_MEMORY:
  212.       return dev->vram_size >> 20;
  213.    case PIPE_CAP_UMA:
  214.       return 0;
  215.    }
  216.  
  217.    NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
  218.    return 0;
  219. }
  220.  
  221. static int
  222. nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
  223.                              enum pipe_shader_cap param)
  224. {
  225.    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  226.  
  227.    switch (shader) {
  228.    case PIPE_SHADER_VERTEX:
  229.       /*
  230.    case PIPE_SHADER_TESSELLATION_CONTROL:
  231.    case PIPE_SHADER_TESSELLATION_EVALUATION:
  232.       */
  233.    case PIPE_SHADER_GEOMETRY:
  234.    case PIPE_SHADER_FRAGMENT:
  235.       break;
  236.    case PIPE_SHADER_COMPUTE:
  237.       if (class_3d != NVE4_3D_CLASS)
  238.          return 0;
  239.       break;
  240.    default:
  241.       return 0;
  242.    }
  243.  
  244.    switch (param) {
  245.    case PIPE_SHADER_CAP_PREFERRED_IR:
  246.       return PIPE_SHADER_IR_TGSI;
  247.    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
  248.    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
  249.    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
  250.    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
  251.       return 16384;
  252.    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
  253.       return 16;
  254.    case PIPE_SHADER_CAP_MAX_INPUTS:
  255.       if (shader == PIPE_SHADER_VERTEX)
  256.          return 32;
  257.       /* NOTE: These only count our slots for GENERIC varyings.
  258.        * The address space may be larger, but the actual hard limit seems to be
  259.        * less than what the address space layout permits, so don't add TEXCOORD,
  260.        * COLOR, etc. here.
  261.        */
  262.       if (shader == PIPE_SHADER_FRAGMENT)
  263.          return 0x1f0 / 16;
  264.       /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
  265.        * and excludes 0x60 per-patch inputs.
  266.        */
  267.       return 0x200 / 16;
  268.    case PIPE_SHADER_CAP_MAX_OUTPUTS:
  269.       return 32;
  270.    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
  271.       return 65536;
  272.    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
  273.       if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
  274.          return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
  275.       return NVC0_MAX_PIPE_CONSTBUFS;
  276.    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
  277.    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
  278.       return shader != PIPE_SHADER_FRAGMENT;
  279.    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
  280.    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
  281.       return 1;
  282.    case PIPE_SHADER_CAP_MAX_PREDS:
  283.       return 0;
  284.    case PIPE_SHADER_CAP_MAX_TEMPS:
  285.       return NVC0_CAP_MAX_PROGRAM_TEMPS;
  286.    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
  287.       return 1;
  288.    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
  289.       return 0;
  290.    case PIPE_SHADER_CAP_SUBROUTINES:
  291.       return 1;
  292.    case PIPE_SHADER_CAP_INTEGERS:
  293.       return 1;
  294.    case PIPE_SHADER_CAP_DOUBLES:
  295.       return 1;
  296.    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
  297.       return 1;
  298.    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
  299.    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
  300.       return 0;
  301.    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
  302.       return 16; /* would be 32 in linked (OpenGL-style) mode */
  303.    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
  304.       return 16; /* XXX not sure if more are really safe */
  305.    default:
  306.       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
  307.       return 0;
  308.    }
  309. }
  310.  
  311. static float
  312. nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
  313. {
  314.    switch (param) {
  315.    case PIPE_CAPF_MAX_LINE_WIDTH:
  316.    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
  317.       return 10.0f;
  318.    case PIPE_CAPF_MAX_POINT_WIDTH:
  319.       return 63.0f;
  320.    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
  321.       return 63.375f;
  322.    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
  323.       return 16.0f;
  324.    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
  325.       return 15.0f;
  326.    case PIPE_CAPF_GUARD_BAND_LEFT:
  327.    case PIPE_CAPF_GUARD_BAND_TOP:
  328.       return 0.0f;
  329.    case PIPE_CAPF_GUARD_BAND_RIGHT:
  330.    case PIPE_CAPF_GUARD_BAND_BOTTOM:
  331.       return 0.0f; /* that or infinity */
  332.    }
  333.  
  334.    NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
  335.    return 0.0f;
  336. }
  337.  
  338. static int
  339. nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
  340.                               enum pipe_compute_cap param, void *data)
  341. {
  342.    uint64_t *data64 = (uint64_t *)data;
  343.    const uint16_t obj_class = nvc0_screen(pscreen)->compute->oclass;
  344.  
  345.    switch (param) {
  346.    case PIPE_COMPUTE_CAP_GRID_DIMENSION:
  347.       data64[0] = 3;
  348.       return 8;
  349.    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
  350.       data64[0] = (obj_class >= NVE4_COMPUTE_CLASS) ? 0x7fffffff : 65535;
  351.       data64[1] = 65535;
  352.       data64[2] = 65535;
  353.       return 24;
  354.    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
  355.       data64[0] = 1024;
  356.       data64[1] = 1024;
  357.       data64[2] = 64;
  358.       return 24;
  359.    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
  360.       data64[0] = 1024;
  361.       return 8;
  362.    case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
  363.       data64[0] = (uint64_t)1 << 40;
  364.       return 8;
  365.    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
  366.       data64[0] = 48 << 10;
  367.       return 8;
  368.    case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
  369.       data64[0] = 512 << 10;
  370.       return 8;
  371.    case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
  372.       data64[0] = 4096;
  373.       return 8;
  374.    default:
  375.       return 0;
  376.    }
  377. }
  378.  
  379. static void
  380. nvc0_screen_destroy(struct pipe_screen *pscreen)
  381. {
  382.    struct nvc0_screen *screen = nvc0_screen(pscreen);
  383.  
  384.    if (!nouveau_drm_screen_unref(&screen->base))
  385.       return;
  386.  
  387.    if (screen->base.fence.current) {
  388.       struct nouveau_fence *current = NULL;
  389.  
  390.       /* nouveau_fence_wait will create a new current fence, so wait on the
  391.        * _current_ one, and remove both.
  392.        */
  393.       nouveau_fence_ref(screen->base.fence.current, &current);
  394.       nouveau_fence_wait(current);
  395.       nouveau_fence_ref(NULL, &current);
  396.       nouveau_fence_ref(NULL, &screen->base.fence.current);
  397.    }
  398.    if (screen->base.pushbuf)
  399.       screen->base.pushbuf->user_priv = NULL;
  400.  
  401.    if (screen->blitter)
  402.       nvc0_blitter_destroy(screen);
  403.    if (screen->pm.prog) {
  404.       screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
  405.       nvc0_program_destroy(NULL, screen->pm.prog);
  406.    }
  407.  
  408.    nouveau_bo_ref(NULL, &screen->text);
  409.    nouveau_bo_ref(NULL, &screen->uniform_bo);
  410.    nouveau_bo_ref(NULL, &screen->tls);
  411.    nouveau_bo_ref(NULL, &screen->txc);
  412.    nouveau_bo_ref(NULL, &screen->fence.bo);
  413.    nouveau_bo_ref(NULL, &screen->poly_cache);
  414.    nouveau_bo_ref(NULL, &screen->parm);
  415.  
  416.    nouveau_heap_destroy(&screen->lib_code);
  417.    nouveau_heap_destroy(&screen->text_heap);
  418.  
  419.    FREE(screen->tic.entries);
  420.  
  421.    nouveau_object_del(&screen->eng3d);
  422.    nouveau_object_del(&screen->eng2d);
  423.    nouveau_object_del(&screen->m2mf);
  424.    nouveau_object_del(&screen->compute);
  425.    nouveau_object_del(&screen->nvsw);
  426.  
  427.    nouveau_screen_fini(&screen->base);
  428.  
  429.    FREE(screen);
  430. }
  431.  
  432. static int
  433. nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos,
  434.                      unsigned size, const uint32_t *data)
  435. {
  436.    struct nouveau_pushbuf *push = screen->base.pushbuf;
  437.  
  438.    size /= 4;
  439.  
  440.    assert((pos + size) <= 0x800);
  441.  
  442.    BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2);
  443.    PUSH_DATA (push, (m - 0x3800) / 8);
  444.    PUSH_DATA (push, pos);
  445.    BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1);
  446.    PUSH_DATA (push, pos);
  447.    PUSH_DATAp(push, data, size);
  448.  
  449.    return pos + size;
  450. }
  451.  
  452. static void
  453. nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
  454. {
  455.    BEGIN_NVC0(push, SUBC_3D(0x10cc), 1);
  456.    PUSH_DATA (push, 0xff);
  457.    BEGIN_NVC0(push, SUBC_3D(0x10e0), 2);
  458.    PUSH_DATA (push, 0xff);
  459.    PUSH_DATA (push, 0xff);
  460.    BEGIN_NVC0(push, SUBC_3D(0x10ec), 2);
  461.    PUSH_DATA (push, 0xff);
  462.    PUSH_DATA (push, 0xff);
  463.    BEGIN_NVC0(push, SUBC_3D(0x074c), 1);
  464.    PUSH_DATA (push, 0x3f);
  465.  
  466.    BEGIN_NVC0(push, SUBC_3D(0x16a8), 1);
  467.    PUSH_DATA (push, (3 << 16) | 3);
  468.    BEGIN_NVC0(push, SUBC_3D(0x1794), 1);
  469.    PUSH_DATA (push, (2 << 16) | 2);
  470.  
  471.    if (obj_class < GM107_3D_CLASS) {
  472.       BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
  473.       PUSH_DATA (push, 0);
  474.    }
  475.    BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
  476.    PUSH_DATA (push, 0x10);
  477.    BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
  478.    PUSH_DATA (push, 0x10);
  479.    BEGIN_NVC0(push, SUBC_3D(0x1290), 1);
  480.    PUSH_DATA (push, 0x10);
  481.    BEGIN_NVC0(push, SUBC_3D(0x12d8), 2);
  482.    PUSH_DATA (push, 0x10);
  483.    PUSH_DATA (push, 0x10);
  484.    BEGIN_NVC0(push, SUBC_3D(0x1140), 1);
  485.    PUSH_DATA (push, 0x10);
  486.    BEGIN_NVC0(push, SUBC_3D(0x1610), 1);
  487.    PUSH_DATA (push, 0xe);
  488.  
  489.    BEGIN_NVC0(push, NVC0_3D(VERTEX_ID_GEN_MODE), 1);
  490.    PUSH_DATA (push, NVC0_3D_VERTEX_ID_GEN_MODE_DRAW_ARRAYS_ADD_START);
  491.    BEGIN_NVC0(push, SUBC_3D(0x030c), 1);
  492.    PUSH_DATA (push, 0);
  493.    BEGIN_NVC0(push, SUBC_3D(0x0300), 1);
  494.    PUSH_DATA (push, 3);
  495.  
  496.    BEGIN_NVC0(push, SUBC_3D(0x02d0), 1);
  497.    PUSH_DATA (push, 0x3fffff);
  498.    BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1);
  499.    PUSH_DATA (push, 1);
  500.    BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
  501.    PUSH_DATA (push, 1);
  502.  
  503.    if (obj_class < GM107_3D_CLASS) {
  504.       BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
  505.       PUSH_DATA (push, 3);
  506.  
  507.       if (obj_class >= NVE4_3D_CLASS) {
  508.          BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
  509.          PUSH_DATA (push, 1);
  510.       }
  511.    }
  512.  
  513.    /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
  514.     * are supposed to do */
  515. }
  516.  
  517. static void
  518. nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
  519. {
  520.    struct nvc0_screen *screen = nvc0_screen(pscreen);
  521.    struct nouveau_pushbuf *push = screen->base.pushbuf;
  522.  
  523.    /* we need to do it after possible flush in MARK_RING */
  524.    *sequence = ++screen->base.fence.sequence;
  525.  
  526.    BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4);
  527.    PUSH_DATAh(push, screen->fence.bo->offset);
  528.    PUSH_DATA (push, screen->fence.bo->offset);
  529.    PUSH_DATA (push, *sequence);
  530.    PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT |
  531.               (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT));
  532. }
  533.  
  534. static u32
  535. nvc0_screen_fence_update(struct pipe_screen *pscreen)
  536. {
  537.    struct nvc0_screen *screen = nvc0_screen(pscreen);
  538.    return screen->fence.map[0];
  539. }
  540.  
  541. static int
  542. nvc0_screen_init_compute(struct nvc0_screen *screen)
  543. {
  544.    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
  545.  
  546.    switch (screen->base.device->chipset & ~0xf) {
  547.    case 0xc0:
  548.    case 0xd0:
  549.       /* Using COMPUTE has weird effects on 3D state, we need to
  550.        * investigate this further before enabling it by default.
  551.        */
  552.       if (debug_get_bool_option("NVC0_COMPUTE", FALSE))
  553.          return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
  554.       return 0;
  555.    case 0xe0:
  556.       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
  557.    case 0xf0:
  558.    case 0x100:
  559.    case 0x110:
  560.       return 0;
  561.    default:
  562.       return -1;
  563.    }
  564. }
  565.  
  566. boolean
  567. nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
  568.                             uint32_t lpos, uint32_t lneg, uint32_t cstack)
  569. {
  570.    struct nouveau_bo *bo = NULL;
  571.    int ret;
  572.    uint64_t size = (lpos + lneg) * 32 + cstack;
  573.  
  574.    if (size >= (1 << 20)) {
  575.       NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
  576.       return FALSE;
  577.    }
  578.  
  579.    size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
  580.    size  = align(size, 0x8000);
  581.    size *= screen->mp_count;
  582.  
  583.    size = align(size, 1 << 17);
  584.  
  585.    ret = nouveau_bo_new(screen->base.device, NOUVEAU_BO_VRAM, 1 << 17, size,
  586.                         NULL, &bo);
  587.    if (ret) {
  588.       NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
  589.       return FALSE;
  590.    }
  591.    nouveau_bo_ref(NULL, &screen->tls);
  592.    screen->tls = bo;
  593.    return TRUE;
  594. }
  595.  
  596. #define FAIL_SCREEN_INIT(str, err)                    \
  597.    do {                                               \
  598.       NOUVEAU_ERR(str, err);                          \
  599.       nvc0_screen_destroy(pscreen);                   \
  600.       return NULL;                                    \
  601.    } while(0)
  602.  
  603. struct pipe_screen *
  604. nvc0_screen_create(struct nouveau_device *dev)
  605. {
  606.    struct nvc0_screen *screen;
  607.    struct pipe_screen *pscreen;
  608.    struct nouveau_object *chan;
  609.    struct nouveau_pushbuf *push;
  610.    uint64_t value;
  611.    uint32_t obj_class;
  612.    int ret;
  613.    unsigned i;
  614.  
  615.    switch (dev->chipset & ~0xf) {
  616.    case 0xc0:
  617.    case 0xd0:
  618.    case 0xe0:
  619.    case 0xf0:
  620.    case 0x100:
  621.    case 0x110:
  622.       break;
  623.    default:
  624.       return NULL;
  625.    }
  626.  
  627.    screen = CALLOC_STRUCT(nvc0_screen);
  628.    if (!screen)
  629.       return NULL;
  630.    pscreen = &screen->base.base;
  631.  
  632.    ret = nouveau_screen_init(&screen->base, dev);
  633.    if (ret) {
  634.       nvc0_screen_destroy(pscreen);
  635.       return NULL;
  636.    }
  637.    chan = screen->base.channel;
  638.    push = screen->base.pushbuf;
  639.    push->user_priv = screen;
  640.    push->rsvd_kick = 5;
  641.  
  642.    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
  643.       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
  644.       PIPE_BIND_COMMAND_ARGS_BUFFER;
  645.    screen->base.sysmem_bindings |=
  646.       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
  647.  
  648.    pscreen->destroy = nvc0_screen_destroy;
  649.    pscreen->context_create = nvc0_create;
  650.    pscreen->is_format_supported = nvc0_screen_is_format_supported;
  651.    pscreen->get_param = nvc0_screen_get_param;
  652.    pscreen->get_shader_param = nvc0_screen_get_shader_param;
  653.    pscreen->get_paramf = nvc0_screen_get_paramf;
  654.    pscreen->get_driver_query_info = nvc0_screen_get_driver_query_info;
  655.    pscreen->get_driver_query_group_info = nvc0_screen_get_driver_query_group_info;
  656.  
  657.    nvc0_screen_init_resource_functions(pscreen);
  658.  
  659.    screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
  660.    screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
  661.  
  662.    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL,
  663.                         &screen->fence.bo);
  664.    if (ret)
  665.       goto fail;
  666.    nouveau_bo_map(screen->fence.bo, 0, NULL);
  667.    screen->fence.map = screen->fence.bo->map;
  668.    screen->base.fence.emit = nvc0_screen_fence_emit;
  669.    screen->base.fence.update = nvc0_screen_fence_update;
  670.  
  671.  
  672.    ret = nouveau_object_new(chan,
  673.                             (dev->chipset < 0xe0) ? 0x1f906e : 0x906e, 0x906e,
  674.                             NULL, 0, &screen->nvsw);
  675.    if (ret)
  676.       FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
  677.  
  678.  
  679.    switch (dev->chipset & ~0xf) {
  680.    case 0x110:
  681.    case 0x100:
  682.    case 0xf0:
  683.       obj_class = NVF0_P2MF_CLASS;
  684.       break;
  685.    case 0xe0:
  686.       obj_class = NVE4_P2MF_CLASS;
  687.       break;
  688.    default:
  689.       obj_class = NVC0_M2MF_CLASS;
  690.       break;
  691.    }
  692.    ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0,
  693.                             &screen->m2mf);
  694.    if (ret)
  695.       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
  696.  
  697.    BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
  698.    PUSH_DATA (push, screen->m2mf->oclass);
  699.    if (screen->m2mf->oclass == NVE4_P2MF_CLASS) {
  700.       BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1);
  701.       PUSH_DATA (push, 0xa0b5);
  702.    }
  703.  
  704.    ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0,
  705.                             &screen->eng2d);
  706.    if (ret)
  707.       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
  708.  
  709.    BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
  710.    PUSH_DATA (push, screen->eng2d->oclass);
  711.    BEGIN_NVC0(push, SUBC_2D(NVC0_2D_SINGLE_GPC), 1);
  712.    PUSH_DATA (push, 0);
  713.    BEGIN_NVC0(push, NVC0_2D(OPERATION), 1);
  714.    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
  715.    BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1);
  716.    PUSH_DATA (push, 0);
  717.    BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1);
  718.    PUSH_DATA (push, 0);
  719.    BEGIN_NVC0(push, SUBC_2D(0x0884), 1);
  720.    PUSH_DATA (push, 0x3f);
  721.    BEGIN_NVC0(push, SUBC_2D(0x0888), 1);
  722.    PUSH_DATA (push, 1);
  723.    BEGIN_NVC0(push, NVC0_2D(COND_MODE), 1);
  724.    PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
  725.  
  726.    BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2);
  727.    PUSH_DATAh(push, screen->fence.bo->offset + 16);
  728.    PUSH_DATA (push, screen->fence.bo->offset + 16);
  729.  
  730.    switch (dev->chipset & ~0xf) {
  731.    case 0x110:
  732.       obj_class = GM107_3D_CLASS;
  733.       break;
  734.    case 0x100:
  735.    case 0xf0:
  736.       obj_class = NVF0_3D_CLASS;
  737.       break;
  738.    case 0xe0:
  739.       switch (dev->chipset) {
  740.       case 0xea:
  741.          obj_class = NVEA_3D_CLASS;
  742.          break;
  743.       default:
  744.          obj_class = NVE4_3D_CLASS;
  745.          break;
  746.       }
  747.       break;
  748.    case 0xd0:
  749.       obj_class = NVC8_3D_CLASS;
  750.       break;
  751.    case 0xc0:
  752.    default:
  753.       switch (dev->chipset) {
  754.       case 0xc8:
  755.          obj_class = NVC8_3D_CLASS;
  756.          break;
  757.       case 0xc1:
  758.          obj_class = NVC1_3D_CLASS;
  759.          break;
  760.       default:
  761.          obj_class = NVC0_3D_CLASS;
  762.          break;
  763.       }
  764.       break;
  765.    }
  766.    ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0,
  767.                             &screen->eng3d);
  768.    if (ret)
  769.       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
  770.    screen->base.class_3d = obj_class;
  771.  
  772.    BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
  773.    PUSH_DATA (push, screen->eng3d->oclass);
  774.  
  775.    BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1);
  776.    PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS);
  777.  
  778.    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
  779.       /* kill shaders after about 1 second (at 100 MHz) */
  780.       BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1);
  781.       PUSH_DATA (push, 0x17);
  782.    }
  783.  
  784.    IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE), dev->drm_version >= 0x01000101);
  785.    BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
  786.    for (i = 0; i < 8; ++i)
  787.            PUSH_DATA(push, dev->drm_version >= 0x01000101);
  788.  
  789.    BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
  790.    PUSH_DATA (push, 1);
  791.  
  792.    BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1);
  793.    PUSH_DATA (push, 0);
  794.    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1);
  795.    PUSH_DATA (push, 0);
  796.    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1);
  797.    PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1);
  798.    BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1);
  799.    PUSH_DATA (push, 0);
  800.    BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1);
  801.    PUSH_DATA (push, 1);
  802.    BEGIN_NVC0(push, NVC0_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
  803.    PUSH_DATA (push, 1);
  804.    BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1);
  805.    PUSH_DATA (push, 1);
  806.    BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1);
  807.    PUSH_DATA (push, 0);
  808.    if (screen->eng3d->oclass < NVE4_3D_CLASS) {
  809.       BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1);
  810.       PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
  811.    } else {
  812.       BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1);
  813.       PUSH_DATA (push, 15);
  814.    }
  815.    BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1);
  816.    PUSH_DATA (push, 8); /* 128 */
  817.    BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1);
  818.    PUSH_DATA (push, 1);
  819.    if (screen->eng3d->oclass >= NVC1_3D_CLASS) {
  820.       BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1);
  821.       PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1);
  822.    }
  823.  
  824.    nvc0_magic_3d_init(push, screen->eng3d->oclass);
  825.  
  826.    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
  827.                         &screen->text);
  828.    if (ret)
  829.       goto fail;
  830.  
  831.    /* XXX: getting a page fault at the end of the code buffer every few
  832.     *  launches, don't use the last 256 bytes to work around them - prefetch ?
  833.     */
  834.    nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
  835.  
  836.    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL,
  837.                         &screen->uniform_bo);
  838.    if (ret)
  839.       goto fail;
  840.  
  841.    PUSH_REFN (push, screen->uniform_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
  842.  
  843.    for (i = 0; i < 5; ++i) {
  844.       /* TIC and TSC entries for each unit (nve4+ only) */
  845.       /* auxiliary constants (6 user clip planes, base instance id) */
  846.       BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
  847.       PUSH_DATA (push, 512);
  848.       PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
  849.       PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9));
  850.       BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
  851.       PUSH_DATA (push, (15 << 4) | 1);
  852.       if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
  853.          unsigned j;
  854.          BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
  855.          PUSH_DATA (push, 0);
  856.          for (j = 0; j < 8; ++j)
  857.             PUSH_DATA(push, j);
  858.       } else {
  859.          BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
  860.          PUSH_DATA (push, 0x54);
  861.       }
  862.    }
  863.    BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
  864.    PUSH_DATA (push, 0);
  865.  
  866.    /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
  867.    BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
  868.    PUSH_DATA (push, 256);
  869.    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
  870.    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
  871.    BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
  872.    PUSH_DATA (push, 0);
  873.    PUSH_DATAf(push, 0.0f);
  874.    PUSH_DATAf(push, 0.0f);
  875.    PUSH_DATAf(push, 0.0f);
  876.    PUSH_DATAf(push, 0.0f);
  877.    BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
  878.    PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
  879.    PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9));
  880.  
  881.    if (dev->drm_version >= 0x01000101) {
  882.       ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
  883.       if (ret) {
  884.          NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
  885.          goto fail;
  886.       }
  887.    } else {
  888.       if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
  889.          value = (8 << 8) | 4;
  890.       else
  891.          value = (16 << 8) | 4;
  892.    }
  893.    screen->mp_count = value >> 8;
  894.    screen->mp_count_compute = screen->mp_count;
  895.  
  896.    nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
  897.  
  898.    BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
  899.    PUSH_DATAh(push, screen->text->offset);
  900.    PUSH_DATA (push, screen->text->offset);
  901.    BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
  902.    PUSH_DATAh(push, screen->tls->offset);
  903.    PUSH_DATA (push, screen->tls->offset);
  904.    PUSH_DATA (push, screen->tls->size >> 32);
  905.    PUSH_DATA (push, screen->tls->size);
  906.    BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1);
  907.    PUSH_DATA (push, 0);
  908.    BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
  909.    PUSH_DATA (push, 0);
  910.  
  911.    if (screen->eng3d->oclass < GM107_3D_CLASS) {
  912.       ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
  913.                            &screen->poly_cache);
  914.       if (ret)
  915.          goto fail;
  916.  
  917.       BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
  918.       PUSH_DATAh(push, screen->poly_cache->offset);
  919.       PUSH_DATA (push, screen->poly_cache->offset);
  920.       PUSH_DATA (push, 3);
  921.    }
  922.  
  923.    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL,
  924.                         &screen->txc);
  925.    if (ret)
  926.       goto fail;
  927.  
  928.    BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
  929.    PUSH_DATAh(push, screen->txc->offset);
  930.    PUSH_DATA (push, screen->txc->offset);
  931.    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
  932.  
  933.    BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
  934.    PUSH_DATAh(push, screen->txc->offset + 65536);
  935.    PUSH_DATA (push, screen->txc->offset + 65536);
  936.    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
  937.  
  938.    BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1);
  939.    PUSH_DATA (push, 0);
  940.    BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2);
  941.    PUSH_DATA (push, 0);
  942.    PUSH_DATA (push, 0);
  943.    BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
  944.    PUSH_DATA (push, 0x3f);
  945.  
  946.    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1);
  947.    PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY);
  948.    BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
  949.    for (i = 0; i < 8 * 2; ++i)
  950.       PUSH_DATA(push, 0);
  951.    BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1);
  952.    PUSH_DATA (push, 0);
  953.    BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1);
  954.    PUSH_DATA (push, 0);
  955.  
  956.    /* neither scissors, viewport nor stencil mask should affect clears */
  957.    BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1);
  958.    PUSH_DATA (push, 0);
  959.  
  960.    BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
  961.    PUSH_DATA (push, 1);
  962.    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
  963.       BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(i)), 2);
  964.       PUSH_DATAf(push, 0.0f);
  965.       PUSH_DATAf(push, 1.0f);
  966.    }
  967.    BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1);
  968.    PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1);
  969.  
  970.    /* We use scissors instead of exact view volume clipping,
  971.     * so they're always enabled.
  972.     */
  973.    for (i = 0; i < NVC0_MAX_VIEWPORTS; i++) {
  974.       BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(i)), 3);
  975.       PUSH_DATA (push, 1);
  976.       PUSH_DATA (push, 8192 << 16);
  977.       PUSH_DATA (push, 8192 << 16);
  978.    }
  979.  
  980. #define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n);
  981.  
  982.    i = 0;
  983.    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, mme9097_per_instance_bf);
  984.    MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, mme9097_blend_enables);
  985.    MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, mme9097_vertex_array_select);
  986.    MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, mme9097_tep_select);
  987.    MK_MACRO(NVC0_3D_MACRO_GP_SELECT, mme9097_gp_select);
  988.    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, mme9097_poly_mode_front);
  989.    MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, mme9097_poly_mode_back);
  990.    MK_MACRO(NVC0_3D_MACRO_DRAW_ARRAYS_INDIRECT, mme9097_draw_arrays_indirect);
  991.    MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT, mme9097_draw_elts_indirect);
  992.  
  993.    BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
  994.    PUSH_DATA (push, 1);
  995.    BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1);
  996.    PUSH_DATA (push, 1);
  997.    BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1);
  998.    PUSH_DATA (push, 0x40);
  999.    BEGIN_NVC0(push, NVC0_3D(LAYER), 1);
  1000.    PUSH_DATA (push, 0);
  1001.    BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1);
  1002.    PUSH_DATA (push, 0x30);
  1003.    BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1);
  1004.    PUSH_DATA (push, 3);
  1005.    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
  1006.    PUSH_DATA (push, 0x20);
  1007.    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
  1008.    PUSH_DATA (push, 0x00);
  1009.  
  1010.    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
  1011.    PUSH_DATA (push, 0);
  1012.    BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1);
  1013.    PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL);
  1014.  
  1015.    IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1);
  1016.  
  1017.    if (nvc0_screen_init_compute(screen))
  1018.       goto fail;
  1019.  
  1020.    PUSH_KICK (push);
  1021.  
  1022.    screen->tic.entries = CALLOC(4096, sizeof(void *));
  1023.    screen->tsc.entries = screen->tic.entries + 2048;
  1024.  
  1025.    if (!nvc0_blitter_create(screen))
  1026.       goto fail;
  1027.  
  1028.    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
  1029.  
  1030.    return pscreen;
  1031.  
  1032. fail:
  1033.    nvc0_screen_destroy(pscreen);
  1034.    return NULL;
  1035. }
  1036.  
  1037. int
  1038. nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry)
  1039. {
  1040.    int i = screen->tic.next;
  1041.  
  1042.    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
  1043.       i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
  1044.  
  1045.    screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1);
  1046.  
  1047.    if (screen->tic.entries[i])
  1048.       nv50_tic_entry(screen->tic.entries[i])->id = -1;
  1049.  
  1050.    screen->tic.entries[i] = entry;
  1051.    return i;
  1052. }
  1053.  
  1054. int
  1055. nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry)
  1056. {
  1057.    int i = screen->tsc.next;
  1058.  
  1059.    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
  1060.       i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
  1061.  
  1062.    screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1);
  1063.  
  1064.    if (screen->tsc.entries[i])
  1065.       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
  1066.  
  1067.    screen->tsc.entries[i] = entry;
  1068.    return i;
  1069. }
  1070.