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  1. /*
  2.  * Copyright 2010 Christoph Bumiller
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice shall be included in
  12.  * all copies or substantial portions of the Software.
  13.  *
  14.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20.  * OTHER DEALINGS IN THE SOFTWARE.
  21.  */
  22.  
  23. #include "pipe/p_context.h"
  24. #include "pipe/p_state.h"
  25. #include "util/u_inlines.h"
  26. #include "util/u_format.h"
  27. #include "translate/translate.h"
  28.  
  29. #include "nv50/nv50_context.h"
  30. #include "nv50/nv50_resource.h"
  31.  
  32. #include "nv50/nv50_3d.xml.h"
  33.  
  34. void
  35. nv50_vertex_state_delete(struct pipe_context *pipe,
  36.                          void *hwcso)
  37. {
  38.    struct nv50_vertex_stateobj *so = hwcso;
  39.  
  40.    if (so->translate)
  41.       so->translate->release(so->translate);
  42.    FREE(hwcso);
  43. }
  44.  
  45. void *
  46. nv50_vertex_state_create(struct pipe_context *pipe,
  47.                          unsigned num_elements,
  48.                          const struct pipe_vertex_element *elements)
  49. {
  50.     struct nv50_vertex_stateobj *so;
  51.     struct translate_key transkey;
  52.     unsigned i;
  53.  
  54.     so = MALLOC(sizeof(*so) +
  55.                 num_elements * sizeof(struct nv50_vertex_element));
  56.     if (!so)
  57.         return NULL;
  58.     so->num_elements = num_elements;
  59.     so->instance_elts = 0;
  60.     so->instance_bufs = 0;
  61.     so->need_conversion = FALSE;
  62.  
  63.     memset(so->vb_access_size, 0, sizeof(so->vb_access_size));
  64.  
  65.     for (i = 0; i < PIPE_MAX_ATTRIBS; ++i)
  66.        so->min_instance_div[i] = 0xffffffff;
  67.  
  68.     transkey.nr_elements = 0;
  69.     transkey.output_stride = 0;
  70.  
  71.     for (i = 0; i < num_elements; ++i) {
  72.         const struct pipe_vertex_element *ve = &elements[i];
  73.         const unsigned vbi = ve->vertex_buffer_index;
  74.         unsigned size;
  75.         enum pipe_format fmt = ve->src_format;
  76.  
  77.         so->element[i].pipe = elements[i];
  78.         so->element[i].state = nv50_format_table[fmt].vtx;
  79.  
  80.         if (!so->element[i].state) {
  81.             switch (util_format_get_nr_components(fmt)) {
  82.             case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
  83.             case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
  84.             case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
  85.             case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
  86.             default:
  87.                 assert(0);
  88.                 FREE(so);
  89.                 return NULL;
  90.             }
  91.             so->element[i].state = nv50_format_table[fmt].vtx;
  92.             so->need_conversion = TRUE;
  93.         }
  94.         so->element[i].state |= i;
  95.  
  96.         size = util_format_get_blocksize(fmt);
  97.         if (so->vb_access_size[vbi] < (ve->src_offset + size))
  98.            so->vb_access_size[vbi] = ve->src_offset + size;
  99.  
  100.         if (1) {
  101.             unsigned j = transkey.nr_elements++;
  102.  
  103.             transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
  104.             transkey.element[j].input_format = ve->src_format;
  105.             transkey.element[j].input_buffer = vbi;
  106.             transkey.element[j].input_offset = ve->src_offset;
  107.             transkey.element[j].instance_divisor = ve->instance_divisor;
  108.  
  109.             transkey.element[j].output_format = fmt;
  110.             transkey.element[j].output_offset = transkey.output_stride;
  111.             transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3;
  112.  
  113.             if (unlikely(ve->instance_divisor)) {
  114.                so->instance_elts |= 1 << i;
  115.                so->instance_bufs |= 1 << vbi;
  116.                if (ve->instance_divisor < so->min_instance_div[vbi])
  117.                   so->min_instance_div[vbi] = ve->instance_divisor;
  118.             }
  119.         }
  120.     }
  121.  
  122.     so->translate = translate_create(&transkey);
  123.     so->vertex_size = transkey.output_stride / 4;
  124.     so->packet_vertex_limit = NV04_PFIFO_MAX_PACKET_LEN /
  125.        MAX2(so->vertex_size, 1);
  126.  
  127.     return so;
  128. }
  129.  
  130. #define NV50_3D_VERTEX_ATTRIB_INACTIVE              \
  131.    NV50_3D_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT |         \
  132.    NV50_3D_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32 | \
  133.    NV50_3D_VERTEX_ARRAY_ATTRIB_CONST
  134.  
  135. static void
  136. nv50_emit_vtxattr(struct nv50_context *nv50, struct pipe_vertex_buffer *vb,
  137.                   struct pipe_vertex_element *ve, unsigned attr)
  138. {
  139.    struct nouveau_pushbuf *push = nv50->base.pushbuf;
  140.    const void *data = (const uint8_t *)vb->user_buffer + ve->src_offset;
  141.    float v[4];
  142.    const unsigned nc = util_format_get_nr_components(ve->src_format);
  143.    const struct util_format_description *desc =
  144.       util_format_description(ve->src_format);
  145.  
  146.    assert(vb->user_buffer);
  147.  
  148.    if (desc->channel[0].pure_integer) {
  149.       if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) {
  150.          desc->unpack_rgba_sint((int32_t *)v, 0, data, 0, 1, 1);
  151.       } else {
  152.          desc->unpack_rgba_uint((uint32_t *)v, 0, data, 0, 1, 1);
  153.       }
  154.    } else {
  155.       desc->unpack_rgba_float(v, 0, data, 0, 1, 1);
  156.    }
  157.  
  158.    switch (nc) {
  159.    case 4:
  160.       BEGIN_NV04(push, NV50_3D(VTX_ATTR_4F_X(attr)), 4);
  161.       PUSH_DATAf(push, v[0]);
  162.       PUSH_DATAf(push, v[1]);
  163.       PUSH_DATAf(push, v[2]);
  164.       PUSH_DATAf(push, v[3]);
  165.       break;
  166.    case 3:
  167.       BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(attr)), 3);
  168.       PUSH_DATAf(push, v[0]);
  169.       PUSH_DATAf(push, v[1]);
  170.       PUSH_DATAf(push, v[2]);
  171.       break;
  172.    case 2:
  173.       BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(attr)), 2);
  174.       PUSH_DATAf(push, v[0]);
  175.       PUSH_DATAf(push, v[1]);
  176.       break;
  177.    case 1:
  178.       if (attr == nv50->vertprog->vp.edgeflag) {
  179.          BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
  180.          PUSH_DATA (push, v[0] ? 1 : 0);
  181.       }
  182.       BEGIN_NV04(push, NV50_3D(VTX_ATTR_1F(attr)), 1);
  183.       PUSH_DATAf(push, v[0]);
  184.       break;
  185.    default:
  186.       assert(0);
  187.       break;
  188.    }
  189. }
  190.  
  191. static INLINE void
  192. nv50_user_vbuf_range(struct nv50_context *nv50, unsigned vbi,
  193.                      uint32_t *base, uint32_t *size)
  194. {
  195.    assert(vbi < PIPE_MAX_ATTRIBS);
  196.    if (unlikely(nv50->vertex->instance_bufs & (1 << vbi))) {
  197.       /* TODO: use min and max instance divisor to get a proper range */
  198.       *base = 0;
  199.       *size = nv50->vtxbuf[vbi].buffer->width0;
  200.    } else {
  201.       /* NOTE: if there are user buffers, we *must* have index bounds */
  202.       assert(nv50->vb_elt_limit != ~0);
  203.       *base = nv50->vb_elt_first * nv50->vtxbuf[vbi].stride;
  204.       *size = nv50->vb_elt_limit * nv50->vtxbuf[vbi].stride +
  205.          nv50->vertex->vb_access_size[vbi];
  206.    }
  207. }
  208.  
  209. static void
  210. nv50_upload_user_buffers(struct nv50_context *nv50,
  211.                          uint64_t addrs[], uint32_t limits[])
  212. {
  213.    unsigned b;
  214.  
  215.    assert(nv50->num_vtxbufs <= PIPE_MAX_ATTRIBS);
  216.    for (b = 0; b < nv50->num_vtxbufs; ++b) {
  217.       struct nouveau_bo *bo;
  218.       const struct pipe_vertex_buffer *vb = &nv50->vtxbuf[b];
  219.       uint32_t base, size;
  220.  
  221.       if (!(nv50->vbo_user & (1 << b)) || !vb->stride)
  222.          continue;
  223.       nv50_user_vbuf_range(nv50, b, &base, &size);
  224.  
  225.       limits[b] = base + size - 1;
  226.       addrs[b] = nouveau_scratch_data(&nv50->base, vb->user_buffer, base, size,
  227.                                       &bo);
  228.       if (addrs[b])
  229.          BCTX_REFN_bo(nv50->bufctx_3d, VERTEX_TMP, NOUVEAU_BO_GART |
  230.                       NOUVEAU_BO_RD, bo);
  231.    }
  232.    nv50->base.vbo_dirty = TRUE;
  233. }
  234.  
  235. static void
  236. nv50_update_user_vbufs(struct nv50_context *nv50)
  237. {
  238.    uint64_t address[PIPE_MAX_ATTRIBS];
  239.    struct nouveau_pushbuf *push = nv50->base.pushbuf;
  240.    unsigned i;
  241.    uint32_t written = 0;
  242.  
  243.    for (i = 0; i < nv50->vertex->num_elements; ++i) {
  244.       struct pipe_vertex_element *ve = &nv50->vertex->element[i].pipe;
  245.       const unsigned b = ve->vertex_buffer_index;
  246.       struct pipe_vertex_buffer *vb;
  247.       uint32_t base, size;
  248.  
  249.       assert(b < PIPE_MAX_ATTRIBS);
  250.       vb = &nv50->vtxbuf[b];
  251.  
  252.       if (!(nv50->vbo_user & (1 << b)))
  253.          continue;
  254.  
  255.       if (!vb->stride) {
  256.          nv50_emit_vtxattr(nv50, vb, ve, i);
  257.          continue;
  258.       }
  259.       nv50_user_vbuf_range(nv50, b, &base, &size);
  260.  
  261.       if (!(written & (1 << b))) {
  262.          struct nouveau_bo *bo;
  263.          const uint32_t bo_flags = NOUVEAU_BO_GART | NOUVEAU_BO_RD;
  264.          written |= 1 << b;
  265.          address[b] = nouveau_scratch_data(&nv50->base, vb->user_buffer,
  266.                                            base, size, &bo);
  267.          if (address[b])
  268.             BCTX_REFN_bo(nv50->bufctx_3d, VERTEX_TMP, bo_flags, bo);
  269.       }
  270.  
  271.       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
  272.       PUSH_DATAh(push, address[b] + base + size - 1);
  273.       PUSH_DATA (push, address[b] + base + size - 1);
  274.       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_START_HIGH(i)), 2);
  275.       PUSH_DATAh(push, address[b] + ve->src_offset);
  276.       PUSH_DATA (push, address[b] + ve->src_offset);
  277.    }
  278.    nv50->base.vbo_dirty = TRUE;
  279. }
  280.  
  281. static INLINE void
  282. nv50_release_user_vbufs(struct nv50_context *nv50)
  283. {
  284.    if (nv50->vbo_user) {
  285.       nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_VERTEX_TMP);
  286.       nouveau_scratch_done(&nv50->base);
  287.    }
  288. }
  289.  
  290. void
  291. nv50_vertex_arrays_validate(struct nv50_context *nv50)
  292. {
  293.    uint64_t addrs[PIPE_MAX_ATTRIBS];
  294.    uint32_t limits[PIPE_MAX_ATTRIBS];
  295.    struct nouveau_pushbuf *push = nv50->base.pushbuf;
  296.    struct nv50_vertex_stateobj *vertex = nv50->vertex;
  297.    struct pipe_vertex_buffer *vb;
  298.    struct nv50_vertex_element *ve;
  299.    uint32_t mask;
  300.    uint32_t refd = 0;
  301.    unsigned i;
  302.    const unsigned n = MAX2(vertex->num_elements, nv50->state.num_vtxelts);
  303.  
  304.    if (unlikely(vertex->need_conversion))
  305.       nv50->vbo_fifo = ~0;
  306.    else
  307.    if (nv50->vbo_user & ~nv50->vbo_constant)
  308.       nv50->vbo_fifo = nv50->vbo_push_hint ? ~0 : 0;
  309.    else
  310.       nv50->vbo_fifo = 0;
  311.  
  312.    if (!nv50->vbo_fifo) {
  313.       /* if vertex buffer was written by GPU - flush VBO cache */
  314.       assert(nv50->num_vtxbufs <= PIPE_MAX_ATTRIBS);
  315.       for (i = 0; i < nv50->num_vtxbufs; ++i) {
  316.          struct nv04_resource *buf = nv04_resource(nv50->vtxbuf[i].buffer);
  317.          if (buf && buf->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
  318.             buf->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
  319.             nv50->base.vbo_dirty = TRUE;
  320.             break;
  321.          }
  322.       }
  323.    }
  324.  
  325.    /* update vertex format state */
  326.    BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_ATTRIB(0)), n);
  327.    if (nv50->vbo_fifo) {
  328.       nv50->state.num_vtxelts = vertex->num_elements;
  329.       for (i = 0; i < vertex->num_elements; ++i)
  330.          PUSH_DATA (push, vertex->element[i].state);
  331.       for (; i < n; ++i)
  332.          PUSH_DATA (push, NV50_3D_VERTEX_ATTRIB_INACTIVE);
  333.       for (i = 0; i < n; ++i) {
  334.          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
  335.          PUSH_DATA (push, 0);
  336.       }
  337.       return;
  338.    }
  339.    for (i = 0; i < vertex->num_elements; ++i) {
  340.       const unsigned b = vertex->element[i].pipe.vertex_buffer_index;
  341.  
  342.       assert(b < PIPE_MAX_ATTRIBS);
  343.       ve = &vertex->element[i];
  344.       vb = &nv50->vtxbuf[b];
  345.  
  346.       if (likely(vb->stride) || !(nv50->vbo_user & (1 << b)))
  347.          PUSH_DATA(push, ve->state);
  348.       else
  349.          PUSH_DATA(push, ve->state | NV50_3D_VERTEX_ARRAY_ATTRIB_CONST);
  350.    }
  351.    for (; i < n; ++i)
  352.       PUSH_DATA(push, NV50_3D_VERTEX_ATTRIB_INACTIVE);
  353.  
  354.    /* update per-instance enables */
  355.    mask = vertex->instance_elts ^ nv50->state.instance_elts;
  356.    while (mask) {
  357.       const int i = ffs(mask) - 1;
  358.       mask &= ~(1 << i);
  359.       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1);
  360.       PUSH_DATA (push, (vertex->instance_elts >> i) & 1);
  361.    }
  362.    nv50->state.instance_elts = vertex->instance_elts;
  363.  
  364.    if (nv50->vbo_user & ~nv50->vbo_constant)
  365.       nv50_upload_user_buffers(nv50, addrs, limits);
  366.  
  367.    /* update buffers and set constant attributes */
  368.    for (i = 0; i < vertex->num_elements; ++i) {
  369.       uint64_t address, limit;
  370.       const unsigned b = vertex->element[i].pipe.vertex_buffer_index;
  371.  
  372.       assert(b < PIPE_MAX_ATTRIBS);
  373.       ve = &vertex->element[i];
  374.       vb = &nv50->vtxbuf[b];
  375.  
  376.       if (unlikely(nv50->vbo_constant & (1 << b))) {
  377.          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
  378.          PUSH_DATA (push, 0);
  379.          nv50_emit_vtxattr(nv50, vb, &ve->pipe, i);
  380.          continue;
  381.       } else
  382.       if (nv50->vbo_user & (1 << b)) {
  383.          address = addrs[b] + ve->pipe.src_offset;
  384.          limit = addrs[b] + limits[b];
  385.       } else {
  386.          struct nv04_resource *buf = nv04_resource(vb->buffer);
  387.          if (!(refd & (1 << b))) {
  388.             refd |= 1 << b;
  389.             BCTX_REFN(nv50->bufctx_3d, VERTEX, buf, RD);
  390.          }
  391.          address = buf->address + vb->buffer_offset + ve->pipe.src_offset;
  392.          limit = buf->address + buf->base.width0 - 1;
  393.       }
  394.  
  395.       if (unlikely(ve->pipe.instance_divisor)) {
  396.          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 4);
  397.          PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
  398.          PUSH_DATAh(push, address);
  399.          PUSH_DATA (push, address);
  400.          PUSH_DATA (push, ve->pipe.instance_divisor);
  401.       } else {
  402.          BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 3);
  403.          PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride);
  404.          PUSH_DATAh(push, address);
  405.          PUSH_DATA (push, address);
  406.       }
  407.       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
  408.       PUSH_DATAh(push, limit);
  409.       PUSH_DATA (push, limit);
  410.    }
  411.    for (; i < nv50->state.num_vtxelts; ++i) {
  412.       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
  413.       PUSH_DATA (push, 0);
  414.    }
  415.    nv50->state.num_vtxelts = vertex->num_elements;
  416. }
  417.  
  418. #define NV50_PRIM_GL_CASE(n) \
  419.    case PIPE_PRIM_##n: return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
  420.  
  421. static INLINE unsigned
  422. nv50_prim_gl(unsigned prim)
  423. {
  424.    switch (prim) {
  425.    NV50_PRIM_GL_CASE(POINTS);
  426.    NV50_PRIM_GL_CASE(LINES);
  427.    NV50_PRIM_GL_CASE(LINE_LOOP);
  428.    NV50_PRIM_GL_CASE(LINE_STRIP);
  429.    NV50_PRIM_GL_CASE(TRIANGLES);
  430.    NV50_PRIM_GL_CASE(TRIANGLE_STRIP);
  431.    NV50_PRIM_GL_CASE(TRIANGLE_FAN);
  432.    NV50_PRIM_GL_CASE(QUADS);
  433.    NV50_PRIM_GL_CASE(QUAD_STRIP);
  434.    NV50_PRIM_GL_CASE(POLYGON);
  435.    NV50_PRIM_GL_CASE(LINES_ADJACENCY);
  436.    NV50_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
  437.    NV50_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
  438.    NV50_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
  439.    default:
  440.       return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
  441.       break;
  442.    }
  443. }
  444.  
  445. /* For pre-nva0 transform feedback. */
  446. static const uint8_t nv50_pipe_prim_to_prim_size[PIPE_PRIM_MAX + 1] =
  447. {
  448.    [PIPE_PRIM_POINTS] = 1,
  449.    [PIPE_PRIM_LINES] = 2,
  450.    [PIPE_PRIM_LINE_LOOP] = 2,
  451.    [PIPE_PRIM_LINE_STRIP] = 2,
  452.    [PIPE_PRIM_TRIANGLES] = 3,
  453.    [PIPE_PRIM_TRIANGLE_STRIP] = 3,
  454.    [PIPE_PRIM_TRIANGLE_FAN] = 3,
  455.    [PIPE_PRIM_QUADS] = 3,
  456.    [PIPE_PRIM_QUAD_STRIP] = 3,
  457.    [PIPE_PRIM_POLYGON] = 3,
  458.    [PIPE_PRIM_LINES_ADJACENCY] = 2,
  459.    [PIPE_PRIM_LINE_STRIP_ADJACENCY] = 2,
  460.    [PIPE_PRIM_TRIANGLES_ADJACENCY] = 3,
  461.    [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = 3
  462. };
  463.  
  464. static void
  465. nv50_draw_arrays(struct nv50_context *nv50,
  466.                  unsigned mode, unsigned start, unsigned count,
  467.                  unsigned instance_count)
  468. {
  469.    struct nouveau_pushbuf *push = nv50->base.pushbuf;
  470.    unsigned prim;
  471.  
  472.    if (nv50->state.index_bias) {
  473.       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
  474.       PUSH_DATA (push, 0);
  475.       if (nv50->screen->base.class_3d >= NV84_3D_CLASS) {
  476.          BEGIN_NV04(push, SUBC_3D(NV84_3D_VERTEX_ID_BASE), 1);
  477.          PUSH_DATA (push, 0);
  478.       }
  479.       nv50->state.index_bias = 0;
  480.    }
  481.  
  482.    prim = nv50_prim_gl(mode);
  483.  
  484.    while (instance_count--) {
  485.       BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
  486.       PUSH_DATA (push, prim);
  487.       BEGIN_NV04(push, NV50_3D(VERTEX_BUFFER_FIRST), 2);
  488.       PUSH_DATA (push, start);
  489.       PUSH_DATA (push, count);
  490.       BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
  491.       PUSH_DATA (push, 0);
  492.  
  493.       prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
  494.    }
  495. }
  496.  
  497. static void
  498. nv50_draw_elements_inline_u08(struct nouveau_pushbuf *push, const uint8_t *map,
  499.                               unsigned start, unsigned count)
  500. {
  501.    map += start;
  502.  
  503.    if (count & 3) {
  504.       unsigned i;
  505.       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), count & 3);
  506.       for (i = 0; i < (count & 3); ++i)
  507.          PUSH_DATA(push, *map++);
  508.       count &= ~3;
  509.    }
  510.    while (count) {
  511.       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
  512.  
  513.       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U8), nr);
  514.       for (i = 0; i < nr; ++i) {
  515.          PUSH_DATA(push,
  516.                    (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
  517.          map += 4;
  518.       }
  519.       count -= nr * 4;
  520.    }
  521. }
  522.  
  523. static void
  524. nv50_draw_elements_inline_u16(struct nouveau_pushbuf *push, const uint16_t *map,
  525.                               unsigned start, unsigned count)
  526. {
  527.    map += start;
  528.  
  529.    if (count & 1) {
  530.       count &= ~1;
  531.       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1);
  532.       PUSH_DATA (push, *map++);
  533.    }
  534.    while (count) {
  535.       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
  536.  
  537.       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr);
  538.       for (i = 0; i < nr; ++i) {
  539.          PUSH_DATA(push, (map[1] << 16) | map[0]);
  540.          map += 2;
  541.       }
  542.       count -= nr * 2;
  543.    }
  544. }
  545.  
  546. static void
  547. nv50_draw_elements_inline_u32(struct nouveau_pushbuf *push, const uint32_t *map,
  548.                               unsigned start, unsigned count)
  549. {
  550.    map += start;
  551.  
  552.    while (count) {
  553.       const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
  554.  
  555.       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), nr);
  556.       PUSH_DATAp(push, map, nr);
  557.  
  558.       map += nr;
  559.       count -= nr;
  560.    }
  561. }
  562.  
  563. static void
  564. nv50_draw_elements_inline_u32_short(struct nouveau_pushbuf *push,
  565.                                     const uint32_t *map,
  566.                                     unsigned start, unsigned count)
  567. {
  568.    map += start;
  569.  
  570.    if (count & 1) {
  571.       count--;
  572.       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1);
  573.       PUSH_DATA (push, *map++);
  574.    }
  575.    while (count) {
  576.       unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
  577.  
  578.       BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr);
  579.       for (i = 0; i < nr; ++i) {
  580.          PUSH_DATA(push, (map[1] << 16) | map[0]);
  581.          map += 2;
  582.       }
  583.       count -= nr * 2;
  584.    }
  585. }
  586.  
  587. static void
  588. nv50_draw_elements(struct nv50_context *nv50, boolean shorten,
  589.                    unsigned mode, unsigned start, unsigned count,
  590.                    unsigned instance_count, int32_t index_bias)
  591. {
  592.    struct nouveau_pushbuf *push = nv50->base.pushbuf;
  593.    unsigned prim;
  594.    const unsigned index_size = nv50->idxbuf.index_size;
  595.  
  596.    prim = nv50_prim_gl(mode);
  597.  
  598.    if (index_bias != nv50->state.index_bias) {
  599.       BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
  600.       PUSH_DATA (push, index_bias);
  601.       if (nv50->screen->base.class_3d >= NV84_3D_CLASS) {
  602.          BEGIN_NV04(push, SUBC_3D(NV84_3D_VERTEX_ID_BASE), 1);
  603.          PUSH_DATA (push, index_bias);
  604.       }
  605.       nv50->state.index_bias = index_bias;
  606.    }
  607.  
  608.    if (nv50->idxbuf.buffer) {
  609.       struct nv04_resource *buf = nv04_resource(nv50->idxbuf.buffer);
  610.       unsigned pb_start;
  611.       unsigned pb_bytes;
  612.       const unsigned base = (buf->offset + nv50->idxbuf.offset) & ~3;
  613.  
  614.       start += ((buf->offset + nv50->idxbuf.offset) & 3) >> (index_size >> 1);
  615.  
  616.       assert(nouveau_resource_mapped_by_gpu(nv50->idxbuf.buffer));
  617.  
  618.       /* This shouldn't have to be here. The going theory is that the buffer
  619.        * is being filled in by PGRAPH, and it's not done yet by the time it
  620.        * gets submitted to PFIFO, which in turn starts immediately prefetching
  621.        * the not-yet-written data. Ideally this wait would only happen on
  622.        * pushbuf submit, but it's probably not a big performance difference.
  623.        */
  624.       if (buf->fence_wr && !nouveau_fence_signalled(buf->fence_wr))
  625.          nouveau_fence_wait(buf->fence_wr);
  626.  
  627.       while (instance_count--) {
  628.          BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
  629.          PUSH_DATA (push, prim);
  630.  
  631.          nouveau_pushbuf_space(push, 8, 0, 1);
  632.  
  633.          switch (index_size) {
  634.          case 4:
  635.             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U32), count);
  636.             nouveau_pushbuf_data(push, buf->bo, base + start * 4, count * 4);
  637.             break;
  638.          case 2:
  639.             pb_start = (start & ~1) * 2;
  640.             pb_bytes = ((start + count + 1) & ~1) * 2 - pb_start;
  641.  
  642.             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1);
  643.             PUSH_DATA (push, (start << 31) | count);
  644.             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U16), pb_bytes / 4);
  645.             nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
  646.             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1);
  647.             PUSH_DATA (push, 0);
  648.             break;
  649.          default:
  650.             assert(index_size == 1);
  651.             pb_start = start & ~3;
  652.             pb_bytes = ((start + count + 3) & ~3) - pb_start;
  653.  
  654.             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1);
  655.             PUSH_DATA (push, (start << 30) | count);
  656.             BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U8), pb_bytes / 4);
  657.             nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
  658.             BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1);
  659.             PUSH_DATA (push, 0);
  660.             break;
  661.          }
  662.          BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
  663.          PUSH_DATA (push, 0);
  664.  
  665.          prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
  666.       }
  667.    } else {
  668.       const void *data = nv50->idxbuf.user_buffer;
  669.  
  670.       while (instance_count--) {
  671.          BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
  672.          PUSH_DATA (push, prim);
  673.          switch (index_size) {
  674.          case 1:
  675.             nv50_draw_elements_inline_u08(push, data, start, count);
  676.             break;
  677.          case 2:
  678.             nv50_draw_elements_inline_u16(push, data, start, count);
  679.             break;
  680.          case 4:
  681.             if (shorten)
  682.                nv50_draw_elements_inline_u32_short(push, data, start, count);
  683.             else
  684.                nv50_draw_elements_inline_u32(push, data, start, count);
  685.             break;
  686.          default:
  687.             assert(0);
  688.             return;
  689.          }
  690.          BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
  691.          PUSH_DATA (push, 0);
  692.  
  693.          prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
  694.       }
  695.    }
  696. }
  697.  
  698. static void
  699. nva0_draw_stream_output(struct nv50_context *nv50,
  700.                         const struct pipe_draw_info *info)
  701. {
  702.    struct nouveau_pushbuf *push = nv50->base.pushbuf;
  703.    struct nv50_so_target *so = nv50_so_target(info->count_from_stream_output);
  704.    struct nv04_resource *res = nv04_resource(so->pipe.buffer);
  705.    unsigned num_instances = info->instance_count;
  706.    unsigned mode = nv50_prim_gl(info->mode);
  707.  
  708.    if (unlikely(nv50->screen->base.class_3d < NVA0_3D_CLASS)) {
  709.       /* A proper implementation without waiting doesn't seem possible,
  710.        * so don't bother.
  711.        */
  712.       NOUVEAU_ERR("draw_stream_output not supported on pre-NVA0 cards\n");
  713.       return;
  714.    }
  715.  
  716.    if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
  717.       res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
  718.       PUSH_SPACE(push, 4);
  719.       BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
  720.       PUSH_DATA (push, 0);
  721.       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1);
  722.       PUSH_DATA (push, 0);
  723.    }
  724.  
  725.    assert(num_instances);
  726.    do {
  727.       PUSH_SPACE(push, 8);
  728.       BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
  729.       PUSH_DATA (push, mode);
  730.       BEGIN_NV04(push, NVA0_3D(DRAW_TFB_BASE), 1);
  731.       PUSH_DATA (push, 0);
  732.       BEGIN_NV04(push, NVA0_3D(DRAW_TFB_STRIDE), 1);
  733.       PUSH_DATA (push, 0);
  734.       BEGIN_NV04(push, NVA0_3D(DRAW_TFB_BYTES), 1);
  735.       nv50_query_pushbuf_submit(push, so->pq, 0x4);
  736.       BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1);
  737.       PUSH_DATA (push, 0);
  738.  
  739.       mode |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
  740.    } while (--num_instances);
  741. }
  742.  
  743. static void
  744. nv50_draw_vbo_kick_notify(struct nouveau_pushbuf *chan)
  745. {
  746.    struct nv50_screen *screen = chan->user_priv;
  747.  
  748.    nouveau_fence_update(&screen->base, TRUE);
  749.  
  750.    nv50_bufctx_fence(screen->cur_ctx->bufctx_3d, TRUE);
  751. }
  752.  
  753. void
  754. nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
  755. {
  756.    struct nv50_context *nv50 = nv50_context(pipe);
  757.    struct nouveau_pushbuf *push = nv50->base.pushbuf;
  758.    int i, s;
  759.  
  760.    /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */
  761.    nv50->vb_elt_first = info->min_index + info->index_bias;
  762.    nv50->vb_elt_limit = info->max_index - info->min_index;
  763.    nv50->instance_off = info->start_instance;
  764.    nv50->instance_max = info->instance_count - 1;
  765.  
  766.    /* For picking only a few vertices from a large user buffer, push is better,
  767.     * if index count is larger and we expect repeated vertices, suggest upload.
  768.     */
  769.    nv50->vbo_push_hint = /* the 64 is heuristic */
  770.       !(info->indexed && ((nv50->vb_elt_limit + 64) < info->count));
  771.  
  772.    if (nv50->vbo_user && !(nv50->dirty & (NV50_NEW_ARRAYS | NV50_NEW_VERTEX))) {
  773.       if (!!nv50->vbo_fifo != nv50->vbo_push_hint)
  774.          nv50->dirty |= NV50_NEW_ARRAYS;
  775.       else
  776.       if (!nv50->vbo_fifo)
  777.          nv50_update_user_vbufs(nv50);
  778.    }
  779.  
  780.    if (unlikely(nv50->num_so_targets && !nv50->gmtyprog))
  781.       nv50->state.prim_size = nv50_pipe_prim_to_prim_size[info->mode];
  782.  
  783.    nv50_state_validate(nv50, ~0, 8); /* 8 as minimum, we use flush_notify */
  784.  
  785.    push->kick_notify = nv50_draw_vbo_kick_notify;
  786.  
  787.    for (s = 0; s < 3 && !nv50->cb_dirty; ++s) {
  788.       uint32_t valid = nv50->constbuf_valid[s];
  789.  
  790.       while (valid && !nv50->cb_dirty) {
  791.          const unsigned i = ffs(valid) - 1;
  792.          struct pipe_resource *res;
  793.  
  794.          valid &= ~(1 << i);
  795.          if (nv50->constbuf[s][i].user)
  796.             continue;
  797.  
  798.          res = nv50->constbuf[s][i].u.buf;
  799.          if (!res)
  800.             continue;
  801.  
  802.          if (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
  803.             nv50->cb_dirty = TRUE;
  804.       }
  805.    }
  806.  
  807.    /* If there are any coherent constbufs, flush the cache */
  808.    if (nv50->cb_dirty) {
  809.       BEGIN_NV04(push, NV50_3D(CODE_CB_FLUSH), 1);
  810.       PUSH_DATA (push, 0);
  811.       nv50->cb_dirty = FALSE;
  812.    }
  813.  
  814.    if (nv50->vbo_fifo) {
  815.       nv50_push_vbo(nv50, info);
  816.       push->kick_notify = nv50_default_kick_notify;
  817.       nouveau_pushbuf_bufctx(push, NULL);
  818.       return;
  819.    }
  820.  
  821.    if (nv50->state.instance_base != info->start_instance) {
  822.       nv50->state.instance_base = info->start_instance;
  823.       /* NOTE: this does not affect the shader input, should it ? */
  824.       BEGIN_NV04(push, NV50_3D(VB_INSTANCE_BASE), 1);
  825.       PUSH_DATA (push, info->start_instance);
  826.    }
  827.  
  828.    for (i = 0; i < nv50->num_vtxbufs && !nv50->base.vbo_dirty; ++i) {
  829.       if (!nv50->vtxbuf[i].buffer)
  830.          continue;
  831.       if (nv50->vtxbuf[i].buffer->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
  832.          nv50->base.vbo_dirty = TRUE;
  833.    }
  834.  
  835.    if (!nv50->base.vbo_dirty && nv50->idxbuf.buffer &&
  836.        nv50->idxbuf.buffer->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
  837.       nv50->base.vbo_dirty = TRUE;
  838.  
  839.    if (nv50->base.vbo_dirty) {
  840.       BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1);
  841.       PUSH_DATA (push, 0);
  842.       nv50->base.vbo_dirty = FALSE;
  843.    }
  844.  
  845.    if (info->indexed) {
  846.       boolean shorten = info->max_index <= 65535;
  847.  
  848.       if (info->primitive_restart != nv50->state.prim_restart) {
  849.          if (info->primitive_restart) {
  850.             BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 2);
  851.             PUSH_DATA (push, 1);
  852.             PUSH_DATA (push, info->restart_index);
  853.  
  854.             if (info->restart_index > 65535)
  855.                shorten = FALSE;
  856.          } else {
  857.             BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 1);
  858.             PUSH_DATA (push, 0);
  859.          }
  860.          nv50->state.prim_restart = info->primitive_restart;
  861.       } else
  862.       if (info->primitive_restart) {
  863.          BEGIN_NV04(push, NV50_3D(PRIM_RESTART_INDEX), 1);
  864.          PUSH_DATA (push, info->restart_index);
  865.  
  866.          if (info->restart_index > 65535)
  867.             shorten = FALSE;
  868.       }
  869.  
  870.       nv50_draw_elements(nv50, shorten,
  871.                          info->mode, info->start, info->count,
  872.                          info->instance_count, info->index_bias);
  873.    } else
  874.    if (unlikely(info->count_from_stream_output)) {
  875.       nva0_draw_stream_output(nv50, info);
  876.    } else {
  877.       nv50_draw_arrays(nv50,
  878.                        info->mode, info->start, info->count,
  879.                        info->instance_count);
  880.    }
  881.    push->kick_notify = nv50_default_kick_notify;
  882.  
  883.    nv50_release_user_vbufs(nv50);
  884.  
  885.    nouveau_pushbuf_bufctx(push, NULL);
  886. }
  887.