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  1. /*
  2.  * Copyright 2011 Christoph Bumiller
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice shall be included in
  12.  * all copies or substantial portions of the Software.
  13.  *
  14.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20.  * OTHER DEALINGS IN THE SOFTWARE.
  21.  */
  22.  
  23. #include "codegen/nv50_ir_target_nvc0.h"
  24.  
  25. namespace nv50_ir {
  26.  
  27. Target *getTargetNVC0(unsigned int chipset)
  28. {
  29.    return new TargetNVC0(chipset);
  30. }
  31.  
  32. TargetNVC0::TargetNVC0(unsigned int card) :
  33.    Target(card < 0x110, false, card >= 0xe4)
  34. {
  35.    chipset = card;
  36.    initOpInfo();
  37. }
  38.  
  39. // BULTINS / LIBRARY FUNCTIONS:
  40.  
  41. // lazyness -> will just hardcode everything for the time being
  42.  
  43. #include "lib/gf100.asm.h"
  44. #include "lib/gk104.asm.h"
  45. #include "lib/gk110.asm.h"
  46.  
  47. void
  48. TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t *size) const
  49. {
  50.    switch (chipset & ~0xf) {
  51.    case 0xe0:
  52.       if (chipset < NVISA_GK20A_CHIPSET) {
  53.          *code = (const uint32_t *)&gk104_builtin_code[0];
  54.          *size = sizeof(gk104_builtin_code);
  55.          break;
  56.       }
  57.       /* fall-through for GK20A */
  58.    case 0xf0:
  59.    case 0x100:
  60.       *code = (const uint32_t *)&gk110_builtin_code[0];
  61.       *size = sizeof(gk110_builtin_code);
  62.       break;
  63.    default:
  64.       *code = (const uint32_t *)&gf100_builtin_code[0];
  65.       *size = sizeof(gf100_builtin_code);
  66.       break;
  67.    }
  68. }
  69.  
  70. uint32_t
  71. TargetNVC0::getBuiltinOffset(int builtin) const
  72. {
  73.    assert(builtin < NVC0_BUILTIN_COUNT);
  74.  
  75.    switch (chipset & ~0xf) {
  76.    case 0xe0:
  77.       if (chipset < NVISA_GK20A_CHIPSET)
  78.          return gk104_builtin_offsets[builtin];
  79.       /* fall-through for GK20A */
  80.    case 0xf0:
  81.    case 0x100:
  82.       return gk110_builtin_offsets[builtin];
  83.    default:
  84.       return gf100_builtin_offsets[builtin];
  85.    }
  86. }
  87.  
  88. struct opProperties
  89. {
  90.    operation op;
  91.    unsigned int mNeg   : 4;
  92.    unsigned int mAbs   : 4;
  93.    unsigned int mNot   : 4;
  94.    unsigned int mSat   : 4;
  95.    unsigned int fConst : 3;
  96.    unsigned int fImmd  : 4; // last bit indicates if full immediate is suppoted
  97. };
  98.  
  99. static const struct opProperties _initProps[] =
  100. {
  101.    //           neg  abs  not  sat  c[]  imm
  102.    { OP_ADD,    0x3, 0x3, 0x0, 0x8, 0x2, 0x2 | 0x8 },
  103.    { OP_SUB,    0x3, 0x3, 0x0, 0x0, 0x2, 0x2 | 0x8 },
  104.    { OP_MUL,    0x3, 0x0, 0x0, 0x8, 0x2, 0x2 | 0x8 },
  105.    { OP_MAX,    0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
  106.    { OP_MIN,    0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
  107.    { OP_MAD,    0x7, 0x0, 0x0, 0x8, 0x6, 0x2 | 0x8 }, // special c[] constraint
  108.    { OP_MADSP,  0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
  109.    { OP_ABS,    0x0, 0x0, 0x0, 0x0, 0x1, 0x0 },
  110.    { OP_NEG,    0x0, 0x1, 0x0, 0x0, 0x1, 0x0 },
  111.    { OP_CVT,    0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
  112.    { OP_CEIL,   0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
  113.    { OP_FLOOR,  0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
  114.    { OP_TRUNC,  0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
  115.    { OP_AND,    0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
  116.    { OP_OR,     0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
  117.    { OP_XOR,    0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
  118.    { OP_SHL,    0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
  119.    { OP_SHR,    0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
  120.    { OP_SET,    0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
  121.    { OP_SLCT,   0x4, 0x0, 0x0, 0x0, 0x6, 0x2 }, // special c[] constraint
  122.    { OP_PREEX2, 0x1, 0x1, 0x0, 0x0, 0x1, 0x1 },
  123.    { OP_PRESIN, 0x1, 0x1, 0x0, 0x0, 0x1, 0x1 },
  124.    { OP_COS,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
  125.    { OP_SIN,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
  126.    { OP_EX2,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
  127.    { OP_LG2,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
  128.    { OP_RCP,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
  129.    { OP_RSQ,    0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
  130.    { OP_DFDX,   0x1, 0x0, 0x0, 0x0, 0x0, 0x0 },
  131.    { OP_DFDY,   0x1, 0x0, 0x0, 0x0, 0x0, 0x0 },
  132.    { OP_CALL,   0x0, 0x0, 0x0, 0x0, 0x1, 0x0 },
  133.    { OP_POPCNT, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 },
  134.    { OP_INSBF,  0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
  135.    { OP_EXTBF,  0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
  136.    { OP_BFIND,  0x0, 0x0, 0x1, 0x0, 0x1, 0x1 },
  137.    { OP_PERMT,  0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
  138.    { OP_SET_AND, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
  139.    { OP_SET_OR, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
  140.    { OP_SET_XOR, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
  141.    // saturate only:
  142.    { OP_LINTERP, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0 },
  143.    { OP_PINTERP, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0 },
  144.    // nve4 ops:
  145.    { OP_SULDB,   0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
  146.    { OP_SUSTB,   0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
  147.    { OP_SUSTP,   0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
  148.    { OP_SUCLAMP, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
  149.    { OP_SUBFM,   0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
  150.    { OP_SUEAU,   0x0, 0x0, 0x0, 0x0, 0x6, 0x2 }
  151. };
  152.  
  153. void TargetNVC0::initOpInfo()
  154. {
  155.    unsigned int i, j;
  156.  
  157.    static const uint32_t commutative[(OP_LAST + 31) / 32] =
  158.    {
  159.       // ADD, MAD, MUL, AND, OR, XOR, MAX, MIN
  160.       0x0670ca00, 0x0000003f, 0x00000000, 0x00000000
  161.    };
  162.  
  163.    static const uint32_t shortForm[(OP_LAST + 31) / 32] =
  164.    {
  165.       // ADD, MAD, MUL, AND, OR, XOR, PRESIN, PREEX2, SFN, CVT, PINTERP, MOV
  166.       0x0670ca00, 0x00000000, 0x00000000, 0x00000000
  167.    };
  168.  
  169.    static const operation noDest[] =
  170.    {
  171.       OP_STORE, OP_WRSV, OP_EXPORT, OP_BRA, OP_CALL, OP_RET, OP_EXIT,
  172.       OP_DISCARD, OP_CONT, OP_BREAK, OP_PRECONT, OP_PREBREAK, OP_PRERET,
  173.       OP_JOIN, OP_JOINAT, OP_BRKPT, OP_MEMBAR, OP_EMIT, OP_RESTART,
  174.       OP_QUADON, OP_QUADPOP, OP_TEXBAR, OP_SUSTB, OP_SUSTP, OP_SUREDP,
  175.       OP_SUREDB, OP_BAR
  176.    };
  177.  
  178.    static const operation noPred[] =
  179.    {
  180.       OP_CALL, OP_PRERET, OP_QUADON, OP_QUADPOP,
  181.       OP_JOINAT, OP_PREBREAK, OP_PRECONT, OP_BRKPT
  182.    };
  183.  
  184.    for (i = 0; i < DATA_FILE_COUNT; ++i)
  185.       nativeFileMap[i] = (DataFile)i;
  186.    nativeFileMap[FILE_ADDRESS] = FILE_GPR;
  187.  
  188.    for (i = 0; i < OP_LAST; ++i) {
  189.       opInfo[i].variants = NULL;
  190.       opInfo[i].op = (operation)i;
  191.       opInfo[i].srcTypes = 1 << (int)TYPE_F32;
  192.       opInfo[i].dstTypes = 1 << (int)TYPE_F32;
  193.       opInfo[i].immdBits = 0;
  194.       opInfo[i].srcNr = operationSrcNr[i];
  195.  
  196.       for (j = 0; j < opInfo[i].srcNr; ++j) {
  197.          opInfo[i].srcMods[j] = 0;
  198.          opInfo[i].srcFiles[j] = 1 << (int)FILE_GPR;
  199.       }
  200.       opInfo[i].dstMods = 0;
  201.       opInfo[i].dstFiles = 1 << (int)FILE_GPR;
  202.  
  203.       opInfo[i].hasDest = 1;
  204.       opInfo[i].vector = (i >= OP_TEX && i <= OP_TEXCSAA);
  205.       opInfo[i].commutative = (commutative[i / 32] >> (i % 32)) & 1;
  206.       opInfo[i].pseudo = (i < OP_MOV);
  207.       opInfo[i].predicate = !opInfo[i].pseudo;
  208.       opInfo[i].flow = (i >= OP_BRA && i <= OP_JOIN);
  209.       opInfo[i].minEncSize = (shortForm[i / 32] & (1 << (i % 32))) ? 4 : 8;
  210.    }
  211.    for (i = 0; i < sizeof(noDest) / sizeof(noDest[0]); ++i)
  212.       opInfo[noDest[i]].hasDest = 0;
  213.    for (i = 0; i < sizeof(noPred) / sizeof(noPred[0]); ++i)
  214.       opInfo[noPred[i]].predicate = 0;
  215.  
  216.    for (i = 0; i < sizeof(_initProps) / sizeof(_initProps[0]); ++i) {
  217.       const struct opProperties *prop = &_initProps[i];
  218.  
  219.       for (int s = 0; s < 3; ++s) {
  220.          if (prop->mNeg & (1 << s))
  221.             opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_NEG;
  222.          if (prop->mAbs & (1 << s))
  223.             opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_ABS;
  224.          if (prop->mNot & (1 << s))
  225.             opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_NOT;
  226.          if (prop->fConst & (1 << s))
  227.             opInfo[prop->op].srcFiles[s] |= 1 << (int)FILE_MEMORY_CONST;
  228.          if (prop->fImmd & (1 << s))
  229.             opInfo[prop->op].srcFiles[s] |= 1 << (int)FILE_IMMEDIATE;
  230.          if (prop->fImmd & 8)
  231.             opInfo[prop->op].immdBits = 0xffffffff;
  232.       }
  233.       if (prop->mSat & 8)
  234.          opInfo[prop->op].dstMods = NV50_IR_MOD_SAT;
  235.    }
  236. }
  237.  
  238. unsigned int
  239. TargetNVC0::getFileSize(DataFile file) const
  240. {
  241.    switch (file) {
  242.    case FILE_NULL:          return 0;
  243.    case FILE_GPR:           return (chipset >= NVISA_GK20A_CHIPSET) ? 255 : 63;
  244.    case FILE_PREDICATE:     return 7;
  245.    case FILE_FLAGS:         return 1;
  246.    case FILE_ADDRESS:       return 0;
  247.    case FILE_IMMEDIATE:     return 0;
  248.    case FILE_MEMORY_CONST:  return 65536;
  249.    case FILE_SHADER_INPUT:  return 0x400;
  250.    case FILE_SHADER_OUTPUT: return 0x400;
  251.    case FILE_MEMORY_GLOBAL: return 0xffffffff;
  252.    case FILE_MEMORY_SHARED: return 16 << 10;
  253.    case FILE_MEMORY_LOCAL:  return 48 << 10;
  254.    case FILE_SYSTEM_VALUE:  return 32;
  255.    default:
  256.       assert(!"invalid file");
  257.       return 0;
  258.    }
  259. }
  260.  
  261. unsigned int
  262. TargetNVC0::getFileUnit(DataFile file) const
  263. {
  264.    if (file == FILE_GPR || file == FILE_ADDRESS || file == FILE_SYSTEM_VALUE)
  265.       return 2;
  266.    return 0;
  267. }
  268.  
  269. uint32_t
  270. TargetNVC0::getSVAddress(DataFile shaderFile, const Symbol *sym) const
  271. {
  272.    const int idx = sym->reg.data.sv.index;
  273.    const SVSemantic sv = sym->reg.data.sv.sv;
  274.  
  275.    const bool isInput = shaderFile == FILE_SHADER_INPUT;
  276.    const bool kepler = getChipset() >= NVISA_GK104_CHIPSET;
  277.  
  278.    switch (sv) {
  279.    case SV_POSITION:       return 0x070 + idx * 4;
  280.    case SV_INSTANCE_ID:    return 0x2f8;
  281.    case SV_VERTEX_ID:      return 0x2fc;
  282.    case SV_PRIMITIVE_ID:   return isInput ? 0x060 : 0x040;
  283.    case SV_LAYER:          return 0x064;
  284.    case SV_VIEWPORT_INDEX: return 0x068;
  285.    case SV_POINT_SIZE:     return 0x06c;
  286.    case SV_CLIP_DISTANCE:  return 0x2c0 + idx * 4;
  287.    case SV_POINT_COORD:    return 0x2e0 + idx * 4;
  288.    case SV_FACE:           return 0x3fc;
  289.    case SV_TESS_FACTOR:    return 0x000 + idx * 4;
  290.    case SV_TESS_COORD:     return 0x2f0 + idx * 4;
  291.    case SV_NTID:           return kepler ? (0x00 + idx * 4) : ~0;
  292.    case SV_NCTAID:         return kepler ? (0x0c + idx * 4) : ~0;
  293.    case SV_GRIDID:         return kepler ? 0x18 : ~0;
  294.    case SV_SAMPLE_INDEX:   return 0;
  295.    case SV_SAMPLE_POS:     return 0;
  296.    case SV_SAMPLE_MASK:    return 0;
  297.    default:
  298.       return 0xffffffff;
  299.    }
  300. }
  301.  
  302. bool
  303. TargetNVC0::insnCanLoad(const Instruction *i, int s,
  304.                         const Instruction *ld) const
  305. {
  306.    DataFile sf = ld->src(0).getFile();
  307.  
  308.    // immediate 0 can be represented by GPR $r63/$r255
  309.    if (sf == FILE_IMMEDIATE && ld->getSrc(0)->reg.data.u64 == 0)
  310.       return (!i->isPseudo() &&
  311.               !i->asTex() &&
  312.               i->op != OP_EXPORT && i->op != OP_STORE);
  313.  
  314.    if (s >= opInfo[i->op].srcNr)
  315.       return false;
  316.    if (!(opInfo[i->op].srcFiles[s] & (1 << (int)sf)))
  317.       return false;
  318.  
  319.    // indirect loads can only be done by OP_LOAD/VFETCH/INTERP on nvc0
  320.    if (ld->src(0).isIndirect(0))
  321.       return false;
  322.  
  323.    for (int k = 0; i->srcExists(k); ++k) {
  324.       if (i->src(k).getFile() == FILE_IMMEDIATE) {
  325.          if (k == 2 && i->op == OP_SUCLAMP) // special case
  326.             continue;
  327.          if (i->getSrc(k)->reg.data.u64 != 0)
  328.             return false;
  329.       } else
  330.       if (i->src(k).getFile() != FILE_GPR &&
  331.           i->src(k).getFile() != FILE_PREDICATE) {
  332.          return false;
  333.       }
  334.    }
  335.  
  336.    // not all instructions support full 32 bit immediates
  337.    if (sf == FILE_IMMEDIATE) {
  338.       Storage &reg = ld->getSrc(0)->asImm()->reg;
  339.  
  340.       if (typeSizeof(i->sType) > 4)
  341.          return false;
  342.       if (opInfo[i->op].immdBits != 0xffffffff) {
  343.          if (i->sType == TYPE_F32) {
  344.             if (reg.data.u32 & 0xfff)
  345.                return false;
  346.          } else
  347.          if (i->sType == TYPE_S32 || i->sType == TYPE_U32) {
  348.             // with u32, 0xfffff counts as 0xffffffff as well
  349.             if (reg.data.s32 > 0x7ffff || reg.data.s32 < -0x80000)
  350.                return false;
  351.          }
  352.       } else
  353.       if (i->op == OP_MAD || i->op == OP_FMA) {
  354.          // requires src == dst, cannot decide before RA
  355.          // (except if we implement more constraints)
  356.          if (ld->getSrc(0)->asImm()->reg.data.u32 & 0xfff)
  357.             return false;
  358.       } else
  359.       if (i->op == OP_ADD && i->sType == TYPE_F32) {
  360.          // add f32 LIMM cannot saturate
  361.          if (i->saturate && (reg.data.u32 & 0xfff))
  362.             return false;
  363.       }
  364.    }
  365.  
  366.    return true;
  367. }
  368.  
  369. bool
  370. TargetNVC0::isAccessSupported(DataFile file, DataType ty) const
  371. {
  372.    if (ty == TYPE_NONE)
  373.       return false;
  374.    if (file == FILE_MEMORY_CONST && getChipset() >= 0xe0) // wrong encoding ?
  375.       return typeSizeof(ty) <= 8;
  376.    if (ty == TYPE_B96)
  377.       return false;
  378.    return true;
  379. }
  380.  
  381. bool
  382. TargetNVC0::isOpSupported(operation op, DataType ty) const
  383. {
  384.    if ((op == OP_MAD || op == OP_FMA) && (ty != TYPE_F32))
  385.       return false;
  386.    if (op == OP_SAD && ty != TYPE_S32 && ty != TYPE_U32)
  387.       return false;
  388.    if (op == OP_POW || op == OP_SQRT || op == OP_DIV || op == OP_MOD)
  389.       return false;
  390.    return true;
  391. }
  392.  
  393. bool
  394. TargetNVC0::isModSupported(const Instruction *insn, int s, Modifier mod) const
  395. {
  396.    if (!isFloatType(insn->dType)) {
  397.       switch (insn->op) {
  398.       case OP_ABS:
  399.       case OP_NEG:
  400.       case OP_CVT:
  401.       case OP_CEIL:
  402.       case OP_FLOOR:
  403.       case OP_TRUNC:
  404.       case OP_AND:
  405.       case OP_OR:
  406.       case OP_XOR:
  407.       case OP_POPCNT:
  408.       case OP_BFIND:
  409.          break;
  410.       case OP_SET:
  411.          if (insn->sType != TYPE_F32)
  412.             return false;
  413.          break;
  414.       case OP_ADD:
  415.          if (mod.abs())
  416.             return false;
  417.          if (insn->src(s ? 0 : 1).mod.neg())
  418.             return false;
  419.          break;
  420.       case OP_SUB:
  421.          if (s == 0)
  422.             return insn->src(1).mod.neg() ? false : true;
  423.          break;
  424.       default:
  425.          return false;
  426.       }
  427.    }
  428.    if (s >= 3)
  429.       return false;
  430.    return (mod & Modifier(opInfo[insn->op].srcMods[s])) == mod;
  431. }
  432.  
  433. bool
  434. TargetNVC0::mayPredicate(const Instruction *insn, const Value *pred) const
  435. {
  436.    if (insn->getPredicate())
  437.       return false;
  438.    return opInfo[insn->op].predicate;
  439. }
  440.  
  441. bool
  442. TargetNVC0::isSatSupported(const Instruction *insn) const
  443. {
  444.    if (insn->op == OP_CVT)
  445.       return true;
  446.    if (!(opInfo[insn->op].dstMods & NV50_IR_MOD_SAT))
  447.       return false;
  448.  
  449.    if (insn->dType == TYPE_U32)
  450.       return (insn->op == OP_ADD) || (insn->op == OP_MAD);
  451.  
  452.    // add f32 LIMM cannot saturate
  453.    if (insn->op == OP_ADD && insn->sType == TYPE_F32) {
  454.       if (insn->getSrc(1)->asImm() &&
  455.           insn->getSrc(1)->reg.data.u32 & 0xfff)
  456.          return false;
  457.    }
  458.  
  459.    return insn->dType == TYPE_F32;
  460. }
  461.  
  462. bool
  463. TargetNVC0::isPostMultiplySupported(operation op, float f, int& e) const
  464. {
  465.    if (op != OP_MUL)
  466.       return false;
  467.    f = fabsf(f);
  468.    e = static_cast<int>(log2f(f));
  469.    if (e < -3 || e > 3)
  470.       return false;
  471.    return f == exp2f(static_cast<float>(e));
  472. }
  473.  
  474. // TODO: better values
  475. // this could be more precise, e.g. depending on the issue-to-read/write delay
  476. // of the depending instruction, but it's good enough
  477. int TargetNVC0::getLatency(const Instruction *i) const
  478. {
  479.    if (chipset >= 0xe4) {
  480.       if (i->dType == TYPE_F64 || i->sType == TYPE_F64)
  481.          return 20;
  482.       switch (i->op) {
  483.       case OP_LINTERP:
  484.       case OP_PINTERP:
  485.          return 15;
  486.       case OP_LOAD:
  487.          if (i->src(0).getFile() == FILE_MEMORY_CONST)
  488.             return 9;
  489.          // fall through
  490.       case OP_VFETCH:
  491.          return 24;
  492.       default:
  493.          if (Target::getOpClass(i->op) == OPCLASS_TEXTURE)
  494.             return 17;
  495.          if (i->op == OP_MUL && i->dType != TYPE_F32)
  496.             return 15;
  497.          return 9;
  498.       }
  499.    } else {
  500.       if (i->op == OP_LOAD) {
  501.          if (i->cache == CACHE_CV)
  502.             return 700;
  503.          return 48;
  504.       }
  505.       return 24;
  506.    }
  507.    return 32;
  508. }
  509.  
  510. // These are "inverse" throughput values, i.e. the number of cycles required
  511. // to issue a specific instruction for a full warp (32 threads).
  512. //
  513. // Assuming we have more than 1 warp in flight, a higher issue latency results
  514. // in a lower result latency since the MP will have spent more time with other
  515. // warps.
  516. // This also helps to determine the number of cycles between instructions in
  517. // a single warp.
  518. //
  519. int TargetNVC0::getThroughput(const Instruction *i) const
  520. {
  521.    // TODO: better values
  522.    if (i->dType == TYPE_F32) {
  523.       switch (i->op) {
  524.       case OP_ADD:
  525.       case OP_MUL:
  526.       case OP_MAD:
  527.       case OP_FMA:
  528.          return 1;
  529.       case OP_CVT:
  530.       case OP_CEIL:
  531.       case OP_FLOOR:
  532.       case OP_TRUNC:
  533.       case OP_SET:
  534.       case OP_SLCT:
  535.       case OP_MIN:
  536.       case OP_MAX:
  537.          return 2;
  538.       case OP_RCP:
  539.       case OP_RSQ:
  540.       case OP_LG2:
  541.       case OP_SIN:
  542.       case OP_COS:
  543.       case OP_PRESIN:
  544.       case OP_PREEX2:
  545.       default:
  546.          return 8;
  547.       }
  548.    } else
  549.    if (i->dType == TYPE_U32 || i->dType == TYPE_S32) {
  550.       switch (i->op) {
  551.       case OP_ADD:
  552.       case OP_AND:
  553.       case OP_OR:
  554.       case OP_XOR:
  555.       case OP_NOT:
  556.          return 1;
  557.       case OP_MUL:
  558.       case OP_MAD:
  559.       case OP_CVT:
  560.       case OP_SET:
  561.       case OP_SLCT:
  562.       case OP_SHL:
  563.       case OP_SHR:
  564.       case OP_NEG:
  565.       case OP_ABS:
  566.       case OP_MIN:
  567.       case OP_MAX:
  568.       default:
  569.          return 2;
  570.       }
  571.    } else
  572.    if (i->dType == TYPE_F64) {
  573.       return 2;
  574.    } else {
  575.       return 1;
  576.    }
  577. }
  578.  
  579. bool TargetNVC0::canDualIssue(const Instruction *a, const Instruction *b) const
  580. {
  581.    const OpClass clA = operationClass[a->op];
  582.    const OpClass clB = operationClass[b->op];
  583.  
  584.    if (getChipset() >= 0xe4) {
  585.       // not texturing
  586.       // not if the 2nd instruction isn't necessarily executed
  587.       if (clA == OPCLASS_TEXTURE || clA == OPCLASS_FLOW)
  588.          return false;
  589.       // anything with MOV
  590.       if (a->op == OP_MOV || b->op == OP_MOV)
  591.          return true;
  592.       if (clA == clB) {
  593.          // only F32 arith or integer additions
  594.          if (clA != OPCLASS_ARITH)
  595.             return false;
  596.          return (a->dType == TYPE_F32 || a->op == OP_ADD ||
  597.                  b->dType == TYPE_F32 || b->op == OP_ADD);
  598.       }
  599.       // nothing with TEXBAR
  600.       if (a->op == OP_TEXBAR || b->op == OP_TEXBAR)
  601.          return false;
  602.       // no loads and stores accessing the the same space
  603.       if ((clA == OPCLASS_LOAD && clB == OPCLASS_STORE) ||
  604.           (clB == OPCLASS_LOAD && clA == OPCLASS_STORE))
  605.          if (a->src(0).getFile() == b->src(0).getFile())
  606.             return false;
  607.       // no > 32-bit ops
  608.       if (typeSizeof(a->dType) > 4 || typeSizeof(b->dType) > 4 ||
  609.           typeSizeof(a->sType) > 4 || typeSizeof(b->sType) > 4)
  610.          return false;
  611.       return true;
  612.    } else {
  613.       return false; // info not needed (yet)
  614.    }
  615. }
  616.  
  617. } // namespace nv50_ir
  618.