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  1. /*
  2.  * Mesa 3-D graphics library
  3.  *
  4.  * Copyright (C) 2012-2013 LunarG, Inc.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included
  14.  * in all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22.  * DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors:
  25.  *    Chia-I Wu <olv@lunarg.com>
  26.  */
  27.  
  28. #include "genhw/genhw.h"
  29. #include "intel_winsys.h"
  30.  
  31. #include "ilo_debug.h"
  32. #include "ilo_dev.h"
  33.  
  34. /**
  35.  * Initialize the \p dev from \p winsys.  \p winsys is considered owned by \p
  36.  * dev and will be destroyed in \p ilo_dev_cleanup().
  37.  */
  38. bool
  39. ilo_dev_init(struct ilo_dev *dev, struct intel_winsys *winsys)
  40. {
  41.    const struct intel_winsys_info *info;
  42.  
  43.    info = intel_winsys_get_info(winsys);
  44.  
  45.    dev->winsys = winsys;
  46.    dev->devid = info->devid;
  47.    dev->aperture_total = info->aperture_total;
  48.    dev->aperture_mappable = info->aperture_mappable;
  49.    dev->has_llc = info->has_llc;
  50.    dev->has_address_swizzling = info->has_address_swizzling;
  51.    dev->has_logical_context = info->has_logical_context;
  52.    dev->has_ppgtt = info->has_ppgtt;
  53.    dev->has_timestamp = info->has_timestamp;
  54.    dev->has_gen7_sol_reset = info->has_gen7_sol_reset;
  55.  
  56.    if (!dev->has_logical_context) {
  57.       ilo_err("missing hardware logical context support\n");
  58.       return false;
  59.    }
  60.  
  61.    /*
  62.     * PIPE_CONTROL and MI_* use PPGTT writes on GEN7+ and privileged GGTT
  63.     * writes on GEN6.
  64.     *
  65.     * From the Sandy Bridge PRM, volume 1 part 3, page 101:
  66.     *
  67.     *     "[DevSNB] When Per-Process GTT Enable is set, it is assumed that all
  68.     *      code is in a secure environment, independent of address space.
  69.     *      Under this condition, this bit only specifies the address space
  70.     *      (GGTT or PPGTT). All commands are executed "as-is""
  71.     *
  72.     * We need PPGTT to be enabled on GEN6 too.
  73.     */
  74.    if (!dev->has_ppgtt) {
  75.       /* experiments show that it does not really matter... */
  76.       ilo_warn("PPGTT disabled\n");
  77.    }
  78.  
  79.    if (gen_is_bdw(info->devid) || gen_is_chv(info->devid)) {
  80.       dev->gen_opaque = ILO_GEN(8);
  81.       dev->gt = (gen_is_bdw(info->devid)) ? gen_get_bdw_gt(info->devid) : 1;
  82.       /* XXX random values */
  83.       if (dev->gt == 3) {
  84.          dev->eu_count = 48;
  85.          dev->thread_count = 336;
  86.          dev->urb_size = 384 * 1024;
  87.       } else if (dev->gt == 2) {
  88.          dev->eu_count = 24;
  89.          dev->thread_count = 168;
  90.          dev->urb_size = 384 * 1024;
  91.       } else {
  92.          dev->eu_count = 12;
  93.          dev->thread_count = 84;
  94.          dev->urb_size = 192 * 1024;
  95.       }
  96.    } else if (gen_is_hsw(info->devid)) {
  97.       /*
  98.        * From the Haswell PRM, volume 4, page 8:
  99.        *
  100.        *     "Description                    GT3      GT2      GT1.5    GT1
  101.        *      (...)
  102.        *      EUs (Total)                    40       20       12       10
  103.        *      Threads (Total)                280      140      84       70
  104.        *      (...)
  105.        *      URB Size (max, within L3$)     512KB    256KB    256KB    128KB
  106.        */
  107.       dev->gen_opaque = ILO_GEN(7.5);
  108.       dev->gt = gen_get_hsw_gt(info->devid);
  109.       if (dev->gt == 3) {
  110.          dev->eu_count = 40;
  111.          dev->thread_count = 280;
  112.          dev->urb_size = 512 * 1024;
  113.       } else if (dev->gt == 2) {
  114.          dev->eu_count = 20;
  115.          dev->thread_count = 140;
  116.          dev->urb_size = 256 * 1024;
  117.       } else {
  118.          dev->eu_count = 10;
  119.          dev->thread_count = 70;
  120.          dev->urb_size = 128 * 1024;
  121.       }
  122.    } else if (gen_is_ivb(info->devid) || gen_is_vlv(info->devid)) {
  123.       /*
  124.        * From the Ivy Bridge PRM, volume 1 part 1, page 18:
  125.        *
  126.        *     "Device             # of EUs        #Threads/EU
  127.        *      Ivy Bridge (GT2)   16              8
  128.        *      Ivy Bridge (GT1)   6               6"
  129.        *
  130.        * From the Ivy Bridge PRM, volume 4 part 2, page 17:
  131.        *
  132.        *     "URB Size    URB Rows    URB Rows when SLM Enabled
  133.        *      128k        4096        2048
  134.        *      256k        8096        4096"
  135.        */
  136.       dev->gen_opaque = ILO_GEN(7);
  137.       dev->gt = (gen_is_ivb(info->devid)) ? gen_get_ivb_gt(info->devid) : 1;
  138.       if (dev->gt == 2) {
  139.          dev->eu_count = 16;
  140.          dev->thread_count = 128;
  141.          dev->urb_size = 256 * 1024;
  142.       } else {
  143.          dev->eu_count = 6;
  144.          dev->thread_count = 36;
  145.          dev->urb_size = 128 * 1024;
  146.       }
  147.    } else if (gen_is_snb(info->devid)) {
  148.       /*
  149.        * From the Sandy Bridge PRM, volume 1 part 1, page 22:
  150.        *
  151.        *     "Device             # of EUs        #Threads/EU
  152.        *      SNB GT2            12              5
  153.        *      SNB GT1            6               4"
  154.        *
  155.        * From the Sandy Bridge PRM, volume 4 part 2, page 18:
  156.        *
  157.        *     "[DevSNB]: The GT1 product's URB provides 32KB of storage,
  158.        *      arranged as 1024 256-bit rows. The GT2 product's URB provides
  159.        *      64KB of storage, arranged as 2048 256-bit rows. A row
  160.        *      corresponds in size to an EU GRF register. Read/write access to
  161.        *      the URB is generally supported on a row-granular basis."
  162.        */
  163.       dev->gen_opaque = ILO_GEN(6);
  164.       dev->gt = gen_get_snb_gt(info->devid);
  165.       if (dev->gt == 2) {
  166.          dev->eu_count = 12;
  167.          dev->thread_count = 60;
  168.          dev->urb_size = 64 * 1024;
  169.       } else {
  170.          dev->eu_count = 6;
  171.          dev->thread_count = 24;
  172.          dev->urb_size = 32 * 1024;
  173.       }
  174.    } else {
  175.       ilo_err("unknown GPU generation\n");
  176.       return false;
  177.    }
  178.  
  179.    return true;
  180. }
  181.  
  182. void
  183. ilo_dev_cleanup(struct ilo_dev *dev)
  184. {
  185.    intel_winsys_destroy(dev->winsys);
  186. }
  187.