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  1.  
  2. #include <assert.h>
  3. #include <stdlib.h>
  4. #include <memory.h>
  5.  
  6. #include <intel_bufmgr.h>
  7. //#include "xf86.h"
  8. #include "uxa/intel.h"
  9. #include "i830_reg.h"
  10. #include "i965_reg.h"
  11.  
  12. /* bring in brw structs */
  13. #include "brw_defines.h"
  14. #include "brw_structs.h"
  15.  
  16. #include "i915_pciids.h"
  17. #include <pixlib2.h>
  18. #include <kos32sys.h>
  19.  
  20. #define PictOpClear             0
  21. #define PictOpSrc               1
  22. #define PictOpDst               2
  23. #define PictOpOver              3
  24. #define PictOpOverReverse       4
  25. #define PictOpIn                5
  26. #define PictOpInReverse         6
  27. #define PictOpOut               7
  28. #define PictOpOutReverse        8
  29. #define PictOpAtop              9
  30. #define PictOpAtopReverse       10
  31. #define PictOpXor               11
  32. #define PictOpAdd               12
  33. #define PictOpSaturate          13
  34. #define PictOpMaximum           13
  35.  
  36. static int    tls_mask;
  37.  
  38. intel_screen_private *driverPrivate;
  39. __LOCK_INIT_RECURSIVE(, __uxa_lock);
  40.  
  41. #define DBG printf
  42.  
  43. typedef struct
  44. {
  45.     struct list     entry;
  46.     uint32_t        width;
  47.     uint32_t        height;
  48.     void           *data;
  49.     uint32_t        pitch;
  50.     drm_intel_bo   *bo;
  51.     uint32_t        bo_size;
  52.     uint32_t        flags;
  53. }surface_t;
  54.  
  55. #define to_surface(x) (surface_t*)((x)->handle)
  56.  
  57. struct _Pixmap fb_pixmap;
  58.  
  59. struct list sf_list;
  60.  
  61. int uxa_update_fb(struct intel_screen_private *intel);
  62.  
  63. static void i830_done_composite(PixmapPtr dest)
  64. {
  65.         intel_screen_private *intel = intel_get_screen_private();
  66.  
  67.         if (intel->vertex_flush)
  68.                 intel->vertex_flush(intel);
  69.  
  70. //      intel_debug_flush(scrn);
  71. }
  72.  
  73. int uxa_bitmap_from_handle(bitmap_t *bitmap, uint32_t handle)
  74. {
  75.     struct intel_screen_private *intel = intel_get_screen_private();
  76.     drm_intel_bo *bo;
  77.     surface_t    *sf;
  78.     unsigned int size;
  79.  
  80.     bitmap->handle = 0;
  81.  
  82.     __lock_acquire_recursive(__uxa_lock);
  83.     list_for_each_entry(sf, &sf_list, entry)
  84.     {
  85.         if (sf->bo->handle == handle)
  86.         {
  87.             bitmap->handle = (uint32_t)sf;
  88.             break;
  89.         }
  90.     }
  91.     __lock_release_recursive(__uxa_lock);
  92.  
  93.     if(bitmap->handle)
  94.         return 0;
  95.  
  96.     sf = malloc(sizeof(*sf));
  97.     if(sf == NULL)
  98.         goto err_1;
  99.  
  100.     size = bitmap->pitch * bitmap->height;
  101.  
  102.     bo = bo_create_from_gem_handle(intel->bufmgr, size, handle);
  103.  
  104.     sf->width   = bitmap->width;
  105.     sf->height  = bitmap->height;
  106.     sf->data    = NULL;
  107.     sf->pitch   = bitmap->pitch;
  108.     sf->bo      = bo;
  109.     sf->bo_size = size;
  110.     sf->flags   = bitmap->flags;
  111.  
  112.     bitmap->handle = (uint32_t)sf;
  113.  
  114.     return 0;
  115.  
  116. err_1:
  117.  
  118.     return -1;
  119. };
  120.  
  121. void uxa_set_bo_handle(bitmap_t *bitmap, int handle)
  122. {
  123.     uxa_bitmap_from_handle(bitmap, handle);
  124. };
  125.  
  126.  
  127. int uxa_blit_tex(bitmap_t *bitmap, int scale, int vsync,
  128.                  int dst_x, int dst_y,int w, int h, int src_x, int src_y)
  129. {
  130. //    DBG("%s\n", __FUNCTION__);
  131.  
  132.     struct _Pixmap pixSrc, pixMask;
  133.     struct intel_pixmap privSrc;
  134.     struct _Picture pictSrc, pictDst;
  135.         struct intel_screen_private *intel = intel_get_screen_private();
  136.  
  137.     surface_t *sf = to_surface(bitmap);
  138.  
  139.     int winx, winy;
  140.  
  141.     char proc_info[1024];
  142.     get_proc_info(proc_info);
  143.     winx = *(uint32_t*)(proc_info+34);
  144.     winy = *(uint32_t*)(proc_info+38);
  145.  
  146.     memset(&pixSrc,  0, sizeof(pixSrc));
  147.     memset(&pixMask, 0, sizeof(pixMask));
  148.     memset(&privSrc, 0, sizeof(pixSrc));
  149.  
  150.     memset(&pictSrc, 0, sizeof(pictSrc));
  151.     memset(&pictDst, 0, sizeof(pictDst));
  152.  
  153.     pixSrc.drawable.bitsPerPixel = 32;
  154.     pixSrc.drawable.width        = sf->width;
  155.     pixSrc.drawable.height       = sf->height;
  156.     pixSrc.devKind               = sf->pitch;
  157.     pixSrc.private               = &privSrc;
  158.  
  159.     list_init(&privSrc.batch);
  160.     privSrc.bo = sf->bo;
  161.     privSrc.stride = sf->pitch;
  162.     privSrc.tiling = I915_TILING_X;
  163.  
  164.     pictSrc.format     = PICT_x8r8g8b8;
  165.     pictSrc.filter     = PictFilterNearest;
  166.     pictSrc.repeatType = RepeatNone;
  167.  
  168.     pictDst.format     = PICT_a8r8g8b8;
  169.     pictDst.filter = PictFilterNearest;
  170.     pictDst.repeatType = RepeatNone;
  171.  
  172.     uxa_update_fb(intel);
  173.  
  174.     i965_prepare_composite(PictOpSrc, &pictSrc, NULL, &pictDst,
  175.                            &pixSrc, NULL, &fb_pixmap);
  176.  
  177.     i965_composite(&fb_pixmap, src_x, src_y, 0, 0,
  178.                     dst_x+winx, dst_y+winy, w, h);
  179.  
  180.     i830_done_composite(&fb_pixmap);
  181.  
  182.         intel_batch_submit();
  183.  
  184. //    DBG("%s done\n", __FUNCTION__);
  185.  
  186.     return 0;
  187. };
  188.  
  189.  
  190. int uxa_init_fb(struct intel_screen_private *intel)
  191. {
  192.     struct drm_i915_fb_info fb;
  193.     static struct intel_pixmap ipix;
  194.     int ret;
  195.  
  196.     memset(&fb, 0, sizeof(fb));
  197.  
  198.     ret = drmIoctl(intel->scrn, SRV_FBINFO, &fb);
  199.         if( ret != 0 )
  200.             return ret;
  201.  
  202.     intel->front_buffer = intel_bo_gem_create_from_name(intel->bufmgr,"frontbuffer", fb.name);
  203.     if(intel->front_buffer == NULL)
  204.         return -1;
  205.  
  206.     ipix.bo = intel->front_buffer;
  207.     list_init(&ipix.batch);
  208.     ipix.stride = fb.pitch;
  209.     ipix.tiling = fb.tiling;
  210.     ipix.pinned = PIN_SCANOUT;
  211.  
  212.     printf("create frontbuffer name %d bo %x\n", fb.name, ipix.bo);
  213.     printf("size %d, offset %d handle %d\n",ipix.bo->size, ipix.bo->offset, ipix.bo->handle);
  214.  
  215.     fb_pixmap.drawable.bitsPerPixel = 32;
  216.     fb_pixmap.drawable.width  = fb.width;
  217.     fb_pixmap.drawable.height = fb.height;
  218.     fb_pixmap.devKind = fb.pitch;
  219.     fb_pixmap.private = &ipix;
  220.  
  221.     return 0;
  222. }
  223.  
  224. int uxa_update_fb(struct intel_screen_private *intel)
  225. {
  226.     struct drm_i915_fb_info fb;
  227.     struct intel_pixmap *ipix;
  228.     size_t size;
  229.     int ret;
  230.  
  231. //    DBG("%s\n", __FUNCTION__);
  232.  
  233.     ret = drmIoctl(intel->scrn, SRV_FBINFO, &fb);
  234.         if( ret != 0 )
  235.             return ret;
  236.  
  237.     ipix = (struct intel_pixmap*)fb_pixmap.private;
  238.  
  239.     list_init(&ipix->batch);
  240.     ipix->stride = fb.pitch;
  241.     ipix->tiling = fb.tiling;
  242.  
  243.     fb_pixmap.drawable.width  = fb.width;
  244.     fb_pixmap.drawable.height = fb.height;
  245.     fb_pixmap.devKind = fb.pitch;
  246.  
  247.     return 0;
  248. };
  249.  
  250. int uxa_init(uint32_t service)
  251. {
  252.     static struct pci_device device;
  253.         struct intel_screen_private *intel = intel_get_screen_private();
  254.  
  255.     ioctl_t   io;
  256.     int caps = 0;
  257.  
  258.     DBG("%s\n", __FUNCTION__);
  259.  
  260.     __lock_acquire_recursive(__uxa_lock);
  261.  
  262.     if(intel)
  263.         goto done;
  264.  
  265.     io.handle   = service;
  266.     io.io_code  = SRV_GET_PCI_INFO;
  267.     io.input    = &device;
  268.     io.inp_size = sizeof(device);
  269.     io.output   = NULL;
  270.     io.out_size = 0;
  271.  
  272.     if (call_service(&io)!=0)
  273.         goto err1;
  274.  
  275.     intel = (intel_screen_private*)malloc(sizeof(*intel));
  276.     if (intel == NULL)
  277.         goto err1;
  278.  
  279.     list_init(&sf_list);
  280.  
  281.     driverPrivate = intel;
  282.     memset(intel, 0, sizeof(*intel));
  283.  
  284. //    sna->cpu_features = sna_cpu_detect();
  285.  
  286.     intel->PciInfo = &device;
  287.         intel->info = intel_detect_chipset(intel->PciInfo);
  288.     intel->scrn = service;
  289.  
  290.     intel->bufmgr = intel_bufmgr_gem_init(service, 8192);
  291.     if(intel->bufmgr == NULL)
  292.     {
  293.                 printf("Memory manager initialization failed\n");
  294.                 goto err1;
  295.     };
  296.  
  297.         list_init(&intel->batch_pixmaps);
  298.  
  299.         if ((INTEL_INFO(intel)->gen == 060)) {
  300.                 intel->wa_scratch_bo =
  301.                         drm_intel_bo_alloc(intel->bufmgr, "wa scratch",
  302.                                            4096, 4096);
  303.         }
  304.  
  305.     if( uxa_init_fb(intel) != 0)
  306.         goto err1;
  307.  
  308.         intel_batch_init();
  309.  
  310.         if (INTEL_INFO(intel)->gen >= 040)
  311.                 gen4_render_state_init();
  312.  
  313.         if (!intel_uxa_init()) {
  314.                 printf("Hardware acceleration initialization failed\n");
  315.                 goto err1;
  316.         }
  317.  
  318.     tls_mask = tls_alloc();
  319.  
  320. //    printf("tls mask %x\n", tls_mask);
  321.  
  322. done:
  323. //    caps = sna_device->render.caps;
  324.  
  325. err1:
  326.     __lock_release_recursive(__uxa_lock);
  327.  
  328.     LEAVE();
  329.     return caps;
  330. }
  331.  
  332.  
  333.  
  334. static void
  335. gen6_context_switch(intel_screen_private *intel,
  336.                     int new_mode)
  337. {
  338.         intel_batch_submit(intel->scrn);
  339. }
  340.  
  341. static void
  342. gen5_context_switch(intel_screen_private *intel,
  343.                     int new_mode)
  344. {
  345.         /* Ironlake has a limitation that a 3D or Media command can't
  346.          * be the first command after a BLT, unless it's
  347.          * non-pipelined.  Instead of trying to track it and emit a
  348.          * command at the right time, we just emit a dummy
  349.          * non-pipelined 3D instruction after each blit.
  350.          */
  351.  
  352.         if (new_mode == I915_EXEC_BLT) {
  353.                 OUT_BATCH(MI_FLUSH |
  354.                           MI_STATE_INSTRUCTION_CACHE_FLUSH |
  355.                           MI_INHIBIT_RENDER_CACHE_FLUSH);
  356.         } else {
  357.                 OUT_BATCH(CMD_POLY_STIPPLE_OFFSET << 16);
  358.                 OUT_BATCH(0);
  359.         }
  360. }
  361.  
  362. static void
  363. gen4_context_switch(intel_screen_private *intel,
  364.                     int new_mode)
  365. {
  366.         if (new_mode == I915_EXEC_BLT) {
  367.                 OUT_BATCH(MI_FLUSH |
  368.                           MI_STATE_INSTRUCTION_CACHE_FLUSH |
  369.                           MI_INHIBIT_RENDER_CACHE_FLUSH);
  370.         }
  371. }
  372.  
  373. static void
  374. intel_limits_init(intel_screen_private *intel)
  375. {
  376.         /* Limits are described in the BLT engine chapter under Graphics Data Size
  377.          * Limitations, and the descriptions of SURFACE_STATE, 3DSTATE_BUFFER_INFO,
  378.          * 3DSTATE_DRAWING_RECTANGLE, 3DSTATE_MAP_INFO, and 3DSTATE_MAP_INFO.
  379.          *
  380.          * i845 through i965 limits 2D rendering to 65536 lines and pitch of 32768.
  381.          *
  382.          * i965 limits 3D surface to (2*element size)-aligned offset if un-tiled.
  383.          * i965 limits 3D surface to 4kB-aligned offset if tiled.
  384.          * i965 limits 3D surfaces to w,h of ?,8192.
  385.          * i965 limits 3D surface to pitch of 1B - 128kB.
  386.          * i965 limits 3D surface pitch alignment to 1 or 2 times the element size.
  387.          * i965 limits 3D surface pitch alignment to 512B if tiled.
  388.          * i965 limits 3D destination drawing rect to w,h of 8192,8192.
  389.          *
  390.          * i915 limits 3D textures to 4B-aligned offset if un-tiled.
  391.          * i915 limits 3D textures to ~4kB-aligned offset if tiled.
  392.          * i915 limits 3D textures to width,height of 2048,2048.
  393.          * i915 limits 3D textures to pitch of 16B - 8kB, in dwords.
  394.          * i915 limits 3D destination to ~4kB-aligned offset if tiled.
  395.          * i915 limits 3D destination to pitch of 16B - 8kB, in dwords, if un-tiled.
  396.          * i915 limits 3D destination to pitch 64B-aligned if used with depth.
  397.          * i915 limits 3D destination to pitch of 512B - 8kB, in tiles, if tiled.
  398.          * i915 limits 3D destination to POT aligned pitch if tiled.
  399.          * i915 limits 3D destination drawing rect to w,h of 2048,2048.
  400.          *
  401.          * i845 limits 3D textures to 4B-aligned offset if un-tiled.
  402.          * i845 limits 3D textures to ~4kB-aligned offset if tiled.
  403.          * i845 limits 3D textures to width,height of 2048,2048.
  404.          * i845 limits 3D textures to pitch of 4B - 8kB, in dwords.
  405.          * i845 limits 3D destination to 4B-aligned offset if un-tiled.
  406.          * i845 limits 3D destination to ~4kB-aligned offset if tiled.
  407.          * i845 limits 3D destination to pitch of 8B - 8kB, in dwords.
  408.          * i845 limits 3D destination drawing rect to w,h of 2048,2048.
  409.          *
  410.          * For the tiled issues, the only tiled buffer we draw to should be
  411.          * the front, which will have an appropriate pitch/offset already set up,
  412.          * so UXA doesn't need to worry.
  413.          */
  414.         if (INTEL_INFO(intel)->gen >= 040) {
  415.                 intel->accel_pixmap_offset_alignment = 4 * 2;
  416.                 intel->accel_max_x = 8192;
  417.                 intel->accel_max_y = 8192;
  418.         } else {
  419.                 intel->accel_pixmap_offset_alignment = 4;
  420.                 intel->accel_max_x = 2048;
  421.                 intel->accel_max_y = 2048;
  422.         }
  423. }
  424.  
  425.  
  426. Bool intel_uxa_init()
  427. {
  428.         intel_screen_private *intel = intel_get_screen_private();
  429.  
  430.         intel_limits_init(intel);
  431.  
  432.         intel->prim_offset = 0;
  433.         intel->vertex_count = 0;
  434.         intel->vertex_offset = 0;
  435.         intel->vertex_used = 0;
  436.         intel->floats_per_vertex = 0;
  437.         intel->last_floats_per_vertex = 0;
  438.         intel->vertex_bo = NULL;
  439.         intel->surface_used = 0;
  440.         intel->surface_reloc = 0;
  441.  
  442. /*
  443.         intel->uxa_driver->check_composite = i965_check_composite;
  444.         intel->uxa_driver->check_composite_texture = i965_check_composite_texture;
  445.         intel->uxa_driver->prepare_composite = i965_prepare_composite;
  446.         intel->uxa_driver->composite = i965_composite;
  447.         intel->uxa_driver->done_composite = i830_done_composite;
  448. */
  449.         intel->vertex_flush = i965_vertex_flush;
  450.         intel->batch_flush = i965_batch_flush;
  451.         intel->batch_commit_notify = i965_batch_commit_notify;
  452.  
  453.         if (IS_GEN4(intel)) {
  454.                 intel->context_switch = gen4_context_switch;
  455.         } else if (IS_GEN5(intel)) {
  456.                 intel->context_switch = gen5_context_switch;
  457.         } else {
  458.                 intel->context_switch = gen6_context_switch;
  459.         }
  460.  
  461.         return TRUE;
  462. }
  463.  
  464.  
  465. static const struct intel_device_info intel_generic_info = {
  466.         .gen = -1,
  467. };
  468.  
  469. static const struct intel_device_info intel_i915_info = {
  470.         .gen = 030,
  471. };
  472. static const struct intel_device_info intel_i945_info = {
  473.         .gen = 031,
  474. };
  475.  
  476. static const struct intel_device_info intel_g33_info = {
  477.         .gen = 033,
  478. };
  479.  
  480. static const struct intel_device_info intel_i965_info = {
  481.         .gen = 040,
  482. };
  483.  
  484. static const struct intel_device_info intel_g4x_info = {
  485.         .gen = 045,
  486. };
  487.  
  488. static const struct intel_device_info intel_ironlake_info = {
  489.         .gen = 050,
  490. };
  491.  
  492. static const struct intel_device_info intel_sandybridge_info = {
  493.         .gen = 060,
  494. };
  495.  
  496. static const struct intel_device_info intel_ivybridge_info = {
  497.         .gen = 070,
  498. };
  499.  
  500. static const struct intel_device_info intel_valleyview_info = {
  501.         .gen = 071,
  502. };
  503.  
  504. static const struct intel_device_info intel_haswell_info = {
  505.         .gen = 075,
  506. };
  507.  
  508. #define INTEL_DEVICE_MATCH(d,i) \
  509.     { 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0x3 << 16, 0xff << 16, (intptr_t)(i) }
  510.  
  511.  
  512. static const struct pci_id_match intel_device_match[] = {
  513.  
  514.         INTEL_I915G_IDS(&intel_i915_info),
  515.         INTEL_I915GM_IDS(&intel_i915_info),
  516.         INTEL_I945G_IDS(&intel_i945_info),
  517.         INTEL_I945GM_IDS(&intel_i945_info),
  518.  
  519.         INTEL_G33_IDS(&intel_g33_info),
  520.         INTEL_PINEVIEW_IDS(&intel_g33_info),
  521.  
  522.         INTEL_I965G_IDS(&intel_i965_info),
  523.         INTEL_I965GM_IDS(&intel_i965_info),
  524.  
  525.         INTEL_G45_IDS(&intel_g4x_info),
  526.         INTEL_GM45_IDS(&intel_g4x_info),
  527.  
  528.         INTEL_IRONLAKE_D_IDS(&intel_ironlake_info),
  529.         INTEL_IRONLAKE_M_IDS(&intel_ironlake_info),
  530.  
  531.         INTEL_SNB_D_IDS(&intel_sandybridge_info),
  532.         INTEL_SNB_M_IDS(&intel_sandybridge_info),
  533.  
  534.         INTEL_IVB_D_IDS(&intel_ivybridge_info),
  535.         INTEL_IVB_M_IDS(&intel_ivybridge_info),
  536.  
  537.         INTEL_HSW_D_IDS(&intel_haswell_info),
  538.         INTEL_HSW_M_IDS(&intel_haswell_info),
  539.  
  540.         INTEL_VLV_D_IDS(&intel_valleyview_info),
  541.         INTEL_VLV_M_IDS(&intel_valleyview_info),
  542.  
  543.         INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info),
  544.  
  545.         { 0, 0, 0 },
  546. };
  547.  
  548. const struct pci_id_match *PciDevMatch(uint16_t dev,const struct pci_id_match *list)
  549. {
  550.     while(list->device_id)
  551.     {
  552.         if(dev==list->device_id)
  553.             return list;
  554.         list++;
  555.     }
  556.     return NULL;
  557. }
  558.  
  559.  
  560. const struct intel_device_info *
  561. intel_detect_chipset(struct pci_device *pci)
  562. {
  563.     const struct pci_id_match *ent = NULL;
  564.  
  565.     ent = PciDevMatch(pci->device_id, intel_device_match);
  566.  
  567.     if(ent != NULL)
  568.         return (const struct intel_device_info*)ent->match_data;
  569.     else
  570.         return &intel_generic_info;
  571. }
  572.  
  573.