Subversion Repositories Kolibri OS

Rev

Rev 6084 | Rev 6103 | Go to most recent revision | Blame | Compare with Previous | Last modification | View Log | Download | RSS feed

  1. /*
  2.  * Copyright © 2011 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20.  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21.  * SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25.  *
  26.  * New plane/sprite handling.
  27.  *
  28.  * The older chips had a separate interface for programming plane related
  29.  * registers; newer ones are much simpler and we can use the new DRM plane
  30.  * support.
  31.  */
  32. #include <drm/drmP.h>
  33. #include <drm/drm_crtc.h>
  34. #include <drm/drm_fourcc.h>
  35. #include <drm/drm_rect.h>
  36. #include <drm/drm_atomic.h>
  37. #include <drm/drm_plane_helper.h>
  38. #include "intel_drv.h"
  39. #include <drm/i915_drm.h>
  40. #include "i915_drv.h"
  41.  
  42. static bool
  43. format_is_yuv(uint32_t format)
  44. {
  45.         switch (format) {
  46.         case DRM_FORMAT_YUYV:
  47.         case DRM_FORMAT_UYVY:
  48.         case DRM_FORMAT_VYUY:
  49.         case DRM_FORMAT_YVYU:
  50.                 return true;
  51.         default:
  52.                 return false;
  53.         }
  54. }
  55.  
  56. static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
  57.                               int usecs)
  58. {
  59.         /* paranoia */
  60.         if (!adjusted_mode->crtc_htotal)
  61.                 return 1;
  62.  
  63.         return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
  64.                             1000 * adjusted_mode->crtc_htotal);
  65. }
  66.  
  67. /**
  68.  * intel_pipe_update_start() - start update of a set of display registers
  69.  * @crtc: the crtc of which the registers are going to be updated
  70.  * @start_vbl_count: vblank counter return pointer used for error checking
  71.  *
  72.  * Mark the start of an update to pipe registers that should be updated
  73.  * atomically regarding vblank. If the next vblank will happens within
  74.  * the next 100 us, this function waits until the vblank passes.
  75.  *
  76.  * After a successful call to this function, interrupts will be disabled
  77.  * until a subsequent call to intel_pipe_update_end(). That is done to
  78.  * avoid random delays. The value written to @start_vbl_count should be
  79.  * supplied to intel_pipe_update_end() for error checking.
  80.  */
  81. void intel_pipe_update_start(struct intel_crtc *crtc)
  82. {
  83.         struct drm_device *dev = crtc->base.dev;
  84.         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
  85.         enum pipe pipe = crtc->pipe;
  86.         long timeout = msecs_to_jiffies_timeout(1);
  87.         int scanline, min, max, vblank_start;
  88. #if 0
  89. //   wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  90. //   DEFINE_WAIT(wait);
  91.  
  92.         vblank_start = adjusted_mode->crtc_vblank_start;
  93.         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  94.                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
  95.  
  96.         /* FIXME needs to be calibrated sensibly */
  97.         min = vblank_start - usecs_to_scanlines(adjusted_mode, 100);
  98.         max = vblank_start - 1;
  99.  
  100.         if (min <= 0 || max <= 0)
  101.                 return;
  102.  
  103. //   if (WARN_ON(drm_vblank_get(dev, pipe)))
  104. //       return false;
  105.  
  106.         crtc->debug.min_vbl = min;
  107.         crtc->debug.max_vbl = max;
  108.         trace_i915_pipe_update_start(crtc);
  109.  
  110.         for (;;) {
  111.                 /*
  112.                  * prepare_to_wait() has a memory barrier, which guarantees
  113.                  * other CPUs can see the task state update by the time we
  114.                  * read the scanline.
  115.                  */
  116.                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
  117.  
  118.                 scanline = intel_get_crtc_scanline(crtc);
  119.                 if (scanline < min || scanline > max)
  120.                         break;
  121.  
  122.                 if (timeout <= 0) {
  123.                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
  124.                                   pipe_name(crtc->pipe));
  125.                         break;
  126.                 }
  127.  
  128. //       local_irq_enable();
  129.  
  130.         schedule_timeout(timeout);
  131.         timeout = 0;
  132. //       local_irq_disable();
  133.         }
  134.  
  135.         finish_wait(wq, &wait);
  136. #endif
  137.  
  138.         crtc->debug.scanline_start = scanline;
  139.         crtc->debug.start_vbl_time = ktime_get();
  140.         crtc->debug.start_vbl_count =
  141.                 dev->driver->get_vblank_counter(dev, pipe);
  142.  
  143.         trace_i915_pipe_update_vblank_evaded(crtc);
  144. }
  145.  
  146. /**
  147.  * intel_pipe_update_end() - end update of a set of display registers
  148.  * @crtc: the crtc of which the registers were updated
  149.  * @start_vbl_count: start vblank counter (used for error checking)
  150.  *
  151.  * Mark the end of an update started with intel_pipe_update_start(). This
  152.  * re-enables interrupts and verifies the update was actually completed
  153.  * before a vblank using the value of @start_vbl_count.
  154.  */
  155. void intel_pipe_update_end(struct intel_crtc *crtc)
  156. {
  157.         struct drm_device *dev = crtc->base.dev;
  158.         enum pipe pipe = crtc->pipe;
  159.         int scanline_end = intel_get_crtc_scanline(crtc);
  160.         u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
  161.         ktime_t end_vbl_time = ktime_get();
  162.  
  163.         trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
  164.  
  165. //   local_irq_enable();
  166.  
  167.         if (crtc->debug.start_vbl_count &&
  168.             crtc->debug.start_vbl_count != end_vbl_count) {
  169.                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
  170.                           pipe_name(pipe), crtc->debug.start_vbl_count,
  171.                           end_vbl_count,
  172.                           ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
  173.                           crtc->debug.min_vbl, crtc->debug.max_vbl,
  174.                           crtc->debug.scanline_start, scanline_end);
  175.         }
  176. }
  177.  
  178. static void
  179. skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
  180.                  struct drm_framebuffer *fb,
  181.                  int crtc_x, int crtc_y,
  182.                  unsigned int crtc_w, unsigned int crtc_h,
  183.                  uint32_t x, uint32_t y,
  184.                  uint32_t src_w, uint32_t src_h)
  185. {
  186.         struct drm_device *dev = drm_plane->dev;
  187.         struct drm_i915_private *dev_priv = dev->dev_private;
  188.         struct intel_plane *intel_plane = to_intel_plane(drm_plane);
  189.         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  190.         const int pipe = intel_plane->pipe;
  191.         const int plane = intel_plane->plane + 1;
  192.         u32 plane_ctl, stride_div, stride;
  193.         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
  194.         const struct drm_intel_sprite_colorkey *key =
  195.                 &to_intel_plane_state(drm_plane->state)->ckey;
  196.         unsigned long surf_addr;
  197.         u32 tile_height, plane_offset, plane_size;
  198.         unsigned int rotation;
  199.         int x_offset, y_offset;
  200.         struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)->config;
  201.         int scaler_id;
  202.  
  203.         plane_ctl = PLANE_CTL_ENABLE |
  204.                 PLANE_CTL_PIPE_GAMMA_ENABLE |
  205.                 PLANE_CTL_PIPE_CSC_ENABLE;
  206.  
  207.         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
  208.         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
  209.  
  210.         rotation = drm_plane->state->rotation;
  211.         plane_ctl |= skl_plane_ctl_rotation(rotation);
  212.  
  213.         intel_update_sprite_watermarks(drm_plane, crtc, src_w, src_h,
  214.                                        pixel_size, true,
  215.                                        src_w != crtc_w || src_h != crtc_h);
  216.  
  217.         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
  218.                                                fb->pixel_format);
  219.  
  220.         scaler_id = to_intel_plane_state(drm_plane->state)->scaler_id;
  221.  
  222.         /* Sizes are 0 based */
  223.         src_w--;
  224.         src_h--;
  225.         crtc_w--;
  226.         crtc_h--;
  227.  
  228.         if (key->flags) {
  229.                 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
  230.                 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
  231.                 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
  232.         }
  233.  
  234.         if (key->flags & I915_SET_COLORKEY_DESTINATION)
  235.                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
  236.         else if (key->flags & I915_SET_COLORKEY_SOURCE)
  237.                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
  238.  
  239.         surf_addr = intel_plane_obj_offset(intel_plane, obj, 0);
  240.  
  241.         if (intel_rotation_90_or_270(rotation)) {
  242.                 /* stride: Surface height in tiles */
  243.                 tile_height = intel_tile_height(dev, fb->pixel_format,
  244.                                                 fb->modifier[0], 0);
  245.                 stride = DIV_ROUND_UP(fb->height, tile_height);
  246.                 plane_size = (src_w << 16) | src_h;
  247.                 x_offset = stride * tile_height - y - (src_h + 1);
  248.                 y_offset = x;
  249.         } else {
  250.                 stride = fb->pitches[0] / stride_div;
  251.                 plane_size = (src_h << 16) | src_w;
  252.                 x_offset = x;
  253.                 y_offset = y;
  254.         }
  255.         plane_offset = y_offset << 16 | x_offset;
  256.  
  257.         I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
  258.         I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
  259.         I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
  260.  
  261.         /* program plane scaler */
  262.         if (scaler_id >= 0) {
  263.                 uint32_t ps_ctrl = 0;
  264.  
  265.                 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
  266.                         PS_PLANE_SEL(plane));
  267.                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) |
  268.                         crtc_state->scaler_state.scalers[scaler_id].mode;
  269.                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
  270.                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
  271.                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
  272.                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
  273.                         ((crtc_w + 1) << 16)|(crtc_h + 1));
  274.  
  275.                 I915_WRITE(PLANE_POS(pipe, plane), 0);
  276.         } else {
  277.                 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
  278.         }
  279.  
  280.         I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
  281.         I915_WRITE(PLANE_SURF(pipe, plane), surf_addr);
  282.         POSTING_READ(PLANE_SURF(pipe, plane));
  283. }
  284.  
  285. static void
  286. skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
  287. {
  288.         struct drm_device *dev = dplane->dev;
  289.         struct drm_i915_private *dev_priv = dev->dev_private;
  290.         struct intel_plane *intel_plane = to_intel_plane(dplane);
  291.         const int pipe = intel_plane->pipe;
  292.         const int plane = intel_plane->plane + 1;
  293.  
  294.         I915_WRITE(PLANE_CTL(pipe, plane), 0);
  295.  
  296.         I915_WRITE(PLANE_SURF(pipe, plane), 0);
  297.         POSTING_READ(PLANE_SURF(pipe, plane));
  298.  
  299.         intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false);
  300. }
  301.  
  302. static void
  303. chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
  304. {
  305.         struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private;
  306.         int plane = intel_plane->plane;
  307.  
  308.         /* Seems RGB data bypasses the CSC always */
  309.         if (!format_is_yuv(format))
  310.                 return;
  311.  
  312.         /*
  313.          * BT.601 limited range YCbCr -> full range RGB
  314.          *
  315.          * |r|   | 6537 4769     0|   |cr  |
  316.          * |g| = |-3330 4769 -1605| x |y-64|
  317.          * |b|   |    0 4769  8263|   |cb  |
  318.          *
  319.          * Cb and Cr apparently come in as signed already, so no
  320.          * need for any offset. For Y we need to remove the offset.
  321.          */
  322.         I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
  323.         I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
  324.         I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
  325.  
  326.         I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
  327.         I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
  328.         I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
  329.         I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
  330.         I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
  331.  
  332.         I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
  333.         I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
  334.         I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
  335.  
  336.         I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
  337.         I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
  338.         I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
  339. }
  340.  
  341. static void
  342. vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
  343.                  struct drm_framebuffer *fb,
  344.                  int crtc_x, int crtc_y,
  345.                  unsigned int crtc_w, unsigned int crtc_h,
  346.                  uint32_t x, uint32_t y,
  347.                  uint32_t src_w, uint32_t src_h)
  348. {
  349.         struct drm_device *dev = dplane->dev;
  350.         struct drm_i915_private *dev_priv = dev->dev_private;
  351.         struct intel_plane *intel_plane = to_intel_plane(dplane);
  352.         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  353.         int pipe = intel_plane->pipe;
  354.         int plane = intel_plane->plane;
  355.         u32 sprctl;
  356.         unsigned long sprsurf_offset, linear_offset;
  357.         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
  358.         const struct drm_intel_sprite_colorkey *key =
  359.                 &to_intel_plane_state(dplane->state)->ckey;
  360.  
  361.         sprctl = SP_ENABLE;
  362.  
  363.         switch (fb->pixel_format) {
  364.         case DRM_FORMAT_YUYV:
  365.                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
  366.                 break;
  367.         case DRM_FORMAT_YVYU:
  368.                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
  369.                 break;
  370.         case DRM_FORMAT_UYVY:
  371.                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
  372.                 break;
  373.         case DRM_FORMAT_VYUY:
  374.                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
  375.                 break;
  376.         case DRM_FORMAT_RGB565:
  377.                 sprctl |= SP_FORMAT_BGR565;
  378.                 break;
  379.         case DRM_FORMAT_XRGB8888:
  380.                 sprctl |= SP_FORMAT_BGRX8888;
  381.                 break;
  382.         case DRM_FORMAT_ARGB8888:
  383.                 sprctl |= SP_FORMAT_BGRA8888;
  384.                 break;
  385.         case DRM_FORMAT_XBGR2101010:
  386.                 sprctl |= SP_FORMAT_RGBX1010102;
  387.                 break;
  388.         case DRM_FORMAT_ABGR2101010:
  389.                 sprctl |= SP_FORMAT_RGBA1010102;
  390.                 break;
  391.         case DRM_FORMAT_XBGR8888:
  392.                 sprctl |= SP_FORMAT_RGBX8888;
  393.                 break;
  394.         case DRM_FORMAT_ABGR8888:
  395.                 sprctl |= SP_FORMAT_RGBA8888;
  396.                 break;
  397.         default:
  398.                 /*
  399.                  * If we get here one of the upper layers failed to filter
  400.                  * out the unsupported plane formats
  401.                  */
  402.                 BUG();
  403.                 break;
  404.         }
  405.  
  406.         /*
  407.          * Enable gamma to match primary/cursor plane behaviour.
  408.          * FIXME should be user controllable via propertiesa.
  409.          */
  410.         sprctl |= SP_GAMMA_ENABLE;
  411.  
  412.         if (obj->tiling_mode != I915_TILING_NONE)
  413.                 sprctl |= SP_TILED;
  414.  
  415.         /* Sizes are 0 based */
  416.         src_w--;
  417.         src_h--;
  418.         crtc_w--;
  419.         crtc_h--;
  420.  
  421.         linear_offset = y * fb->pitches[0] + x * pixel_size;
  422.         sprsurf_offset = intel_gen4_compute_page_offset(dev_priv,
  423.                                                         &x, &y,
  424.                                                         obj->tiling_mode,
  425.                                                         pixel_size,
  426.                                                         fb->pitches[0]);
  427.         linear_offset -= sprsurf_offset;
  428.  
  429.         if (dplane->state->rotation == BIT(DRM_ROTATE_180)) {
  430.                 sprctl |= SP_ROTATE_180;
  431.  
  432.                 x += src_w;
  433.                 y += src_h;
  434.                 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
  435.         }
  436.  
  437.         if (key->flags) {
  438.                 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
  439.                 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
  440.                 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
  441.         }
  442.  
  443.         if (key->flags & I915_SET_COLORKEY_SOURCE)
  444.                 sprctl |= SP_SOURCE_KEY;
  445.  
  446.         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
  447.                 chv_update_csc(intel_plane, fb->pixel_format);
  448.  
  449.         I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
  450.         I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
  451.  
  452.         if (obj->tiling_mode != I915_TILING_NONE)
  453.                 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
  454.         else
  455.                 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
  456.  
  457.         I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
  458.  
  459.         I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
  460.         I915_WRITE(SPCNTR(pipe, plane), sprctl);
  461.         I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
  462.                    sprsurf_offset);
  463.         POSTING_READ(SPSURF(pipe, plane));
  464. }
  465.  
  466. static void
  467. vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
  468. {
  469.         struct drm_device *dev = dplane->dev;
  470.         struct drm_i915_private *dev_priv = dev->dev_private;
  471.         struct intel_plane *intel_plane = to_intel_plane(dplane);
  472.         int pipe = intel_plane->pipe;
  473.         int plane = intel_plane->plane;
  474.  
  475.         I915_WRITE(SPCNTR(pipe, plane), 0);
  476.  
  477.         I915_WRITE(SPSURF(pipe, plane), 0);
  478.         POSTING_READ(SPSURF(pipe, plane));
  479. }
  480.  
  481. static void
  482. ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
  483.                  struct drm_framebuffer *fb,
  484.                  int crtc_x, int crtc_y,
  485.                  unsigned int crtc_w, unsigned int crtc_h,
  486.                  uint32_t x, uint32_t y,
  487.                  uint32_t src_w, uint32_t src_h)
  488. {
  489.         struct drm_device *dev = plane->dev;
  490.         struct drm_i915_private *dev_priv = dev->dev_private;
  491.         struct intel_plane *intel_plane = to_intel_plane(plane);
  492.         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  493.         enum pipe pipe = intel_plane->pipe;
  494.         u32 sprctl, sprscale = 0;
  495.         unsigned long sprsurf_offset, linear_offset;
  496.         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
  497.         const struct drm_intel_sprite_colorkey *key =
  498.                 &to_intel_plane_state(plane->state)->ckey;
  499.  
  500.         sprctl = SPRITE_ENABLE;
  501.  
  502.         switch (fb->pixel_format) {
  503.         case DRM_FORMAT_XBGR8888:
  504.                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
  505.                 break;
  506.         case DRM_FORMAT_XRGB8888:
  507.                 sprctl |= SPRITE_FORMAT_RGBX888;
  508.                 break;
  509.         case DRM_FORMAT_YUYV:
  510.                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
  511.                 break;
  512.         case DRM_FORMAT_YVYU:
  513.                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
  514.                 break;
  515.         case DRM_FORMAT_UYVY:
  516.                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
  517.                 break;
  518.         case DRM_FORMAT_VYUY:
  519.                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
  520.                 break;
  521.         default:
  522.                 BUG();
  523.         }
  524.  
  525.         /*
  526.          * Enable gamma to match primary/cursor plane behaviour.
  527.          * FIXME should be user controllable via propertiesa.
  528.          */
  529.         sprctl |= SPRITE_GAMMA_ENABLE;
  530.  
  531.         if (obj->tiling_mode != I915_TILING_NONE)
  532.                 sprctl |= SPRITE_TILED;
  533.  
  534.         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
  535.                 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
  536.         else
  537.                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
  538.  
  539.         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
  540.                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
  541.  
  542.         intel_update_sprite_watermarks(plane, crtc, src_w, src_h, pixel_size,
  543.                                        true,
  544.                                        src_w != crtc_w || src_h != crtc_h);
  545.  
  546.         /* Sizes are 0 based */
  547.         src_w--;
  548.         src_h--;
  549.         crtc_w--;
  550.         crtc_h--;
  551.  
  552.         if (crtc_w != src_w || crtc_h != src_h)
  553.                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
  554.  
  555.         linear_offset = y * fb->pitches[0] + x * pixel_size;
  556.         sprsurf_offset =
  557.                 intel_gen4_compute_page_offset(dev_priv,
  558.                                                &x, &y, obj->tiling_mode,
  559.                                                pixel_size, fb->pitches[0]);
  560.         linear_offset -= sprsurf_offset;
  561.  
  562.         if (plane->state->rotation == BIT(DRM_ROTATE_180)) {
  563.                 sprctl |= SPRITE_ROTATE_180;
  564.  
  565.                 /* HSW and BDW does this automagically in hardware */
  566.                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
  567.                         x += src_w;
  568.                         y += src_h;
  569.                         linear_offset += src_h * fb->pitches[0] +
  570.                                 src_w * pixel_size;
  571.                 }
  572.         }
  573.  
  574.         if (key->flags) {
  575.                 I915_WRITE(SPRKEYVAL(pipe), key->min_value);
  576.                 I915_WRITE(SPRKEYMAX(pipe), key->max_value);
  577.                 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask);
  578.         }
  579.  
  580.         if (key->flags & I915_SET_COLORKEY_DESTINATION)
  581.                 sprctl |= SPRITE_DEST_KEY;
  582.         else if (key->flags & I915_SET_COLORKEY_SOURCE)
  583.                 sprctl |= SPRITE_SOURCE_KEY;
  584.  
  585.         I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
  586.         I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
  587.  
  588.         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
  589.          * register */
  590.         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
  591.                 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
  592.         else if (obj->tiling_mode != I915_TILING_NONE)
  593.                 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
  594.         else
  595.                 I915_WRITE(SPRLINOFF(pipe), linear_offset);
  596.  
  597.         I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
  598.         if (intel_plane->can_scale)
  599.                 I915_WRITE(SPRSCALE(pipe), sprscale);
  600.         I915_WRITE(SPRCTL(pipe), sprctl);
  601.         I915_WRITE(SPRSURF(pipe),
  602.                    i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
  603.         POSTING_READ(SPRSURF(pipe));
  604. }
  605.  
  606. static void
  607. ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
  608. {
  609.         struct drm_device *dev = plane->dev;
  610.         struct drm_i915_private *dev_priv = dev->dev_private;
  611.         struct intel_plane *intel_plane = to_intel_plane(plane);
  612.         int pipe = intel_plane->pipe;
  613.  
  614.         I915_WRITE(SPRCTL(pipe), 0);
  615.         /* Can't leave the scaler enabled... */
  616.         if (intel_plane->can_scale)
  617.                 I915_WRITE(SPRSCALE(pipe), 0);
  618.  
  619.         I915_WRITE(SPRSURF(pipe), 0);
  620.         POSTING_READ(SPRSURF(pipe));
  621. }
  622.  
  623. static void
  624. ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
  625.                  struct drm_framebuffer *fb,
  626.                  int crtc_x, int crtc_y,
  627.                  unsigned int crtc_w, unsigned int crtc_h,
  628.                  uint32_t x, uint32_t y,
  629.                  uint32_t src_w, uint32_t src_h)
  630. {
  631.         struct drm_device *dev = plane->dev;
  632.         struct drm_i915_private *dev_priv = dev->dev_private;
  633.         struct intel_plane *intel_plane = to_intel_plane(plane);
  634.         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  635.         int pipe = intel_plane->pipe;
  636.         unsigned long dvssurf_offset, linear_offset;
  637.         u32 dvscntr, dvsscale;
  638.         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
  639.         const struct drm_intel_sprite_colorkey *key =
  640.                 &to_intel_plane_state(plane->state)->ckey;
  641.  
  642.         dvscntr = DVS_ENABLE;
  643.  
  644.         switch (fb->pixel_format) {
  645.         case DRM_FORMAT_XBGR8888:
  646.                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
  647.                 break;
  648.         case DRM_FORMAT_XRGB8888:
  649.                 dvscntr |= DVS_FORMAT_RGBX888;
  650.                 break;
  651.         case DRM_FORMAT_YUYV:
  652.                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
  653.                 break;
  654.         case DRM_FORMAT_YVYU:
  655.                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
  656.                 break;
  657.         case DRM_FORMAT_UYVY:
  658.                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
  659.                 break;
  660.         case DRM_FORMAT_VYUY:
  661.                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
  662.                 break;
  663.         default:
  664.                 BUG();
  665.         }
  666.  
  667.         /*
  668.          * Enable gamma to match primary/cursor plane behaviour.
  669.          * FIXME should be user controllable via propertiesa.
  670.          */
  671.         dvscntr |= DVS_GAMMA_ENABLE;
  672.  
  673.         if (obj->tiling_mode != I915_TILING_NONE)
  674.                 dvscntr |= DVS_TILED;
  675.  
  676.         if (IS_GEN6(dev))
  677.                 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
  678.  
  679.         intel_update_sprite_watermarks(plane, crtc, src_w, src_h,
  680.                                        pixel_size, true,
  681.                                        src_w != crtc_w || src_h != crtc_h);
  682.  
  683.         /* Sizes are 0 based */
  684.         src_w--;
  685.         src_h--;
  686.         crtc_w--;
  687.         crtc_h--;
  688.  
  689.         dvsscale = 0;
  690.         if (crtc_w != src_w || crtc_h != src_h)
  691.                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
  692.  
  693.         linear_offset = y * fb->pitches[0] + x * pixel_size;
  694.         dvssurf_offset =
  695.                 intel_gen4_compute_page_offset(dev_priv,
  696.                                                &x, &y, obj->tiling_mode,
  697.                                                pixel_size, fb->pitches[0]);
  698.         linear_offset -= dvssurf_offset;
  699.  
  700.         if (plane->state->rotation == BIT(DRM_ROTATE_180)) {
  701.                 dvscntr |= DVS_ROTATE_180;
  702.  
  703.                 x += src_w;
  704.                 y += src_h;
  705.                 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
  706.         }
  707.  
  708.         if (key->flags) {
  709.                 I915_WRITE(DVSKEYVAL(pipe), key->min_value);
  710.                 I915_WRITE(DVSKEYMAX(pipe), key->max_value);
  711.                 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask);
  712.         }
  713.  
  714.         if (key->flags & I915_SET_COLORKEY_DESTINATION)
  715.                 dvscntr |= DVS_DEST_KEY;
  716.         else if (key->flags & I915_SET_COLORKEY_SOURCE)
  717.                 dvscntr |= DVS_SOURCE_KEY;
  718.  
  719.         I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
  720.         I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
  721.  
  722.         if (obj->tiling_mode != I915_TILING_NONE)
  723.                 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
  724.         else
  725.                 I915_WRITE(DVSLINOFF(pipe), linear_offset);
  726.  
  727.         I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
  728.         I915_WRITE(DVSSCALE(pipe), dvsscale);
  729.         I915_WRITE(DVSCNTR(pipe), dvscntr);
  730.         I915_WRITE(DVSSURF(pipe),
  731.                    i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
  732.         POSTING_READ(DVSSURF(pipe));
  733. }
  734.  
  735. static void
  736. ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
  737. {
  738.         struct drm_device *dev = plane->dev;
  739.         struct drm_i915_private *dev_priv = dev->dev_private;
  740.         struct intel_plane *intel_plane = to_intel_plane(plane);
  741.         int pipe = intel_plane->pipe;
  742.  
  743.         I915_WRITE(DVSCNTR(pipe), 0);
  744.         /* Disable the scaler */
  745.         I915_WRITE(DVSSCALE(pipe), 0);
  746.  
  747.         I915_WRITE(DVSSURF(pipe), 0);
  748.         POSTING_READ(DVSSURF(pipe));
  749. }
  750.  
  751. static int
  752. intel_check_sprite_plane(struct drm_plane *plane,
  753.                          struct intel_crtc_state *crtc_state,
  754.                          struct intel_plane_state *state)
  755. {
  756.         struct drm_device *dev = plane->dev;
  757.         struct drm_crtc *crtc = state->base.crtc;
  758.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  759.         struct intel_plane *intel_plane = to_intel_plane(plane);
  760.         struct drm_framebuffer *fb = state->base.fb;
  761.         int crtc_x, crtc_y;
  762.         unsigned int crtc_w, crtc_h;
  763.         uint32_t src_x, src_y, src_w, src_h;
  764.         struct drm_rect *src = &state->src;
  765.         struct drm_rect *dst = &state->dst;
  766.         const struct drm_rect *clip = &state->clip;
  767.         int hscale, vscale;
  768.         int max_scale, min_scale;
  769.         bool can_scale;
  770.         int pixel_size;
  771.  
  772.         if (!fb) {
  773.                 state->visible = false;
  774.                 return 0;
  775.         }
  776.  
  777.         /* Don't modify another pipe's plane */
  778.         if (intel_plane->pipe != intel_crtc->pipe) {
  779.                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
  780.                 return -EINVAL;
  781.         }
  782.  
  783.         /* FIXME check all gen limits */
  784.         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
  785.                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
  786.                 return -EINVAL;
  787.         }
  788.  
  789.         /* setup can_scale, min_scale, max_scale */
  790.         if (INTEL_INFO(dev)->gen >= 9) {
  791.                 /* use scaler when colorkey is not required */
  792.                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
  793.                         can_scale = 1;
  794.                         min_scale = 1;
  795.                         max_scale = skl_max_scale(intel_crtc, crtc_state);
  796.                 } else {
  797.                         can_scale = 0;
  798.                         min_scale = DRM_PLANE_HELPER_NO_SCALING;
  799.                         max_scale = DRM_PLANE_HELPER_NO_SCALING;
  800.                 }
  801.         } else {
  802.                 can_scale = intel_plane->can_scale;
  803.                 max_scale = intel_plane->max_downscale << 16;
  804.                 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
  805.         }
  806.  
  807.         /*
  808.          * FIXME the following code does a bunch of fuzzy adjustments to the
  809.          * coordinates and sizes. We probably need some way to decide whether
  810.          * more strict checking should be done instead.
  811.          */
  812.         drm_rect_rotate(src, fb->width << 16, fb->height << 16,
  813.                         state->base.rotation);
  814.  
  815.         hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
  816.         BUG_ON(hscale < 0);
  817.  
  818.         vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
  819.         BUG_ON(vscale < 0);
  820.  
  821.         state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
  822.  
  823.         crtc_x = dst->x1;
  824.         crtc_y = dst->y1;
  825.         crtc_w = drm_rect_width(dst);
  826.         crtc_h = drm_rect_height(dst);
  827.  
  828.         if (state->visible) {
  829.                 /* check again in case clipping clamped the results */
  830.                 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
  831.                 if (hscale < 0) {
  832.                         DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
  833.                         drm_rect_debug_print(src, true);
  834.                         drm_rect_debug_print(dst, false);
  835.  
  836.                         return hscale;
  837.                 }
  838.  
  839.                 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
  840.                 if (vscale < 0) {
  841.                         DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
  842.                         drm_rect_debug_print(src, true);
  843.                         drm_rect_debug_print(dst, false);
  844.  
  845.                         return vscale;
  846.                 }
  847.  
  848.                 /* Make the source viewport size an exact multiple of the scaling factors. */
  849.                 drm_rect_adjust_size(src,
  850.                                      drm_rect_width(dst) * hscale - drm_rect_width(src),
  851.                                      drm_rect_height(dst) * vscale - drm_rect_height(src));
  852.  
  853.                 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
  854.                                     state->base.rotation);
  855.  
  856.                 /* sanity check to make sure the src viewport wasn't enlarged */
  857.                 WARN_ON(src->x1 < (int) state->base.src_x ||
  858.                         src->y1 < (int) state->base.src_y ||
  859.                         src->x2 > (int) state->base.src_x + state->base.src_w ||
  860.                         src->y2 > (int) state->base.src_y + state->base.src_h);
  861.  
  862.                 /*
  863.                  * Hardware doesn't handle subpixel coordinates.
  864.                  * Adjust to (macro)pixel boundary, but be careful not to
  865.                  * increase the source viewport size, because that could
  866.                  * push the downscaling factor out of bounds.
  867.                  */
  868.                 src_x = src->x1 >> 16;
  869.                 src_w = drm_rect_width(src) >> 16;
  870.                 src_y = src->y1 >> 16;
  871.                 src_h = drm_rect_height(src) >> 16;
  872.  
  873.                 if (format_is_yuv(fb->pixel_format)) {
  874.                         src_x &= ~1;
  875.                         src_w &= ~1;
  876.  
  877.                         /*
  878.                          * Must keep src and dst the
  879.                          * same if we can't scale.
  880.                          */
  881.                         if (!can_scale)
  882.                                 crtc_w &= ~1;
  883.  
  884.                         if (crtc_w == 0)
  885.                                 state->visible = false;
  886.                 }
  887.         }
  888.  
  889.         /* Check size restrictions when scaling */
  890.         if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {
  891.                 unsigned int width_bytes;
  892.  
  893.                 WARN_ON(!can_scale);
  894.  
  895.                 /* FIXME interlacing min height is 6 */
  896.  
  897.                 if (crtc_w < 3 || crtc_h < 3)
  898.                         state->visible = false;
  899.  
  900.                 if (src_w < 3 || src_h < 3)
  901.                         state->visible = false;
  902.  
  903.                 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
  904.                 width_bytes = ((src_x * pixel_size) & 63) +
  905.                                         src_w * pixel_size;
  906.  
  907.                 if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
  908.                     width_bytes > 4096 || fb->pitches[0] > 4096)) {
  909.                         DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
  910.                         return -EINVAL;
  911.                 }
  912.         }
  913.  
  914.         if (state->visible) {
  915.                 src->x1 = src_x << 16;
  916.                 src->x2 = (src_x + src_w) << 16;
  917.                 src->y1 = src_y << 16;
  918.                 src->y2 = (src_y + src_h) << 16;
  919.         }
  920.  
  921.         dst->x1 = crtc_x;
  922.         dst->x2 = crtc_x + crtc_w;
  923.         dst->y1 = crtc_y;
  924.         dst->y2 = crtc_y + crtc_h;
  925.  
  926.         return 0;
  927. }
  928.  
  929. static void
  930. intel_commit_sprite_plane(struct drm_plane *plane,
  931.                           struct intel_plane_state *state)
  932. {
  933.         struct drm_crtc *crtc = state->base.crtc;
  934.         struct intel_plane *intel_plane = to_intel_plane(plane);
  935.         struct drm_framebuffer *fb = state->base.fb;
  936.  
  937.         crtc = crtc ? crtc : plane->crtc;
  938.  
  939.         if (!crtc->state->active)
  940.                 return;
  941.  
  942.         if (state->visible) {
  943.                 intel_plane->update_plane(plane, crtc, fb,
  944.                                           state->dst.x1, state->dst.y1,
  945.                                           drm_rect_width(&state->dst),
  946.                                           drm_rect_height(&state->dst),
  947.                                           state->src.x1 >> 16,
  948.                                           state->src.y1 >> 16,
  949.                                           drm_rect_width(&state->src) >> 16,
  950.                                           drm_rect_height(&state->src) >> 16);
  951.         } else {
  952.                 intel_plane->disable_plane(plane, crtc);
  953.         }
  954. }
  955.  
  956. int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
  957.                               struct drm_file *file_priv)
  958. {
  959.         struct drm_intel_sprite_colorkey *set = data;
  960.         struct drm_plane *plane;
  961.         struct drm_plane_state *plane_state;
  962.         struct drm_atomic_state *state;
  963.         struct drm_modeset_acquire_ctx ctx;
  964.         int ret = 0;
  965.  
  966.         /* Make sure we don't try to enable both src & dest simultaneously */
  967.         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
  968.                 return -EINVAL;
  969.  
  970.         if (IS_VALLEYVIEW(dev) &&
  971.             set->flags & I915_SET_COLORKEY_DESTINATION)
  972.                 return -EINVAL;
  973.  
  974.         plane = drm_plane_find(dev, set->plane_id);
  975.         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
  976.                 return -ENOENT;
  977.  
  978.         drm_modeset_acquire_init(&ctx, 0);
  979.  
  980.         state = drm_atomic_state_alloc(plane->dev);
  981.         if (!state) {
  982.                 ret = -ENOMEM;
  983.                 goto out;
  984.         }
  985.         state->acquire_ctx = &ctx;
  986.  
  987.         while (1) {
  988.                 plane_state = drm_atomic_get_plane_state(state, plane);
  989.                 ret = PTR_ERR_OR_ZERO(plane_state);
  990.                 if (!ret) {
  991.                         to_intel_plane_state(plane_state)->ckey = *set;
  992.                         ret = drm_atomic_commit(state);
  993.                 }
  994.  
  995.                 if (ret != -EDEADLK)
  996.                         break;
  997.  
  998.                 drm_atomic_state_clear(state);
  999.                 drm_modeset_backoff(&ctx);
  1000.         }
  1001.  
  1002.         if (ret)
  1003.                 drm_atomic_state_free(state);
  1004.  
  1005. out:
  1006.         drm_modeset_drop_locks(&ctx);
  1007.         drm_modeset_acquire_fini(&ctx);
  1008.         return ret;
  1009. }
  1010.  
  1011. static const uint32_t ilk_plane_formats[] = {
  1012.         DRM_FORMAT_XRGB8888,
  1013.         DRM_FORMAT_YUYV,
  1014.         DRM_FORMAT_YVYU,
  1015.         DRM_FORMAT_UYVY,
  1016.         DRM_FORMAT_VYUY,
  1017. };
  1018.  
  1019. static const uint32_t snb_plane_formats[] = {
  1020.         DRM_FORMAT_XBGR8888,
  1021.         DRM_FORMAT_XRGB8888,
  1022.         DRM_FORMAT_YUYV,
  1023.         DRM_FORMAT_YVYU,
  1024.         DRM_FORMAT_UYVY,
  1025.         DRM_FORMAT_VYUY,
  1026. };
  1027.  
  1028. static const uint32_t vlv_plane_formats[] = {
  1029.         DRM_FORMAT_RGB565,
  1030.         DRM_FORMAT_ABGR8888,
  1031.         DRM_FORMAT_ARGB8888,
  1032.         DRM_FORMAT_XBGR8888,
  1033.         DRM_FORMAT_XRGB8888,
  1034.         DRM_FORMAT_XBGR2101010,
  1035.         DRM_FORMAT_ABGR2101010,
  1036.         DRM_FORMAT_YUYV,
  1037.         DRM_FORMAT_YVYU,
  1038.         DRM_FORMAT_UYVY,
  1039.         DRM_FORMAT_VYUY,
  1040. };
  1041.  
  1042. static uint32_t skl_plane_formats[] = {
  1043.         DRM_FORMAT_RGB565,
  1044.         DRM_FORMAT_ABGR8888,
  1045.         DRM_FORMAT_ARGB8888,
  1046.         DRM_FORMAT_XBGR8888,
  1047.         DRM_FORMAT_XRGB8888,
  1048.         DRM_FORMAT_YUYV,
  1049.         DRM_FORMAT_YVYU,
  1050.         DRM_FORMAT_UYVY,
  1051.         DRM_FORMAT_VYUY,
  1052. };
  1053.  
  1054. int
  1055. intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
  1056. {
  1057.         struct intel_plane *intel_plane;
  1058.         struct intel_plane_state *state;
  1059.         unsigned long possible_crtcs;
  1060.         const uint32_t *plane_formats;
  1061.         int num_plane_formats;
  1062.         int ret;
  1063.  
  1064.         if (INTEL_INFO(dev)->gen < 5)
  1065.                 return -ENODEV;
  1066.  
  1067.         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
  1068.         if (!intel_plane)
  1069.                 return -ENOMEM;
  1070.  
  1071.         state = intel_create_plane_state(&intel_plane->base);
  1072.         if (!state) {
  1073.                 kfree(intel_plane);
  1074.                 return -ENOMEM;
  1075.         }
  1076.         intel_plane->base.state = &state->base;
  1077.  
  1078.         switch (INTEL_INFO(dev)->gen) {
  1079.         case 5:
  1080.         case 6:
  1081.                 intel_plane->can_scale = true;
  1082.                 intel_plane->max_downscale = 16;
  1083.                 intel_plane->update_plane = ilk_update_plane;
  1084.                 intel_plane->disable_plane = ilk_disable_plane;
  1085.  
  1086.                 if (IS_GEN6(dev)) {
  1087.                         plane_formats = snb_plane_formats;
  1088.                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
  1089.                 } else {
  1090.                         plane_formats = ilk_plane_formats;
  1091.                         num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
  1092.                 }
  1093.                 break;
  1094.  
  1095.         case 7:
  1096.         case 8:
  1097.                 if (IS_IVYBRIDGE(dev)) {
  1098.                         intel_plane->can_scale = true;
  1099.                         intel_plane->max_downscale = 2;
  1100.                 } else {
  1101.                         intel_plane->can_scale = false;
  1102.                         intel_plane->max_downscale = 1;
  1103.                 }
  1104.  
  1105.                 if (IS_VALLEYVIEW(dev)) {
  1106.                         intel_plane->update_plane = vlv_update_plane;
  1107.                         intel_plane->disable_plane = vlv_disable_plane;
  1108.  
  1109.                         plane_formats = vlv_plane_formats;
  1110.                         num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
  1111.                 } else {
  1112.                         intel_plane->update_plane = ivb_update_plane;
  1113.                         intel_plane->disable_plane = ivb_disable_plane;
  1114.  
  1115.                         plane_formats = snb_plane_formats;
  1116.                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
  1117.                 }
  1118.                 break;
  1119.         case 9:
  1120.                 intel_plane->can_scale = true;
  1121.                 intel_plane->update_plane = skl_update_plane;
  1122.                 intel_plane->disable_plane = skl_disable_plane;
  1123.                 state->scaler_id = -1;
  1124.  
  1125.                 plane_formats = skl_plane_formats;
  1126.                 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
  1127.                 break;
  1128.         default:
  1129.                 kfree(intel_plane);
  1130.                 return -ENODEV;
  1131.         }
  1132.  
  1133.         intel_plane->pipe = pipe;
  1134.         intel_plane->plane = plane;
  1135.         intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
  1136.         intel_plane->check_plane = intel_check_sprite_plane;
  1137.         intel_plane->commit_plane = intel_commit_sprite_plane;
  1138.         possible_crtcs = (1 << pipe);
  1139.         ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
  1140.                                        &intel_plane_funcs,
  1141.                                        plane_formats, num_plane_formats,
  1142.                                        DRM_PLANE_TYPE_OVERLAY);
  1143.         if (ret) {
  1144.                 kfree(intel_plane);
  1145.                 goto out;
  1146.         }
  1147.  
  1148.         intel_create_rotation_property(dev, intel_plane);
  1149.  
  1150.         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
  1151.  
  1152. out:
  1153.         return ret;
  1154. }
  1155.