Rev 883 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 883 | Rev 885 | ||
---|---|---|---|
Line 1... | Line 1... | ||
1 | #define R300_TEST |
1 | #define R300_TEST |
Line 2... | Line 2... | ||
2 | 2 | ||
Line 3... | Line -... | ||
3 | #include "r5xx_regs.h" |
- | |
4 | - | ||
5 | #define RADEON_BUS_CNTL 0x0030 |
- | |
6 | # define RADEON_BUS_MASTER_DIS (1 << 6) |
- | |
7 | - | ||
8 | - | ||
9 | #define RADEON_SCRATCH_UMSK 0x0770 |
- | |
10 | #define RADEON_SCRATCH_ADDR 0x0774 |
- | |
11 | - | ||
12 | #define RADEON_CP_ME_RAM_ADDR 0x07d4 |
- | |
13 | #define RADEON_CP_ME_RAM_RADDR 0x07d8 |
- | |
14 | #define RADEON_CP_ME_RAM_DATAH 0x07dc |
- | |
15 | #define RADEON_CP_ME_RAM_DATAL 0x07e0 |
- | |
16 | - | ||
17 | #define RADEON_AIC_CNTL 0x01d0 |
- | |
18 | #define RADEON_PCIGART_TRANSLATE_EN (1 << 0) |
- | |
19 | - | ||
20 | - | ||
21 | #define RADEON_CP_RB_BASE 0x0700 |
- | |
22 | #define RADEON_CP_RB_CNTL 0x0704 |
- | |
23 | # define RADEON_BUF_SWAP_32BIT (2 << 16) |
- | |
24 | # define RADEON_RB_NO_UPDATE (1 << 27) |
- | |
25 | #define RADEON_CP_RB_RPTR_ADDR 0x070c |
- | |
26 | #define RADEON_CP_RB_RPTR 0x0710 |
- | |
27 | #define RADEON_CP_RB_WPTR 0x0714 |
- | |
28 | - | ||
29 | #define RADEON_CP_RB_WPTR_DELAY 0x0718 |
- | |
30 | # define RADEON_PRE_WRITE_TIMER_SHIFT 0 |
- | |
31 | # define RADEON_PRE_WRITE_LIMIT_SHIFT 23 |
- | |
32 | - | ||
33 | #define RADEON_CP_IB_BASE 0x0738 |
- | |
34 | - | ||
35 | #define RADEON_CP_CSQ_CNTL 0x0740 |
- | |
36 | # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) |
- | |
37 | # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) |
- | |
38 | # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) |
- | |
39 | # define RADEON_CSQ_PRIBM_INDDIS (2 << 28) |
- | |
40 | # define RADEON_CSQ_PRIPIO_INDBM (3 << 28) |
- | |
41 | # define RADEON_CSQ_PRIBM_INDBM (4 << 28) |
- | |
42 | # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) |
- | |
43 | - | ||
44 | #define RADEON_ISYNC_CNTL 0x1724 |
- | |
45 | # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) |
- | |
46 | # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) |
- | |
47 | # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) |
- | |
48 | # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) |
- | |
Line 49... | Line 3... | ||
49 | # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) |
3 | #include "r5xx_regs.h" |
Line 50... | Line 4... | ||
50 | # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) |
4 | |
Line 208... | Line 162... | ||
208 | 162 | ||
Line 209... | Line 163... | ||
209 | dbgprintf("gui_control %x \n", rhd.gui_control); |
163 | dbgprintf("gui_control %x \n", rhd.gui_control); |
Line 210... | Line 164... | ||
210 | 164 | ||
211 | rhd.surface_cntl = 0; |
- | |
Line 212... | Line 165... | ||
212 | // rhd.dst_pitch_offset = ((screenpitch / 64) << 22) | (rhd.fbLocation >> 10); |
165 | rhd.surface_cntl = 0; |
213 | 166 | ||
Line 214... | Line 167... | ||
214 | rhd.dst_pitch_offset = (((rhd.displayWidth * 4 / 64)<< 22) | |
167 | rhd.dst_pitch_offset = (((rhd.displayWidth * 4 / 64)<< 22) | |
Line 215... | Line 168... | ||
215 | (rhd.fbLocation >> 10)); |
168 | (rhd.fbLocation >> 10)); |
216 | 169 | ||
217 | 170 | ||
218 | dbgprintf("dst_pitch_offset %x \n", rhd.dst_pitch_offset); |
171 | dbgprintf("dst_pitch_offset %x \n", rhd.dst_pitch_offset); |
219 | 172 | ||
220 | scr_pixmap.width = rhd.displayWidth; |
173 | scr_pixmap.width = rhd.displayWidth; |
221 | scr_pixmap.height = rhd.displayHeight; |
174 | scr_pixmap.height = rhd.displayHeight; |
Line 222... | Line 175... | ||
222 | scr_pixmap.format = PICT_a8r8g8b8; |
175 | scr_pixmap.format = PICT_a8r8g8b8; |