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1 | #define R300_TEST |
1 | #define R300_TEST |
2 | 2 | ||
3 | #include "r5xx_regs.h" |
3 | #include "r5xx_regs.h" |
4 | 4 | ||
5 | #define RADEON_BUS_CNTL 0x0030 |
5 | #define RADEON_BUS_CNTL 0x0030 |
6 | # define RADEON_BUS_MASTER_DIS (1 << 6) |
6 | # define RADEON_BUS_MASTER_DIS (1 << 6) |
7 | 7 | ||
8 | 8 | ||
9 | #define RADEON_SCRATCH_UMSK 0x0770 |
9 | #define RADEON_SCRATCH_UMSK 0x0770 |
10 | #define RADEON_SCRATCH_ADDR 0x0774 |
10 | #define RADEON_SCRATCH_ADDR 0x0774 |
11 | 11 | ||
12 | #define RADEON_CP_ME_RAM_ADDR 0x07d4 |
12 | #define RADEON_CP_ME_RAM_ADDR 0x07d4 |
13 | #define RADEON_CP_ME_RAM_RADDR 0x07d8 |
13 | #define RADEON_CP_ME_RAM_RADDR 0x07d8 |
14 | #define RADEON_CP_ME_RAM_DATAH 0x07dc |
14 | #define RADEON_CP_ME_RAM_DATAH 0x07dc |
15 | #define RADEON_CP_ME_RAM_DATAL 0x07e0 |
15 | #define RADEON_CP_ME_RAM_DATAL 0x07e0 |
16 | 16 | ||
17 | #define RADEON_AIC_CNTL 0x01d0 |
17 | #define RADEON_AIC_CNTL 0x01d0 |
18 | #define RADEON_PCIGART_TRANSLATE_EN (1 << 0) |
18 | #define RADEON_PCIGART_TRANSLATE_EN (1 << 0) |
19 | 19 | ||
20 | 20 | ||
21 | #define RADEON_CP_RB_BASE 0x0700 |
21 | #define RADEON_CP_RB_BASE 0x0700 |
22 | #define RADEON_CP_RB_CNTL 0x0704 |
22 | #define RADEON_CP_RB_CNTL 0x0704 |
23 | # define RADEON_BUF_SWAP_32BIT (2 << 16) |
23 | # define RADEON_BUF_SWAP_32BIT (2 << 16) |
24 | # define RADEON_RB_NO_UPDATE (1 << 27) |
24 | # define RADEON_RB_NO_UPDATE (1 << 27) |
25 | #define RADEON_CP_RB_RPTR_ADDR 0x070c |
25 | #define RADEON_CP_RB_RPTR_ADDR 0x070c |
26 | #define RADEON_CP_RB_RPTR 0x0710 |
26 | #define RADEON_CP_RB_RPTR 0x0710 |
27 | #define RADEON_CP_RB_WPTR 0x0714 |
27 | #define RADEON_CP_RB_WPTR 0x0714 |
28 | 28 | ||
29 | #define RADEON_CP_RB_WPTR_DELAY 0x0718 |
29 | #define RADEON_CP_RB_WPTR_DELAY 0x0718 |
30 | # define RADEON_PRE_WRITE_TIMER_SHIFT 0 |
30 | # define RADEON_PRE_WRITE_TIMER_SHIFT 0 |
31 | # define RADEON_PRE_WRITE_LIMIT_SHIFT 23 |
31 | # define RADEON_PRE_WRITE_LIMIT_SHIFT 23 |
32 | 32 | ||
33 | #define RADEON_CP_IB_BASE 0x0738 |
33 | #define RADEON_CP_IB_BASE 0x0738 |
34 | 34 | ||
35 | #define RADEON_CP_CSQ_CNTL 0x0740 |
35 | #define RADEON_CP_CSQ_CNTL 0x0740 |
36 | # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) |
36 | # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) |
37 | # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) |
37 | # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) |
38 | # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) |
38 | # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) |
39 | # define RADEON_CSQ_PRIBM_INDDIS (2 << 28) |
39 | # define RADEON_CSQ_PRIBM_INDDIS (2 << 28) |
40 | # define RADEON_CSQ_PRIPIO_INDBM (3 << 28) |
40 | # define RADEON_CSQ_PRIPIO_INDBM (3 << 28) |
41 | # define RADEON_CSQ_PRIBM_INDBM (4 << 28) |
41 | # define RADEON_CSQ_PRIBM_INDBM (4 << 28) |
42 | # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) |
42 | # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) |
43 | 43 | ||
44 | #define RADEON_ISYNC_CNTL 0x1724 |
44 | #define RADEON_ISYNC_CNTL 0x1724 |
45 | # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) |
45 | # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) |
46 | # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) |
46 | # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) |
47 | # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) |
47 | # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) |
48 | # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) |
48 | # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) |
49 | # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) |
49 | # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) |
50 | # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) |
50 | # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) |
51 | 51 | ||
52 | #define R5XX_LOOP_COUNT 2000000 |
52 | #define R5XX_LOOP_COUNT 2000000 |
53 | 53 | ||
54 | #include "microcode.h" |
54 | #include "microcode.h" |
55 | 55 | ||
56 | #define RADEON_CLOCK_CNTL_DATA 0x000c |
56 | #define RADEON_CLOCK_CNTL_DATA 0x000c |
57 | 57 | ||
58 | #define RADEON_CLOCK_CNTL_INDEX 0x0008 |
58 | #define RADEON_CLOCK_CNTL_INDEX 0x0008 |
59 | # define RADEON_PLL_WR_EN (1 << 7) |
59 | # define RADEON_PLL_WR_EN (1 << 7) |
60 | # define RADEON_PLL_DIV_SEL (3 << 8) |
60 | # define RADEON_PLL_DIV_SEL (3 << 8) |
61 | # define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8) |
61 | # define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8) |
62 | 62 | ||
63 | #define RADEON_MCLK_CNTL 0x0012 /* PLL */ |
63 | #define RADEON_MCLK_CNTL 0x0012 /* PLL */ |
64 | # define RADEON_FORCEON_MCLKA (1 << 16) |
64 | # define RADEON_FORCEON_MCLKA (1 << 16) |
65 | # define RADEON_FORCEON_MCLKB (1 << 17) |
65 | # define RADEON_FORCEON_MCLKB (1 << 17) |
66 | # define RADEON_FORCEON_YCLKA (1 << 18) |
66 | # define RADEON_FORCEON_YCLKA (1 << 18) |
67 | # define RADEON_FORCEON_YCLKB (1 << 19) |
67 | # define RADEON_FORCEON_YCLKB (1 << 19) |
68 | # define RADEON_FORCEON_MC (1 << 20) |
68 | # define RADEON_FORCEON_MC (1 << 20) |
69 | # define RADEON_FORCEON_AIC (1 << 21) |
69 | # define RADEON_FORCEON_AIC (1 << 21) |
70 | # define R300_DISABLE_MC_MCLKA (1 << 21) |
70 | # define R300_DISABLE_MC_MCLKA (1 << 21) |
71 | # define R300_DISABLE_MC_MCLKB (1 << 21) |
71 | # define R300_DISABLE_MC_MCLKB (1 << 21) |
72 | 72 | ||
73 | 73 | ||
74 | void RADEONPllErrataAfterData() |
74 | void RADEONPllErrataAfterData() |
75 | { |
75 | { |
76 | 76 | ||
77 | /* This function is required to workaround a hardware bug in some (all?) |
77 | /* This function is required to workaround a hardware bug in some (all?) |
78 | * revisions of the R300. This workaround should be called after every |
78 | * revisions of the R300. This workaround should be called after every |
79 | * CLOCK_CNTL_INDEX register access. If not, register reads afterward |
79 | * CLOCK_CNTL_INDEX register access. If not, register reads afterward |
80 | * may not be correct. |
80 | * may not be correct. |
81 | */ |
81 | */ |
82 | if (rhd.ChipSet <= RHD_RV380) |
82 | if (rhd.ChipFamily <= CHIP_FAMILY_RV380) |
83 | { |
83 | { |
84 | u32_t save, tmp; |
84 | u32_t save, tmp; |
85 | 85 | ||
86 | save = INREG(RADEON_CLOCK_CNTL_INDEX); |
86 | save = INREG(RADEON_CLOCK_CNTL_INDEX); |
87 | tmp = save & ~(0x3f | RADEON_PLL_WR_EN); |
87 | tmp = save & ~(0x3f | RADEON_PLL_WR_EN); |
88 | OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp); |
88 | OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp); |
89 | tmp = INREG(RADEON_CLOCK_CNTL_DATA); |
89 | tmp = INREG(RADEON_CLOCK_CNTL_DATA); |
90 | OUTREG(RADEON_CLOCK_CNTL_INDEX, save); |
90 | OUTREG(RADEON_CLOCK_CNTL_INDEX, save); |
91 | } |
91 | } |
92 | } |
92 | } |
93 | 93 | ||
94 | 94 | ||
95 | /* Read PLL register */ |
95 | /* Read PLL register */ |
96 | u32_t RADEONINPLL(int addr) |
96 | u32_t RADEONINPLL(int addr) |
97 | { |
97 | { |
98 | u32_t data; |
98 | u32_t data; |
99 | 99 | ||
100 | OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f); |
100 | OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f); |
101 | //RADEONPllErrataAfterIndex(); |
101 | //RADEONPllErrataAfterIndex(); |
102 | data = INREG(RADEON_CLOCK_CNTL_DATA); |
102 | data = INREG(RADEON_CLOCK_CNTL_DATA); |
103 | RADEONPllErrataAfterData(); |
103 | RADEONPllErrataAfterData(); |
104 | 104 | ||
105 | return data; |
105 | return data; |
106 | }; |
106 | }; |
107 | 107 | ||
108 | /* Write PLL information */ |
108 | /* Write PLL information */ |
109 | void RADEONOUTPLL(int addr, u32_t data) |
109 | void RADEONOUTPLL(int addr, u32_t data) |
110 | { |
110 | { |
111 | OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) | |
111 | OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) | |
112 | RADEON_PLL_WR_EN)); |
112 | RADEON_PLL_WR_EN)); |
113 | // RADEONPllErrataAfterIndex(info); |
113 | // RADEONPllErrataAfterIndex(info); |
114 | OUTREG(RADEON_CLOCK_CNTL_DATA, data); |
114 | OUTREG(RADEON_CLOCK_CNTL_DATA, data); |
115 | RADEONPllErrataAfterData(); |
115 | RADEONPllErrataAfterData(); |
116 | } |
116 | } |
117 | 117 | ||
118 | 118 | ||
119 | 119 | ||
120 | static Bool |
120 | static Bool |
121 | R5xxFIFOWaitLocal(u32_t required) //R100-R500 |
121 | R5xxFIFOWaitLocal(u32_t required) //R100-R500 |
122 | { |
122 | { |
123 | int i; |
123 | int i; |
124 | 124 | ||
125 | for (i = 0; i < R5XX_LOOP_COUNT; i++) |
125 | for (i = 0; i < R5XX_LOOP_COUNT; i++) |
126 | if (required <= (INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_FIFOCNT_MASK)) |
126 | if (required <= (INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_FIFOCNT_MASK)) |
127 | return TRUE; |
127 | return TRUE; |
128 | 128 | ||
129 | dbgprintf("%s: Timeout 0x%08X.\n", __func__, |
129 | dbgprintf("%s: Timeout 0x%08X.\n", __func__, |
130 | (unsigned int) INREG(R5XX_RBBM_STATUS)); |
130 | (unsigned int) INREG(R5XX_RBBM_STATUS)); |
131 | return FALSE; |
131 | return FALSE; |
132 | } |
132 | } |
133 | 133 | ||
134 | /* |
134 | /* |
135 | * Flush all dirty data in the Pixel Cache to memory. |
135 | * Flush all dirty data in the Pixel Cache to memory. |
136 | */ |
136 | */ |
137 | 137 | ||
138 | static Bool |
138 | static Bool |
139 | R5xx2DFlush() |
139 | R5xx2DFlush() |
140 | { |
140 | { |
141 | int i; |
141 | int i; |
142 | 142 | ||
143 | MASKREG(R5XX_DSTCACHE_CTLSTAT, |
143 | MASKREG(R5XX_DSTCACHE_CTLSTAT, |
144 | R5XX_DSTCACHE_FLUSH_ALL, R5XX_DSTCACHE_FLUSH_ALL); |
144 | R5XX_DSTCACHE_FLUSH_ALL, R5XX_DSTCACHE_FLUSH_ALL); |
145 | 145 | ||
146 | for (i = 0; i < R5XX_LOOP_COUNT; i++) |
146 | for (i = 0; i < R5XX_LOOP_COUNT; i++) |
147 | if (!(INREG(R5XX_DSTCACHE_CTLSTAT) & R5XX_DSTCACHE_BUSY)) |
147 | if (!(INREG(R5XX_DSTCACHE_CTLSTAT) & R5XX_DSTCACHE_BUSY)) |
148 | return TRUE; |
148 | return TRUE; |
149 | 149 | ||
150 | dbgprintf("%s: Timeout 0x%08x.\n", __func__, |
150 | dbgprintf("%s: Timeout 0x%08x.\n", __func__, |
151 | (unsigned int)INREG(R5XX_DSTCACHE_CTLSTAT)); |
151 | (unsigned int)INREG(R5XX_DSTCACHE_CTLSTAT)); |
152 | return FALSE; |
152 | return FALSE; |
153 | } |
153 | } |
154 | 154 | ||
155 | static Bool |
155 | static Bool |
156 | R5xx2DIdleLocal() //R100-R500 |
156 | R5xx2DIdleLocal() //R100-R500 |
157 | { |
157 | { |
158 | int i; |
158 | int i; |
159 | 159 | ||
160 | /* wait for fifo to clear */ |
160 | /* wait for fifo to clear */ |
161 | for (i = 0; i < R5XX_LOOP_COUNT; i++) |
161 | for (i = 0; i < R5XX_LOOP_COUNT; i++) |
162 | if (64 == (INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_FIFOCNT_MASK)) |
162 | if (64 == (INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_FIFOCNT_MASK)) |
163 | break; |
163 | break; |
164 | 164 | ||
165 | if (i == R5XX_LOOP_COUNT) { |
165 | if (i == R5XX_LOOP_COUNT) { |
166 | dbgprintf("%s: FIFO Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS)); |
166 | dbgprintf("%s: FIFO Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS)); |
167 | return FALSE; |
167 | return FALSE; |
168 | } |
168 | } |
169 | 169 | ||
170 | /* wait for engine to go idle */ |
170 | /* wait for engine to go idle */ |
171 | for (i = 0; i < R5XX_LOOP_COUNT; i++) { |
171 | for (i = 0; i < R5XX_LOOP_COUNT; i++) { |
172 | if (!(INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_ACTIVE)) { |
172 | if (!(INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_ACTIVE)) { |
173 | R5xx2DFlush(); |
173 | R5xx2DFlush(); |
174 | return TRUE; |
174 | return TRUE; |
175 | } |
175 | } |
176 | } |
176 | } |
177 | dbgprintf("%s: Idle Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS)); |
177 | dbgprintf("%s: Idle Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS)); |
178 | return FALSE; |
178 | return FALSE; |
179 | 179 | ||
180 | } |
180 | } |
181 | 181 | ||
182 | static void |
182 | static void |
183 | R5xx2DReset() |
183 | R5xx2DReset() |
184 | { |
184 | { |
185 | u32_t save, tmp; |
185 | u32_t save, tmp; |
186 | u32_t clock_cntl_index; |
186 | u32_t clock_cntl_index; |
187 | u32_t mclk_cntl; |
187 | u32_t mclk_cntl; |
188 | 188 | ||
189 | /* The following RBBM_SOFT_RESET sequence can help un-wedge |
189 | /* The following RBBM_SOFT_RESET sequence can help un-wedge |
190 | * an R300 after the command processor got stuck. */ |
190 | * an R300 after the command processor got stuck. */ |
191 | save = INREG(R5XX_RBBM_SOFT_RESET); |
191 | save = INREG(R5XX_RBBM_SOFT_RESET); |
192 | tmp = save | R5XX_SOFT_RESET_CP | |
192 | tmp = save | R5XX_SOFT_RESET_CP | |
193 | R5XX_SOFT_RESET_HI | R5XX_SOFT_RESET_SE | |
193 | R5XX_SOFT_RESET_HI | R5XX_SOFT_RESET_SE | |
194 | R5XX_SOFT_RESET_RE | R5XX_SOFT_RESET_PP | |
194 | R5XX_SOFT_RESET_RE | R5XX_SOFT_RESET_PP | |
195 | R5XX_SOFT_RESET_E2 | R5XX_SOFT_RESET_RB; |
195 | R5XX_SOFT_RESET_E2 | R5XX_SOFT_RESET_RB; |
196 | OUTREG(R5XX_RBBM_SOFT_RESET, tmp); |
196 | OUTREG(R5XX_RBBM_SOFT_RESET, tmp); |
197 | 197 | ||
198 | INREG(R5XX_RBBM_SOFT_RESET); |
198 | INREG(R5XX_RBBM_SOFT_RESET); |
199 | tmp &= ~(R5XX_SOFT_RESET_CP | R5XX_SOFT_RESET_HI | |
199 | tmp &= ~(R5XX_SOFT_RESET_CP | R5XX_SOFT_RESET_HI | |
200 | R5XX_SOFT_RESET_SE | R5XX_SOFT_RESET_RE | |
200 | R5XX_SOFT_RESET_SE | R5XX_SOFT_RESET_RE | |
201 | R5XX_SOFT_RESET_PP | R5XX_SOFT_RESET_E2 | |
201 | R5XX_SOFT_RESET_PP | R5XX_SOFT_RESET_E2 | |
202 | R5XX_SOFT_RESET_RB); |
202 | R5XX_SOFT_RESET_RB); |
203 | OUTREG(R5XX_RBBM_SOFT_RESET, tmp); |
203 | OUTREG(R5XX_RBBM_SOFT_RESET, tmp); |
204 | 204 | ||
205 | INREG(R5XX_RBBM_SOFT_RESET); |
205 | INREG(R5XX_RBBM_SOFT_RESET); |
206 | OUTREG(R5XX_RBBM_SOFT_RESET, save); |
206 | OUTREG(R5XX_RBBM_SOFT_RESET, save); |
207 | INREG(R5XX_RBBM_SOFT_RESET); |
207 | INREG(R5XX_RBBM_SOFT_RESET); |
208 | 208 | ||
209 | R5xx2DFlush(); |
209 | R5xx2DFlush(); |
210 | 210 | ||
211 | #if 0 |
211 | #if 0 |
212 | clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX); |
212 | clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX); |
213 | RADEONPllErrataAfterIndex(info); |
213 | RADEONPllErrataAfterIndex(info); |
214 | 214 | ||
215 | mclk_cntl = RADEONINPLL(RADEON_MCLK_CNTL); |
215 | mclk_cntl = RADEONINPLL(RADEON_MCLK_CNTL); |
216 | 216 | ||
217 | RADEONOUTPLL(RADEON_MCLK_CNTL, (mclk_cntl | |
217 | RADEONOUTPLL(RADEON_MCLK_CNTL, (mclk_cntl | |
218 | RADEON_FORCEON_MCLKA | |
218 | RADEON_FORCEON_MCLKA | |
219 | RADEON_FORCEON_MCLKB | |
219 | RADEON_FORCEON_MCLKB | |
220 | RADEON_FORCEON_YCLKA | |
220 | RADEON_FORCEON_YCLKA | |
221 | RADEON_FORCEON_YCLKB | |
221 | RADEON_FORCEON_YCLKB | |
222 | RADEON_FORCEON_MC | |
222 | RADEON_FORCEON_MC | |
223 | RADEON_FORCEON_AIC)); |
223 | RADEON_FORCEON_AIC)); |
224 | #endif |
224 | #endif |
225 | 225 | ||
226 | /* Soft resetting HDP thru RBBM_SOFT_RESET register can cause some |
226 | /* Soft resetting HDP thru RBBM_SOFT_RESET register can cause some |
227 | * unexpected behaviour on some machines. Here we use |
227 | * unexpected behaviour on some machines. Here we use |
228 | * R5XX_HOST_PATH_CNTL to reset it. */ |
228 | * R5XX_HOST_PATH_CNTL to reset it. */ |
229 | save = INREG(R5XX_HOST_PATH_CNTL); |
229 | save = INREG(R5XX_HOST_PATH_CNTL); |
230 | 230 | ||
231 | tmp = INREG(R5XX_RBBM_SOFT_RESET); |
231 | tmp = INREG(R5XX_RBBM_SOFT_RESET); |
232 | tmp |= R5XX_SOFT_RESET_CP | R5XX_SOFT_RESET_HI | R5XX_SOFT_RESET_E2; |
232 | tmp |= R5XX_SOFT_RESET_CP | R5XX_SOFT_RESET_HI | R5XX_SOFT_RESET_E2; |
233 | OUTREG(R5XX_RBBM_SOFT_RESET, tmp); |
233 | OUTREG(R5XX_RBBM_SOFT_RESET, tmp); |
234 | 234 | ||
235 | INREG(R5XX_RBBM_SOFT_RESET); |
235 | INREG(R5XX_RBBM_SOFT_RESET); |
236 | OUTREG(R5XX_RBBM_SOFT_RESET, 0); |
236 | OUTREG(R5XX_RBBM_SOFT_RESET, 0); |
237 | 237 | ||
238 | MASKREG(R5XX_RB2D_DSTCACHE_MODE, |
238 | MASKREG(R5XX_RB2D_DSTCACHE_MODE, |
239 | R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE, |
239 | R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE, |
240 | R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE); |
240 | R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE); |
241 | 241 | ||
242 | OUTREG(R5XX_HOST_PATH_CNTL, save | R5XX_HDP_SOFT_RESET); |
242 | OUTREG(R5XX_HOST_PATH_CNTL, save | R5XX_HDP_SOFT_RESET); |
243 | INREG(R5XX_HOST_PATH_CNTL); |
243 | INREG(R5XX_HOST_PATH_CNTL); |
244 | OUTREG(R5XX_HOST_PATH_CNTL, save); |
244 | OUTREG(R5XX_HOST_PATH_CNTL, save); |
245 | 245 | ||
246 | #if 0 |
246 | #if 0 |
247 | OUTREG(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); |
247 | OUTREG(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); |
248 | RADEONPllErrataAfterIndex(info); |
248 | RADEONPllErrataAfterIndex(info); |
249 | RADEONOUTPLL(RADEON_MCLK_CNTL, mclk_cntl); |
249 | RADEONOUTPLL(RADEON_MCLK_CNTL, mclk_cntl); |
250 | #endif |
250 | #endif |
251 | } |
251 | } |
252 | 252 | ||
253 | void |
253 | void |
254 | R5xx2DSetup() |
254 | R5xx2DSetup() |
255 | { |
255 | { |
256 | 256 | ||
257 | /* Setup engine location. This shouldn't be necessary since we |
257 | /* Setup engine location. This shouldn't be necessary since we |
258 | * set them appropriately before any accel ops, but let's avoid |
258 | * set them appropriately before any accel ops, but let's avoid |
259 | * random bogus DMA in case we inadvertently trigger the engine |
259 | * random bogus DMA in case we inadvertently trigger the engine |
260 | * in the wrong place (happened). */ |
260 | * in the wrong place (happened). */ |
261 | R5xxFIFOWaitLocal(2); |
261 | R5xxFIFOWaitLocal(2); |
262 | OUTREG(R5XX_DST_PITCH_OFFSET,rhd.dst_pitch_offset); |
262 | OUTREG(R5XX_DST_PITCH_OFFSET,rhd.dst_pitch_offset); |
263 | OUTREG(R5XX_SRC_PITCH_OFFSET,rhd.dst_pitch_offset); |
263 | OUTREG(R5XX_SRC_PITCH_OFFSET,rhd.dst_pitch_offset); |
264 | 264 | ||
265 | R5xxFIFOWaitLocal(1); |
265 | R5xxFIFOWaitLocal(1); |
266 | MASKREG(R5XX_DP_DATATYPE, 0, R5XX_HOST_BIG_ENDIAN_EN); |
266 | MASKREG(R5XX_DP_DATATYPE, 0, R5XX_HOST_BIG_ENDIAN_EN); |
267 | 267 | ||
268 | OUTREG(R5XX_SURFACE_CNTL, rhd.surface_cntl); |
268 | OUTREG(R5XX_SURFACE_CNTL, rhd.surface_cntl); |
269 | 269 | ||
270 | R5xxFIFOWaitLocal(1); |
270 | R5xxFIFOWaitLocal(1); |
271 | OUTREG(R5XX_DEFAULT_SC_BOTTOM_RIGHT, |
271 | OUTREG(R5XX_DEFAULT_SC_BOTTOM_RIGHT, |
272 | R5XX_DEFAULT_SC_RIGHT_MAX | R5XX_DEFAULT_SC_BOTTOM_MAX); |
272 | R5XX_DEFAULT_SC_RIGHT_MAX | R5XX_DEFAULT_SC_BOTTOM_MAX); |
273 | R5xxFIFOWaitLocal(1); |
273 | R5xxFIFOWaitLocal(1); |
274 | OUTREG(R5XX_DP_GUI_MASTER_CNTL, rhd.gui_control | |
274 | OUTREG(R5XX_DP_GUI_MASTER_CNTL, rhd.gui_control | |
275 | R5XX_GMC_BRUSH_SOLID_COLOR | R5XX_GMC_SRC_DATATYPE_COLOR); |
275 | R5XX_GMC_BRUSH_SOLID_COLOR | R5XX_GMC_SRC_DATATYPE_COLOR); |
276 | 276 | ||
277 | R5xxFIFOWaitLocal(5); |
277 | R5xxFIFOWaitLocal(5); |
278 | OUTREG(R5XX_DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); |
278 | OUTREG(R5XX_DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); |
279 | OUTREG(R5XX_DP_BRUSH_BKGD_CLR, 0x00000000); |
279 | OUTREG(R5XX_DP_BRUSH_BKGD_CLR, 0x00000000); |
280 | OUTREG(R5XX_DP_SRC_FRGD_CLR, 0xFFFFFFFF); |
280 | OUTREG(R5XX_DP_SRC_FRGD_CLR, 0xFFFFFFFF); |
281 | OUTREG(R5XX_DP_SRC_BKGD_CLR, 0x00000000); |
281 | OUTREG(R5XX_DP_SRC_BKGD_CLR, 0x00000000); |
282 | OUTREG(R5XX_DP_WRITE_MASK, 0xFFFFFFFF); |
282 | OUTREG(R5XX_DP_WRITE_MASK, 0xFFFFFFFF); |
283 | 283 | ||
284 | R5xx2DIdleLocal(); |
284 | R5xx2DIdleLocal(); |
285 | } |
285 | } |
286 | 286 | ||
287 | void R5xxFIFOWait(u32_t required) |
287 | void R5xxFIFOWait(u32_t required) |
288 | { |
288 | { |
289 | if (!R5xxFIFOWaitLocal(required)) { |
289 | if (!R5xxFIFOWaitLocal(required)) { |
290 | R5xx2DReset(); |
290 | R5xx2DReset(); |
291 | R5xx2DSetup(); |
291 | R5xx2DSetup(); |
292 | } |
292 | } |
293 | } |
293 | } |
294 | 294 | ||
295 | void R5xx2DIdle() |
295 | void R5xx2DIdle() |
296 | { |
296 | { |
297 | if (!R5xx2DIdleLocal()) { |
297 | if (!R5xx2DIdleLocal()) { |
298 | R5xx2DReset(); |
298 | R5xx2DReset(); |
299 | R5xx2DSetup(); |
299 | R5xx2DSetup(); |
300 | } |
300 | } |
301 | } |
301 | } |
302 | 302 | ||
303 | static void load_microcode() |
303 | static void load_microcode() |
304 | { |
304 | { |
305 | u32_t ifl; |
305 | u32_t ifl; |
306 | int i; |
306 | int i; |
307 | 307 | ||
308 | ifl = safe_cli(); |
308 | ifl = safe_cli(); |
309 | 309 | ||
310 | OUTREG(RADEON_CP_ME_RAM_ADDR,0); |
310 | OUTREG(RADEON_CP_ME_RAM_ADDR,0); |
311 | 311 | ||
312 | R5xx2DIdleLocal(); |
312 | R5xx2DIdleLocal(); |
313 | 313 | ||
314 | switch(rhd.ChipSet) |
314 | switch(rhd.ChipFamily) |
315 | { |
315 | { |
316 | case RHD_R300: |
316 | case CHIP_FAMILY_R300: |
317 | case RHD_R350: |
317 | case CHIP_FAMILY_R350: |
318 | case RHD_RV350: |
318 | case CHIP_FAMILY_RV350: |
319 | case RHD_RV370: |
- | |
320 | case RHD_RV380: |
- | |
321 | dbgprintf("Loading R300 microcode\n"); |
319 | dbgprintf("Loading R300 microcode\n"); |
322 | for (i = 0; i < 256; i++) |
320 | for (i = 0; i < 256; i++) |
323 | { |
321 | { |
324 | OUTREG(RADEON_CP_ME_RAM_DATAH, R300_cp_microcode[i][1]); |
322 | OUTREG(RADEON_CP_ME_RAM_DATAH, R300_cp_microcode[i][1]); |
325 | OUTREG(RADEON_CP_ME_RAM_DATAL, R300_cp_microcode[i][0]); |
323 | OUTREG(RADEON_CP_ME_RAM_DATAL, R300_cp_microcode[i][0]); |
326 | } |
324 | } |
327 | break; |
325 | break; |
328 | 326 | /* |
|
329 | case RHD_RV505: |
327 | case RHD_RV505: |
330 | case RHD_RV515: |
328 | case RHD_RV515: |
331 | case RHD_RV516: |
329 | case RHD_RV516: |
332 | case RHD_R520: |
330 | case RHD_R520: |
333 | case RHD_RV530: |
331 | case RHD_RV530: |
334 | case RHD_RV535: |
332 | case RHD_RV535: |
335 | case RHD_RV550: |
333 | case RHD_RV550: |
336 | case RHD_RV560: |
334 | case RHD_RV560: |
337 | case RHD_RV570: |
335 | case RHD_RV570: |
338 | case RHD_R580: |
336 | case RHD_R580: |
339 | dbgprintf("Loading R500 microcode\n"); |
337 | dbgprintf("Loading R500 microcode\n"); |
340 | for (i = 0; i < 256; i++) |
338 | for (i = 0; i < 256; i++) |
341 | { |
339 | { |
342 | OUTREG(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]); |
340 | OUTREG(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]); |
343 | OUTREG(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]); |
341 | OUTREG(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]); |
344 | } |
342 | } |
345 | } |
343 | */ |
- | 344 | } |
|
346 | safe_sti(ifl); |
345 | safe_sti(ifl); |
347 | }; |
346 | }; |
348 | 347 | ||
349 | 348 | ||
350 | void R5xx2DInit() |
349 | void R5xx2DInit() |
351 | { |
350 | { |
352 | u32_t base; |
351 | u32_t base; |
353 | int screensize; |
352 | int screensize; |
354 | int screenpitch; |
353 | int screenpitch; |
355 | 354 | ||
356 | screensize = GetScreenSize(); |
355 | screensize = GetScreenSize(); |
357 | screenpitch = GetScreenPitch(); |
356 | screenpitch = GetScreenPitch(); |
358 | 357 | ||
359 | rhd.displayWidth = screensize >> 16; |
358 | rhd.displayWidth = screensize >> 16; |
360 | rhd.displayHeight = screensize & 0xFFFF; |
359 | rhd.displayHeight = screensize & 0xFFFF; |
361 | 360 | ||
362 | rhd.__xmin = 0; |
361 | rhd.__xmin = 0; |
363 | rhd.__ymin = 0; |
362 | rhd.__ymin = 0; |
364 | rhd.__xmax = rhd.displayWidth - 1; |
363 | rhd.__xmax = rhd.displayWidth - 1; |
365 | rhd.__ymax = rhd.displayHeight - 1; |
364 | rhd.__ymax = rhd.displayHeight - 1; |
366 | 365 | ||
367 | clip.xmin = 0; |
366 | clip.xmin = 0; |
368 | clip.ymin = 0; |
367 | clip.ymin = 0; |
369 | clip.xmax = rhd.displayWidth - 1; |
368 | clip.xmax = rhd.displayWidth - 1; |
370 | clip.ymax = rhd.displayHeight - 1; |
369 | clip.ymax = rhd.displayHeight - 1; |
371 | 370 | ||
372 | dbgprintf("width %d \n", rhd.displayWidth); |
371 | dbgprintf("width %d \n", rhd.displayWidth); |
373 | dbgprintf("height %d \n", rhd.displayHeight); |
372 | dbgprintf("height %d \n", rhd.displayHeight); |
374 | 373 | ||
375 | rhd.gui_control = (R5XX_DATATYPE_ARGB8888 << R5XX_GMC_DST_DATATYPE_SHIFT) | |
374 | rhd.gui_control = (R5XX_DATATYPE_ARGB8888 << R5XX_GMC_DST_DATATYPE_SHIFT) | |
376 | R5XX_GMC_CLR_CMP_CNTL_DIS | R5XX_GMC_DST_PITCH_OFFSET_CNTL; |
375 | R5XX_GMC_CLR_CMP_CNTL_DIS | R5XX_GMC_DST_PITCH_OFFSET_CNTL; |
377 | 376 | ||
378 | dbgprintf("gui_control %x \n", rhd.gui_control); |
377 | dbgprintf("gui_control %x \n", rhd.gui_control); |
379 | 378 | ||
380 | rhd.surface_cntl = 0; |
379 | rhd.surface_cntl = 0; |
381 | rhd.dst_pitch_offset = ((screenpitch / 64) << 22) | |
380 | rhd.dst_pitch_offset = ((screenpitch / 64) << 22) | (rhd.fbLocation >> 10); |
382 | ((rhd.FbIntAddress + rhd.FbScanoutStart) >> 10); |
381 | |
383 | - | ||
384 | dbgprintf("dst_pitch_offset %x \n", rhd.dst_pitch_offset); |
382 | dbgprintf("dst_pitch_offset %x \n", rhd.dst_pitch_offset); |
385 | 383 | ||
386 | 384 | ||
387 | scr_pixmap.width = rhd.displayWidth; |
385 | scr_pixmap.width = rhd.displayWidth; |
388 | scr_pixmap.height = rhd.displayHeight; |
386 | scr_pixmap.height = rhd.displayHeight; |
389 | scr_pixmap.format = PICT_a8r8g8b8; |
387 | scr_pixmap.format = PICT_a8r8g8b8; |
390 | scr_pixmap.pitch = screenpitch; |
388 | scr_pixmap.pitch = screenpitch; |
391 | scr_pixmap.local = (void*)rhd.FbIntAddress; |
389 | scr_pixmap.local = (void*)rhd.fbLocation; |
392 | scr_pixmap.pitch_offset = rhd.dst_pitch_offset; |
390 | scr_pixmap.pitch_offset = rhd.dst_pitch_offset; |
393 | scr_pixmap.mapped = (void*)0; |
391 | scr_pixmap.mapped = (void*)0; |
394 | 392 | ||
395 | 393 | ||
396 | MASKREG(R5XX_GB_TILE_CONFIG, 0, R5XX_ENABLE_TILING); |
394 | MASKREG(R5XX_GB_TILE_CONFIG, 0, R5XX_ENABLE_TILING); |
397 | OUTREG (R5XX_WAIT_UNTIL, R5XX_WAIT_2D_IDLECLEAN | R5XX_WAIT_3D_IDLECLEAN); |
395 | OUTREG (R5XX_WAIT_UNTIL, R5XX_WAIT_2D_IDLECLEAN | R5XX_WAIT_3D_IDLECLEAN); |
398 | MASKREG(R5XX_DST_PIPE_CONFIG, R5XX_PIPE_AUTO_CONFIG, R5XX_PIPE_AUTO_CONFIG); |
396 | MASKREG(R5XX_DST_PIPE_CONFIG, R5XX_PIPE_AUTO_CONFIG, R5XX_PIPE_AUTO_CONFIG); |
399 | MASKREG(R5XX_RB2D_DSTCACHE_MODE, |
397 | MASKREG(R5XX_RB2D_DSTCACHE_MODE, |
400 | R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE, |
398 | R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE, |
401 | R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE); |
399 | R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE); |
402 | 400 | ||
403 | 401 | ||
404 | R5xx2DReset(); |
402 | R5xx2DReset(); |
405 | R5xx2DSetup(); |
403 | R5xx2DSetup(); |
406 | 404 | ||
407 | MASKREG( RADEON_AIC_CNTL,0, RADEON_PCIGART_TRANSLATE_EN); |
405 | MASKREG( RADEON_AIC_CNTL,0, RADEON_PCIGART_TRANSLATE_EN); |
408 | 406 | ||
409 | // load_microcode(); |
407 | // load_microcode(); |
410 | 408 | ||
411 | // rhd.ring_base = CreateRingBuffer(0x8000, PG_SW | PG_NOCACHE); |
409 | // rhd.ring_base = CreateRingBuffer(0x8000, PG_SW | PG_NOCACHE); |
412 | // dbgprintf("create cp ring buffer %x\n", rhd.ring_base); |
410 | // dbgprintf("create cp ring buffer %x\n", rhd.ring_base); |
413 | // base = GetPgAddr(rhd.ring_base); |
411 | // base = GetPgAddr(rhd.ring_base); |
414 | 412 | ||
415 | // OUTREG(RADEON_CP_RB_BASE, base); |
413 | // OUTREG(RADEON_CP_RB_BASE, base); |
416 | // dbgprintf("ring base %x\n", base); |
414 | // dbgprintf("ring base %x\n", base); |
417 | 415 | ||
418 | // OUTREG(RADEON_CP_RB_WPTR_DELAY, 0); |
416 | // OUTREG(RADEON_CP_RB_WPTR_DELAY, 0); |
419 | 417 | ||
420 | // rhd.ring_rp = rhd.ring_wp = INREG(RADEON_CP_RB_RPTR); |
418 | // rhd.ring_rp = rhd.ring_wp = INREG(RADEON_CP_RB_RPTR); |
421 | // OUTREG(RADEON_CP_RB_WPTR,rhd.ring_rp); |
419 | // OUTREG(RADEON_CP_RB_WPTR,rhd.ring_rp); |
422 | 420 | ||
423 | // OUTREG(RADEON_CP_RB_RPTR_ADDR, 0); // ring buffer read pointer no update |
421 | // OUTREG(RADEON_CP_RB_RPTR_ADDR, 0); // ring buffer read pointer no update |
424 | 422 | ||
425 | // OUTREG(RADEON_CP_RB_CNTL, RADEON_RB_NO_UPDATE | 12); |
423 | // OUTREG(RADEON_CP_RB_CNTL, RADEON_RB_NO_UPDATE | 12); |
426 | // OUTREG(RADEON_SCRATCH_UMSK, 0); // no scratch update |
424 | // OUTREG(RADEON_SCRATCH_UMSK, 0); // no scratch update |
427 | 425 | ||
428 | // MASKREG(RADEON_BUS_CNTL,0,RADEON_BUS_MASTER_DIS); |
426 | // MASKREG(RADEON_BUS_CNTL,0,RADEON_BUS_MASTER_DIS); |
429 | 427 | ||
430 | // R5xx2DIdleLocal(); |
428 | // R5xx2DIdleLocal(); |
431 | 429 | ||
432 | // OUTREG(RADEON_ISYNC_CNTL, RADEON_ISYNC_ANY2D_IDLE3D | |
430 | // OUTREG(RADEON_ISYNC_CNTL, RADEON_ISYNC_ANY2D_IDLE3D | |
433 | // RADEON_ISYNC_ANY3D_IDLE2D | |
431 | // RADEON_ISYNC_ANY3D_IDLE2D | |
434 | // RADEON_ISYNC_WAIT_IDLEGUI | |
432 | // RADEON_ISYNC_WAIT_IDLEGUI | |
435 | // RADEON_ISYNC_CPSCRATCH_IDLEGUI); |
433 | // RADEON_ISYNC_CPSCRATCH_IDLEGUI); |
436 | 434 | ||
437 | // OUTREG(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); // run |
435 | // OUTREG(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); // run |
438 | 436 | ||
439 | }><>><>>>>>>=>>=>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |
437 | }><>><>>>>>>=>>=>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |