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Rev 885 Rev 1002
Line 18... Line 18...
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#	define RADEON_ISYNC_WAIT_IDLEGUI	(1 << 4)
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#	define RADEON_ISYNC_WAIT_IDLEGUI	(1 << 4)
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#	define RADEON_ISYNC_CPSCRATCH_IDLEGUI	(1 << 5)
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#	define RADEON_ISYNC_CPSCRATCH_IDLEGUI	(1 << 5)
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#define RADEON_IDLE_RETRY      16 /* Fall out of idle loops after this count */
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#define RADEON_TIMEOUT    2000000 /* Fall out of wait loops after this count */
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void RADEONPllErrataAfterIndex()
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{
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    if (!(rhd.ChipErrata & CHIP_ERRATA_PLL_DUMMYREADS))
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       return;
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    /* This workaround is necessary on rv200 and RS200 or PLL
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     * reads may return garbage (among others...)
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     */
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    (void)INREG(RADEON_CLOCK_CNTL_DATA);
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    (void)INREG(RADEON_CRTC_GEN_CNTL);
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}
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void RADEONPllErrataAfterData()
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{
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    /* This function is required to workaround a hardware bug in some (all?)
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     * revisions of the R300.  This workaround should be called after every
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     * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
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     * may not be correct.
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     */
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    if (rhd.ChipFamily <= CHIP_FAMILY_RV380)
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    {
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        u32_t save, tmp;
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	save = INREG(RADEON_CLOCK_CNTL_INDEX);
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	tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
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	OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp);
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	tmp = INREG(RADEON_CLOCK_CNTL_DATA);
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	OUTREG(RADEON_CLOCK_CNTL_INDEX, save);
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    }
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}
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/* Read PLL register */
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u32_t RADEONINPLL(int addr)
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{
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    u32_t       data;
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    OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f);
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    RADEONPllErrataAfterIndex();
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    data = INREG(RADEON_CLOCK_CNTL_DATA);
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    RADEONPllErrataAfterData();
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    return data;
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};
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/* Write PLL information */
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void RADEONOUTPLL(int addr, u32_t data)
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{
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    OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) |
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				      RADEON_PLL_WR_EN));
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    RADEONPllErrataAfterIndex();
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#define RADEON_IDLE_RETRY      16 /* Fall out of idle loops after this count */
79 
    OUTREG(RADEON_CLOCK_CNTL_DATA, data);
 23 
#define RADEON_TIMEOUT    4000000 /* Fall out of wait loops after this count */
80 
    RADEONPllErrataAfterData();
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 90 
 
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    return 1;
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    return 1;
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}
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static void init_pipes(RHDPtr info)
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{
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     u32_t gb_tile_config = 0;
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     if ( (info->ChipFamily == CHIP_FAMILY_RV410) ||
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          (info->ChipFamily == CHIP_FAMILY_R420)  ||
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          (info->ChipFamily == CHIP_FAMILY_RS600) ||
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          (info->ChipFamily == CHIP_FAMILY_RS690) ||
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          (info->ChipFamily == CHIP_FAMILY_RS740) ||
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          (info->ChipFamily == CHIP_FAMILY_RS400) ||
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          (info->ChipFamily == CHIP_FAMILY_RS480) || IS_R500_3D)
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     {
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         u32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT);
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         info->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
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         if (IS_R500_3D)
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            OUTPLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
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168 
     }
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     else
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     {
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171 
        if ((info->ChipFamily == CHIP_FAMILY_R300) ||
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            (info->ChipFamily == CHIP_FAMILY_R350))
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        {
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174 
         /* R3xx chips */
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175 
            info->num_gb_pipes = 2;
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        }
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        else {
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         /* RV3xx chips */
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179 
           info->num_gb_pipes = 1;
 - 
 
180 
        }
 - 
 
181 
     }
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182 
 
 - 
 
183 
     if (IS_R300_3D || IS_R500_3D)
 - 
 
184 
     {
 - 
 
185 
 
 - 
 
186 
        dbgprintf("num quad-pipes is %d\n", info->num_gb_pipes);
 - 
 
187 
 
 - 
 
188 
        switch(info->num_gb_pipes) {
 - 
 
189 
           case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
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190 
           case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
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191 
           case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
 - 
 
192 
           default:
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193 
           case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
 - 
 
194 
        }
 - 
 
195 
 
 - 
 
196 
        OUTREG(R300_GB_TILE_CONFIG, gb_tile_config);
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197 
        OUTREG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 - 
 
198 
        OUTREG(R300_DST_PIPE_CONFIG, INREG(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
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        OUTREG(R300_RB2D_DSTCACHE_MODE, (INREG(R300_RB2D_DSTCACHE_MODE) |
 - 
 
200 
                                        R300_DC_AUTOFLUSH_ENABLE |
 - 
 
201 
                                        R300_DC_DC_DISABLE_IGNORE_PE));
 - 
 
202 
    }
 - 
 
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203 
    else
 92 
}
204 
       OUTREG(RADEON_RB3D_CNTL, 0);
 93 
 
205 
};
 94 
 
Line 499... Line 388...
499 
     rhd.ring_rp = rhd.ring_wp = INREG(RADEON_CP_RB_RPTR);
 388 
     rhd.ring_rp = rhd.ring_wp = INREG(RADEON_CP_RB_RPTR);
500 
     OUTREG(RADEON_CP_RB_WPTR, rhd.ring_rp);
 389 
     OUTREG(RADEON_CP_RB_WPTR, rhd.ring_rp);
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Line -... Line 391...
- 
 
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     radeon_cp_start(&rhd);
502 
     radeon_cp_start(&rhd);
 392