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Rev 885 | Rev 1002 | ||
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Line 17... | Line 17... | ||
17 | 17 | ||
18 | if ((info->ChipFamily == CHIP_FAMILY_RS690) || |
18 | if ((info->ChipFamily == CHIP_FAMILY_RS690) || |
Line 19... | Line 19... | ||
19 | (info->ChipFamily == CHIP_FAMILY_RS740)) { |
19 | (info->ChipFamily == CHIP_FAMILY_RS740)) { |
20 | OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); |
20 | OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); |
21 | data = INREG(RS690_MC_DATA); |
21 | data = INREG(RS690_MC_DATA); |
22 | } else if (info->ChipFamily == CHIP_FAMILY_RS600) { |
22 | } else if (info->ChipFamily == CHIP_FAMILY_RS600) { |
23 | OUTREG(RS600_MC_INDEX, (addr & RS600_MC_INDEX_MASK)); |
23 | OUTREG(RS600_MC_INDEX, (addr & RS600_MC_INDEX_MASK)); |
24 | data = INREG(RS600_MC_DATA); |
24 | data = INREG(RS600_MC_DATA); |
25 | } else if (IS_AVIVO_VARIANT) { |
25 | } else if (IS_AVIVO_VARIANT) { |
26 | OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000); |
26 | OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000); |
27 | (void)INREG(AVIVO_MC_INDEX); |
27 | (void)INREG(AVIVO_MC_INDEX); |
28 | data = INREG(AVIVO_MC_DATA); |
28 | data = INREG(AVIVO_MC_DATA); |
29 | 29 | ||
Line 30... | Line 30... | ||
30 | OUTREG(AVIVO_MC_INDEX, 0); |
30 | OUTREG(AVIVO_MC_INDEX, 0); |
31 | (void)INREG(AVIVO_MC_INDEX); |
31 | (void)INREG(AVIVO_MC_INDEX); |
32 | } else { |
32 | } else { |
33 | OUTREG(R300_MC_IND_INDEX, addr & 0x3f); |
33 | OUTREG(R300_MC_IND_INDEX, addr & 0x3f); |
34 | (void)INREG(R300_MC_IND_INDEX); |
34 | (void)INREG(R300_MC_IND_INDEX); |
35 | data = INREG(R300_MC_IND_DATA); |
35 | data = INREG(R300_MC_IND_DATA); |
Line 36... | Line 36... | ||
36 | 36 | ||
37 | OUTREG(R300_MC_IND_INDEX, 0); |
37 | OUTREG(R300_MC_IND_INDEX, 0); |
38 | (void)INREG(R300_MC_IND_INDEX); |
38 | (void)INREG(R300_MC_IND_INDEX); |
Line 39... | Line 39... | ||
39 | } |
39 | } |
40 | 40 | ||
Line 41... | Line 41... | ||
41 | return data; |
41 | return data; |
42 | } |
42 | } |
43 | 43 | ||
44 | /* Write MC information */ |
44 | /* Write MC information */ |
45 | void OUTMC(RHDPtr info, int addr, u32_t data) |
45 | void OUTMC(RHDPtr info, int addr, u32_t data) |
46 | { |
46 | { |
47 | if ((info->ChipFamily == CHIP_FAMILY_RS690) || |
47 | if ((info->ChipFamily == CHIP_FAMILY_RS690) || |
48 | (info->ChipFamily == CHIP_FAMILY_RS740)) { |
48 | (info->ChipFamily == CHIP_FAMILY_RS740)) { |
49 | OUTREG(RS690_MC_INDEX, ((addr & RS690_MC_INDEX_MASK) | RS690_MC_INDEX_WR_EN)); |
49 | OUTREG(RS690_MC_INDEX, ((addr & RS690_MC_INDEX_MASK) | RS690_MC_INDEX_WR_EN)); |
50 | OUTREG(RS690_MC_DATA, data); |
50 | OUTREG(RS690_MC_DATA, data); |
51 | OUTREG(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); |
51 | OUTREG(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); |
52 | } |
52 | } |
53 | else if (info->ChipFamily == CHIP_FAMILY_RS600) { |
53 | else if (info->ChipFamily == CHIP_FAMILY_RS600) { |
54 | OUTREG(RS600_MC_INDEX, ((addr & RS600_MC_INDEX_MASK) | RS600_MC_INDEX_WR_EN)); |
54 | OUTREG(RS600_MC_INDEX, ((addr & RS600_MC_INDEX_MASK) | RS600_MC_INDEX_WR_EN)); |
55 | OUTREG(RS600_MC_DATA, data); |
55 | OUTREG(RS600_MC_DATA, data); |
56 | OUTREG(RS600_MC_INDEX, RS600_MC_INDEX_WR_ACK); |
56 | OUTREG(RS600_MC_INDEX, RS600_MC_INDEX_WR_ACK); |
57 | } |
57 | } |
58 | else if (IS_AVIVO_VARIANT) { |
58 | else if (IS_AVIVO_VARIANT) { |
59 | OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0xff0000); |
59 | OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0xff0000); |
60 | (void)INREG(AVIVO_MC_INDEX); |
60 | (void)INREG(AVIVO_MC_INDEX); |
61 | OUTREG(AVIVO_MC_DATA, data); |
61 | OUTREG(AVIVO_MC_DATA, data); |
62 | OUTREG(AVIVO_MC_INDEX, 0); |
62 | OUTREG(AVIVO_MC_INDEX, 0); |
63 | (void)INREG(AVIVO_MC_INDEX); |
63 | (void)INREG(AVIVO_MC_INDEX); |
64 | } |
64 | } |
65 | else { |
65 | else { |
66 | OUTREG(R300_MC_IND_INDEX, (((addr) & 0x3f) | R300_MC_IND_WR_EN)); |
66 | OUTREG(R300_MC_IND_INDEX, (((addr) & 0x3f) | R300_MC_IND_WR_EN)); |
67 | (void)INREG(R300_MC_IND_INDEX); |
67 | (void)INREG(R300_MC_IND_INDEX); |
68 | OUTREG(R300_MC_IND_DATA, data); |
68 | OUTREG(R300_MC_IND_DATA, data); |
69 | OUTREG(R300_MC_IND_INDEX, 0); |
69 | OUTREG(R300_MC_IND_INDEX, 0); |
Line 70... | Line 70... | ||
70 | (void)INREG(R300_MC_IND_INDEX); |
70 | (void)INREG(R300_MC_IND_INDEX); |
71 | } |
71 | } |
Line 72... | Line 72... | ||
72 | } |
72 | } |
73 | 73 | ||
74 | static Bool avivo_get_mc_idle(RHDPtr info) |
74 | static Bool avivo_get_mc_idle(RHDPtr info) |
75 | { |
75 | { |
76 | 76 | ||
77 | if (info->ChipFamily >= CHIP_FAMILY_R600) { |
77 | if (info->ChipFamily >= CHIP_FAMILY_R600) { |
78 | /* no idea where this is on r600 yet */ |
78 | /* no idea where this is on r600 yet */ |
79 | return TRUE; |
79 | return TRUE; |
80 | } |
80 | } |
81 | else if (info->ChipFamily == CHIP_FAMILY_RV515) { |
81 | else if (info->ChipFamily == CHIP_FAMILY_RV515) { |
82 | if (INMC(info, RV515_MC_STATUS) & RV515_MC_STATUS_IDLE) |
82 | if (INMC(info, RV515_MC_STATUS) & RV515_MC_STATUS_IDLE) |
83 | return TRUE; |
83 | return TRUE; |
84 | else |
84 | else |
85 | return FALSE; |
85 | return FALSE; |
86 | } |
86 | } |
87 | else if (info->ChipFamily == CHIP_FAMILY_RS600) |
87 | else if (info->ChipFamily == CHIP_FAMILY_RS600) |
88 | { |
88 | { |
89 | if (INMC(info, RS600_MC_STATUS) & RS600_MC_STATUS_IDLE) |
89 | if (INMC(info, RS600_MC_STATUS) & RS600_MC_STATUS_IDLE) |
90 | return TRUE; |
90 | return TRUE; |
91 | else |
91 | else |
92 | return FALSE; |
92 | return FALSE; |
93 | } |
93 | } |
94 | else if ((info->ChipFamily == CHIP_FAMILY_RS690) || |
94 | else if ((info->ChipFamily == CHIP_FAMILY_RS690) || |
95 | (info->ChipFamily == CHIP_FAMILY_RS740)) { |
95 | (info->ChipFamily == CHIP_FAMILY_RS740)) { |
96 | if (INMC(info, RS690_MC_STATUS) & RS690_MC_STATUS_IDLE) |
96 | if (INMC(info, RS690_MC_STATUS) & RS690_MC_STATUS_IDLE) |
97 | return TRUE; |
97 | return TRUE; |
98 | else |
98 | else |
99 | return FALSE; |
99 | return FALSE; |
100 | } |
100 | } |
101 | else { |
101 | else { |
102 | if (INMC(info, R520_MC_STATUS) & R520_MC_STATUS_IDLE) |
102 | if (INMC(info, R520_MC_STATUS) & R520_MC_STATUS_IDLE) |
Line 103... | Line 103... | ||
103 | return TRUE; |
103 | return TRUE; |
104 | else |
104 | else |
Line 446... | Line 446... | ||
446 | #endif |
446 | #endif |
Line 447... | Line 447... | ||
447 | 447 | ||
Line 448... | Line -... | ||
448 | - | ||
449 | 448 | ||
450 | static void RADEONInitMemoryMap(RHDPtr info) |
449 | static void RADEONInitMemoryMap(RHDPtr info) |
451 | { |
450 | { |
452 | u32_t mem_size; |
451 | u32_t mem_size; |
Line 453... | Line 452... | ||
453 | u32_t aper_size; |
452 | u32_t aper_size; |
454 | 453 | ||
Line 455... | Line 454... | ||
455 | radeon_read_mc_fb_agp_location(info, LOC_FB | LOC_AGP, &info->mc_fb_location, |
454 | radeon_read_mc_fb_agp_location(info, LOC_FB | LOC_AGP, &info->mc_fb_location, |
456 | &info->mc_agp_location, &info->mc_agp_location_hi); |
455 | &info->mc_agp_location, &info->mc_agp_location_hi); |
Line 457... | Line 456... | ||
457 | 456 | ||
458 | dbgprintf(" MC_FB_LOCATION : 0x%08x\n", (unsigned)info->mc_fb_location); |
457 | dbgprintf(" MC_FB_LOCATION : 0x%08x\n", (unsigned)info->mc_fb_location); |
459 | dbgprintf(" MC_AGP_LOCATION : 0x%08x\n", (unsigned)info->mc_agp_location); |
458 | dbgprintf(" MC_AGP_LOCATION : 0x%08x\n", (unsigned)info->mc_agp_location); |
460 | 459 | ||
461 | 460 | ||
462 | /* We shouldn't use info->videoRam here which might have been clipped |
461 | /* We shouldn't use info->videoRam here which might have been clipped |
463 | * but the real video RAM instead |
462 | * but the real video RAM instead |
464 | */ |
463 | */ |
465 | if (info->ChipFamily >= CHIP_FAMILY_R600){ |
464 | if (info->ChipFamily >= CHIP_FAMILY_R600){ |
466 | mem_size = INREG(R600_CONFIG_MEMSIZE); |
465 | mem_size = INREG(R600_CONFIG_MEMSIZE); |
467 | aper_size = INREG(R600_CONFIG_APER_SIZE); |
466 | aper_size = INREG(R600_CONFIG_APER_SIZE); |
Line 468... | Line 467... | ||
468 | } |
467 | } |
469 | else { |
468 | else { |
Line 470... | Line 469... | ||
470 | mem_size = INREG(RADEON_CONFIG_MEMSIZE); |
469 | mem_size = INREG(RADEON_CONFIG_MEMSIZE); |
471 | aper_size = INREG(RADEON_CONFIG_APER_SIZE); |
470 | aper_size = INREG(RADEON_CONFIG_APER_SIZE); |
472 | } |
471 | } |
473 | 472 | ||
Line 474... | Line 473... | ||
474 | if (mem_size == 0) |
473 | if (mem_size == 0) |
475 | mem_size = 0x800000; |
474 | mem_size = 0x800000; |
476 | 475 | ||
- | 476 | /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - |
|
477 | /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - |
477 | Novell bug 204882 + along with lots of ubuntu ones */ |
478 | Novell bug 204882 + along with lots of ubuntu ones */ |
478 | if (aper_size > mem_size) |
479 | if (aper_size > mem_size) |
479 | mem_size = aper_size; |
480 | mem_size = aper_size; |
480 | |
481 | 481 | ||
Line 482... | Line 482... | ||
482 | 482 | if ( (info->ChipFamily != CHIP_FAMILY_RS600) && |
|
483 | if ( (info->ChipFamily != CHIP_FAMILY_RS600) && |
483 | (info->ChipFamily != CHIP_FAMILY_RS690) && |
484 | (info->ChipFamily != CHIP_FAMILY_RS690) && |
484 | (info->ChipFamily != CHIP_FAMILY_RS740)) |
485 | (info->ChipFamily != CHIP_FAMILY_RS740)) { |
485 | { |
486 | if (info->IsIGP) |
486 | if (info->IsIGP) |
487 | info->mc_fb_location = INREG(RADEON_NB_TOM); |
487 | info->mc_fb_location = INREG(RADEON_NB_TOM); |
488 | else |
488 | else |
489 | { |
489 | { |
490 | u32_t aper0_base; |
490 | u32_t aper0_base; |
491 | 491 | ||
492 | if (info->ChipFamily >= CHIP_FAMILY_R600) { |
492 | if (info->ChipFamily >= CHIP_FAMILY_R600) { |
493 | aper0_base = INREG(R600_CONFIG_F0_BASE); |
493 | aper0_base = INREG(R600_CONFIG_F0_BASE); |
494 | } |
494 | } |
495 | else { |
495 | else { |
496 | aper0_base = INREG(RADEON_CONFIG_APER_0_BASE); |
496 | aper0_base = INREG(RADEON_CONFIG_APER_0_BASE); |
497 | } |
497 | } |
498 | dbgprintf("aper0 base %x\n", aper0_base ); |
498 | dbgprintf("aper0 base %x\n", aper0_base ); |
499 | 499 | ||
500 | /* Recent chips have an "issue" with the memory controller, the |
500 | /* Recent chips have an "issue" with the memory controller, the |
501 | * location must be aligned to the size. We just align it down, |
501 | * location must be aligned to the size. We just align it down, |
502 | * too bad if we walk over the top of system memory, we don't |
502 | * too bad if we walk over the top of system memory, we don't |
503 | * use DMA without a remapped anyway. |
503 | * use DMA without a remapped anyway. |
504 | * Affected chips are rv280, all r3xx, and all r4xx, but not IGP |
504 | * Affected chips are rv280, all r3xx, and all r4xx, but not IGP |
505 | */ |
505 | */ |
506 | if ( info->ChipFamily == CHIP_FAMILY_RV280 || |
506 | if ( info->ChipFamily == CHIP_FAMILY_RV280 || |
507 | info->ChipFamily == CHIP_FAMILY_R300 || |
507 | info->ChipFamily == CHIP_FAMILY_R300 || |
508 | info->ChipFamily == CHIP_FAMILY_R350 || |
508 | info->ChipFamily == CHIP_FAMILY_R350 || |
509 | info->ChipFamily == CHIP_FAMILY_RV350 || |
509 | info->ChipFamily == CHIP_FAMILY_RV350 || |
510 | info->ChipFamily == CHIP_FAMILY_RV380 || |
510 | info->ChipFamily == CHIP_FAMILY_RV380 || |
511 | info->ChipFamily == CHIP_FAMILY_R420 || |
511 | info->ChipFamily == CHIP_FAMILY_R420 || |
512 | info->ChipFamily == CHIP_FAMILY_RV410) |
512 | info->ChipFamily == CHIP_FAMILY_RV410) |
513 | aper0_base &= ~(mem_size - 1); |
513 | aper0_base &= ~(mem_size - 1); |
514 | 514 | ||
515 | if ( info->ChipFamily >= CHIP_FAMILY_R600) { |
515 | if ( info->ChipFamily >= CHIP_FAMILY_R600) { |
516 | info->mc_fb_location = (aper0_base >> 24) | |
516 | info->mc_fb_location = (aper0_base >> 24) | |
517 | (((aper0_base + mem_size - 1) & 0xff000000U) >> 8); |
517 | (((aper0_base + mem_size - 1) & 0xff000000U) >> 8); |
518 | dbgprintf("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location); |
518 | dbgprintf("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location); |
519 | } |
519 | } |
520 | else { |
520 | else { |
521 | info->mc_fb_location = (aper0_base >> 16) | |
521 | info->mc_fb_location = (aper0_base >> 16) | |
522 | ((aper0_base + mem_size - 1) & 0xffff0000U); |
522 | ((aper0_base + mem_size - 1) & 0xffff0000U); |
523 | dbgprintf("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location); |
523 | dbgprintf("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location); |
524 | } |
524 | } |
525 | } |
525 | } |
Line 526... | Line 526... | ||
526 | } |
526 | } |
527 | if (info->ChipFamily >= CHIP_FAMILY_R600) { |
527 | if (info->ChipFamily >= CHIP_FAMILY_R600) { |
528 | info->fbLocation = (info->mc_fb_location & 0xffff) << 24; |
528 | info->fbLocation = (info->mc_fb_location & 0xffff) << 24; |
529 | } |
529 | } |
530 | else { |
530 | else { |
531 | info->fbLocation = (info->mc_fb_location & 0xffff) << 16; |
531 | info->fbLocation = (info->mc_fb_location & 0xffff) << 16; |
532 | } |
532 | } |
533 | /* Just disable the damn AGP apertures for now, it may be |
533 | /* Just disable the damn AGP apertures for now, it may be |
534 | * re-enabled later by the DRM |
534 | * re-enabled later by the DRM |
535 | */ |
535 | */ |
536 | 536 | ||
537 | // if (IS_AVIVO_VARIANT) { |
537 | // if (IS_AVIVO_VARIANT) { |
538 | // if (info->ChipFamily >= CHIP_FAMILY_R600) { |
538 | // if (info->ChipFamily >= CHIP_FAMILY_R600) { |
539 | // OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000); |
539 | // OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000); |
540 | // } |
540 | // } |
541 | // else { |
541 | // else { |
542 | // OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location); |
542 | // OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location); |
Line 543... | Line 543... | ||
543 | // } |
543 | // } |
Line 544... | Line 544... | ||
544 | // info->mc_agp_location = 0x003f0000; |
544 | // info->mc_agp_location = 0x003f0000; |
Line 545... | Line 545... | ||
545 | // } |
545 | // } |
Line 546... | Line 546... | ||
546 | // else |
546 | // else |
Line 811... | Line 811... | ||
811 | 811 | ||
Line 812... | Line 812... | ||
812 | static Bool RADEONPreInitChipType(RHDPtr rhdPtr) |
812 | static Bool RADEONPreInitChipType(RHDPtr rhdPtr) |
813 | { |
813 | { |
814 | u32_t cmd_stat; |
814 | u32_t cmd_stat; |
Line 815... | Line 815... | ||
815 | 815 | ||
Line 816... | Line 816... | ||
816 | rhdPtr->ChipErrata = 0; |
816 | rhdPtr->ChipErrata = 0; |
817 | 817 | ||
818 | if ( (rhdPtr->ChipFamily == CHIP_FAMILY_R300) && |
818 | if ( (rhdPtr->ChipFamily == CHIP_FAMILY_R300) && |
819 | ((_RHDRegRead(rhdPtr,RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) |
819 | ((_RHDRegRead(rhdPtr,RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) |
Line 820... | Line 820... | ||
820 | == RADEON_CFG_ATI_REV_A11)) |
820 | == RADEON_CFG_ATI_REV_A11)) |
821 | rhdPtr->ChipErrata |= CHIP_ERRATA_R300_CG; |
821 | rhdPtr->ChipErrata |= CHIP_ERRATA_R300_CG; |
822 | 822 | ||
Line 823... | Line 823... | ||
823 | if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV200) || |
823 | if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV200) || |
824 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS200) ) |
824 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS200) ) |
825 | rhdPtr->ChipErrata |= CHIP_ERRATA_PLL_DUMMYREADS; |
825 | rhdPtr->ChipErrata |= CHIP_ERRATA_PLL_DUMMYREADS; |
826 | 826 | ||
Line 827... | Line 827... | ||
827 | if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV100) || |
827 | if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV100) || |
Line 828... | Line 828... | ||
828 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS100) || |
828 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS100) || |
Line 829... | Line 829... | ||
829 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS200) ) |
829 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS200) ) |
830 | rhdPtr->ChipErrata |= CHIP_ERRATA_PLL_DELAY; |
830 | rhdPtr->ChipErrata |= CHIP_ERRATA_PLL_DELAY; |
831 | 831 | ||
Line 832... | Line 832... | ||
832 | rhdPtr->cardType = CARD_PCI; |
832 | rhdPtr->cardType = CARD_PCI; |
833 | 833 | ||
Line 834... | Line 834... | ||
834 | 834 | ||
835 | cmd_stat = pciReadLong(rhdPtr->PciTag, PCI_CMD_STAT_REG); |
835 | cmd_stat = pciReadLong(rhdPtr->PciTag, PCI_CMD_STAT_REG); |
836 | 836 | ||
837 | if (cmd_stat & RADEON_CAP_LIST) |
837 | if (cmd_stat & RADEON_CAP_LIST) |
838 | { |
838 | { |
839 | u32_t cap_ptr, cap_id; |
839 | u32_t cap_ptr, cap_id; |
840 | 840 | ||
841 | cap_ptr = pciReadLong(rhdPtr->PciTag, RADEON_CAPABILITIES_PTR_PCI_CONFIG); |
841 | cap_ptr = pciReadLong(rhdPtr->PciTag, RADEON_CAPABILITIES_PTR_PCI_CONFIG); |
842 | cap_ptr &= RADEON_CAP_PTR_MASK; |
842 | cap_ptr &= RADEON_CAP_PTR_MASK; |
843 | 843 | ||
844 | while(cap_ptr != RADEON_CAP_ID_NULL) |
844 | while(cap_ptr != RADEON_CAP_ID_NULL) |
845 | { |
845 | { |
846 | cap_id = pciReadLong(rhdPtr->PciTag, cap_ptr); |
846 | cap_id = pciReadLong(rhdPtr->PciTag, cap_ptr); |
847 | if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) { |
847 | if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) { |
Line 848... | Line 848... | ||
848 | rhdPtr->cardType = CARD_AGP; |
848 | rhdPtr->cardType = CARD_AGP; |
849 | break; |
849 | break; |
Line 850... | Line 850... | ||
850 | } |
850 | } |
851 | if ((cap_id & 0xff)== RADEON_CAP_ID_EXP) { |
851 | if ((cap_id & 0xff)== RADEON_CAP_ID_EXP) { |
852 | rhdPtr->cardType = CARD_PCIE; |
852 | rhdPtr->cardType = CARD_PCIE; |
Line 853... | Line 853... | ||
853 | break; |
853 | break; |
854 | } |
854 | } |
855 | cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK; |
855 | cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK; |
856 | } |
856 | } |
857 | } |
857 | } |
858 | 858 | ||
859 | dbgprintf("%s card detected\n",(rhdPtr->cardType==CARD_PCI) ? "PCI" : |
859 | dbgprintf("%s card detected\n",(rhdPtr->cardType==CARD_PCI) ? "PCI" : |
860 | (rhdPtr->cardType==CARD_PCIE) ? "PCIE" : "AGP"); |
860 | (rhdPtr->cardType==CARD_PCIE) ? "PCIE" : "AGP"); |
861 | 861 | ||
862 | /* treat PCIE IGP cards as PCI */ |
862 | /* treat PCIE IGP cards as PCI */ |
863 | if (rhdPtr->cardType == CARD_PCIE && rhdPtr->IsIGP) |
863 | if (rhdPtr->cardType == CARD_PCIE && rhdPtr->IsIGP) |
864 | rhdPtr->cardType = CARD_PCI; |
864 | rhdPtr->cardType = CARD_PCI; |
Line 865... | Line 865... | ||
865 | 865 | ||
Line 866... | Line 866... | ||
866 | if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RS100) || |
866 | if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RS100) || |
867 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS200) || |
867 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS200) || |
Line 868... | Line 868... | ||
868 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS300) || |
868 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS300) || |
869 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS400) || |
869 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS400) || |
870 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS480) || |
870 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS480) || |
Line 956... | Line 956... | ||
956 | RHDPtr info; |
956 | RHDPtr info; |
957 | 957 | ||
958 | /* We need access to IO space already */ |
958 | /* We need access to IO space already */ |
Line 959... | Line 959... | ||
959 | if ( !rhdMapMMIO(&rhd) ) { |
959 | if ( !rhdMapMMIO(&rhd) ) { |
960 | dbgprintf("Failed to map MMIO.\n"); |
960 | dbgprintf("Failed to map MMIO.\n"); |
961 | return FALSE; |
961 | return FALSE; |
962 | }; |
962 | }; |
963 | 963 | ||
Line 964... | Line 964... | ||
964 | 964 | ||
965 | if( !RADEONPreInitChipType(&rhd)) |
965 | if( !RADEONPreInitChipType(&rhd)) |
Line 966... | Line 966... | ||
966 | return FALSE; |
966 | return FALSE; |
967 | 967 | ||
Line 968... | Line 968... | ||
968 | if (!RADEONPreInitVRAM(&rhd)) |
968 | if (!RADEONPreInitVRAM(&rhd)) |
Line 969... | Line 969... | ||
969 | return FALSE; |
969 | return FALSE; |
970 | 970 | ||
971 | RADEONInitMemoryMap(&rhd); |
971 | RADEONInitMemoryMap(&rhd); |
972 | 972 | ||
973 | if (!rhd.videoRam) |
973 | if (!rhd.videoRam) |
974 | { |
974 | { |
Line 975... | Line 975... | ||
975 | dbgprintf("No Video RAM detected.\n"); |
975 | dbgprintf("No Video RAM detected.\n"); |
976 | goto error1; |
976 | goto error1; |
Line 977... | Line 977... | ||
977 | } |
977 | } |
978 | dbgprintf("VideoRAM: %d kByte\n",rhd.videoRam); |
978 | dbgprintf("VideoRAM: %d kByte\n",rhd.videoRam); |
Line 979... | Line 979... | ||
979 | 979 | ||
980 | // rhd.FbFreeStart = 0; |
980 | // rhd.FbFreeStart = 0; |
Line 981... | Line 981... | ||
981 | rhd.FbFreeSize = rhd.videoRam << 10; |
981 | rhd.FbFreeSize = rhd.videoRam << 10; |
982 | 982 | ||
Line 983... | Line 983... | ||
983 | // if( !rhdMapFB(&rhd)) |
983 | // if( !rhdMapFB(&rhd)) |
Line 984... | Line 984... | ||
984 | // return FALSE; |
984 | // return FALSE; |
Line 985... | Line -... | ||
985 | - | ||
986 | // rhd.FbScanoutStart = 0; |
985 | |
Line 987... | Line 986... | ||
987 | // rhd.FbScanoutSize = 8*1024*1024; |
986 | // rhd.FbScanoutStart = 0; |
- | 987 | // rhd.FbScanoutSize = 8*1024*1024; |
|
988 | 988 | ||
989 | rhd.FbFreeStart = 10*1024*1024; |
989 | rhd.FbFreeStart = 10*1024*1024; |
Line -... | Line 990... | ||
- | 990 | rhd.FbFreeSize = rhd.FbMapSize - rhd.FbFreeStart - rhd.FbSecureSize; |
|
- | 991 | ||
- | 992 | rhdInitHeap(&rhd); |
|
- | 993 | ||
- | 994 | info = &rhd; |
|
- | 995 | ||
- | 996 | return TRUE; |
|
- | 997 | ||
- | 998 | error1: |
|
- | 999 | ||
- | 1000 | return FALSE; |
|
- | 1001 | }; |
|
- | 1002 | ||
- | 1003 | static void RADEONPllErrataAfterIndex() |
|
- | 1004 | { |
|
- | 1005 | if (!(rhd.ChipErrata & CHIP_ERRATA_PLL_DUMMYREADS)) |
|
- | 1006 | return; |
|
- | 1007 | ||
- | 1008 | /* This workaround is necessary on rv200 and RS200 or PLL |
|
- | 1009 | * reads may return garbage (among others...) |
|
- | 1010 | */ |
|
- | 1011 | (void)INREG(RADEON_CLOCK_CNTL_DATA); |
|
- | 1012 | (void)INREG(RADEON_CRTC_GEN_CNTL); |
|
- | 1013 | } |
|
- | 1014 | ||
- | 1015 | ||
- | 1016 | static void RADEONPllErrataAfterData() |
|
- | 1017 | { |
|
- | 1018 | ||
- | 1019 | /* This function is required to workaround a hardware bug in some (all?) |
|
- | 1020 | * revisions of the R300. This workaround should be called after every |
|
- | 1021 | * CLOCK_CNTL_INDEX register access. If not, register reads afterward |
|
- | 1022 | * may not be correct. |
|
- | 1023 | */ |
|
- | 1024 | if (rhd.ChipFamily <= CHIP_FAMILY_RV380) |
|
- | 1025 | { |
|
- | 1026 | u32_t save, tmp; |
|
- | 1027 | ||
- | 1028 | save = INREG(RADEON_CLOCK_CNTL_INDEX); |
|
- | 1029 | tmp = save & ~(0x3f | RADEON_PLL_WR_EN); |
|
- | 1030 | OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp); |
|
- | 1031 | tmp = INREG(RADEON_CLOCK_CNTL_DATA); |
|
- | 1032 | OUTREG(RADEON_CLOCK_CNTL_INDEX, save); |
|
- | 1033 | } |
|
- | 1034 | } |
|
- | 1035 | ||
- | 1036 | ||
- | 1037 | /* Read PLL register */ |
|
- | 1038 | static u32_t RADEONINPLL(int addr) |
|
- | 1039 | { |
|
- | 1040 | u32_t data; |
|
- | 1041 | ||
- | 1042 | OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f); |
|
- | 1043 | RADEONPllErrataAfterIndex(); |
|
- | 1044 | data = INREG(RADEON_CLOCK_CNTL_DATA); |
|
- | 1045 | RADEONPllErrataAfterData(); |
|
- | 1046 | ||
- | 1047 | return data; |
|
- | 1048 | }; |
|
- | 1049 | ||
- | 1050 | /* Write PLL information */ |
|
- | 1051 | static void RADEONOUTPLL(int addr, u32_t data) |
|
- | 1052 | { |
|
- | 1053 | OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) | |
|
- | 1054 | RADEON_PLL_WR_EN)); |
|
- | 1055 | RADEONPllErrataAfterIndex(); |
|
- | 1056 | OUTREG(RADEON_CLOCK_CNTL_DATA, data); |
|
- | 1057 | RADEONPllErrataAfterData(); |
|
- | 1058 | } |
|
- | 1059 | ||
- | 1060 | static void init_pipes(RHDPtr info) |
|
- | 1061 | { |
|
- | 1062 | u32_t gb_tile_config = 0; |
|
- | 1063 | ||
- | 1064 | if ( (info->ChipFamily == CHIP_FAMILY_RV410) || |
|
- | 1065 | (info->ChipFamily == CHIP_FAMILY_R420) || |
|
- | 1066 | (info->ChipFamily == CHIP_FAMILY_RS600) || |
|
- | 1067 | (info->ChipFamily == CHIP_FAMILY_RS690) || |
|
- | 1068 | (info->ChipFamily == CHIP_FAMILY_RS740) || |
|
- | 1069 | (info->ChipFamily == CHIP_FAMILY_RS400) || |
|
- | 1070 | (info->ChipFamily == CHIP_FAMILY_RS480) || IS_R500_3D) |
|
- | 1071 | { |
|
- | 1072 | u32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT); |
|
- | 1073 | ||
- | 1074 | info->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; |
|
- | 1075 | if (IS_R500_3D) |
|
- | 1076 | OUTPLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); |
|
- | 1077 | } |
|
- | 1078 | else |
|
- | 1079 | { |
|
- | 1080 | if ((info->ChipFamily == CHIP_FAMILY_R300) || |
|
- | 1081 | (info->ChipFamily == CHIP_FAMILY_R350)) |
|
- | 1082 | { |
|
- | 1083 | /* R3xx chips */ |
|
- | 1084 | info->num_gb_pipes = 2; |
|
- | 1085 | } |
|
- | 1086 | else { |
|
- | 1087 | /* RV3xx chips */ |
|
- | 1088 | info->num_gb_pipes = 1; |
|
- | 1089 | } |
|
- | 1090 | } |
|
- | 1091 | ||
- | 1092 | if (IS_R300_3D || IS_R500_3D) |
|
- | 1093 | { |
|
- | 1094 | ||
- | 1095 | dbgprintf("num quad-pipes is %d\n", info->num_gb_pipes); |
|
- | 1096 | ||
- | 1097 | switch(info->num_gb_pipes) { |
|
- | 1098 | case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; |
|
- | 1099 | case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; |
|
- | 1100 | case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; |
|
- | 1101 | default: |