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Rev 885 Rev 1002
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#endif
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#endif
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 - 
 
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static void RADEONInitMemoryMap(RHDPtr info)
 449 
static void RADEONInitMemoryMap(RHDPtr info)
451 
{
 450 
{
452 
     u32_t       mem_size;
 451 
    u32_t       mem_size;
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 481 
 
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     if ( (info->ChipFamily != CHIP_FAMILY_RS600) &&
 482 
    if ( (info->ChipFamily != CHIP_FAMILY_RS600) &&
484 
          (info->ChipFamily != CHIP_FAMILY_RS690) &&
 483 
         (info->ChipFamily != CHIP_FAMILY_RS690) &&
485 
          (info->ChipFamily != CHIP_FAMILY_RS740)) {
 484 
         (info->ChipFamily != CHIP_FAMILY_RS740))
- 
 
 485 
    {
486 
        if (info->IsIGP)
 486 
        if (info->IsIGP)
487 
           info->mc_fb_location = INREG(RADEON_NB_TOM);
 487 
          info->mc_fb_location = INREG(RADEON_NB_TOM);
488 
        else
 488 
        else
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        {
 489 
        {
490 
           u32_t aper0_base;
 490 
            u32_t aper0_base;
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 993 
 
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     info = &rhd;
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    info = &rhd;
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 - 
 
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   return TRUE;
 996 
    return TRUE;
- 
 
 997 
 
998 
 
 998 
error1:
999 
error1:
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    return FALSE;
- 
 
 1001 
};
- 
 
 1002 
 
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 1003 
static void RADEONPllErrataAfterIndex()
- 
 
 1004 
{
- 
 
 1005 
    if (!(rhd.ChipErrata & CHIP_ERRATA_PLL_DUMMYREADS))
- 
 
 1006 
       return;
- 
 
 1007 
 
- 
 
 1008 
    /* This workaround is necessary on rv200 and RS200 or PLL
- 
 
 1009 
     * reads may return garbage (among others...)
- 
 
 1010 
     */
- 
 
 1011 
    (void)INREG(RADEON_CLOCK_CNTL_DATA);
- 
 
 1012 
    (void)INREG(RADEON_CRTC_GEN_CNTL);
- 
 
 1013 
}
- 
 
 1014 
 
- 
 
 1015 
 
- 
 
 1016 
static void RADEONPllErrataAfterData()
- 
 
 1017 
{
- 
 
 1018 
 
- 
 
 1019 
    /* This function is required to workaround a hardware bug in some (all?)
- 
 
 1020 
     * revisions of the R300.  This workaround should be called after every
- 
 
 1021 
     * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
- 
 
 1022 
     * may not be correct.
- 
 
 1023 
     */
- 
 
 1024 
    if (rhd.ChipFamily <= CHIP_FAMILY_RV380)
- 
 
 1025 
    {
- 
 
 1026 
        u32_t save, tmp;
- 
 
 1027 
 
- 
 
 1028 
	save = INREG(RADEON_CLOCK_CNTL_INDEX);
- 
 
 1029 
	tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
- 
 
 1030 
	OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp);
- 
 
 1031 
	tmp = INREG(RADEON_CLOCK_CNTL_DATA);
- 
 
 1032 
	OUTREG(RADEON_CLOCK_CNTL_INDEX, save);
- 
 
 1033 
    }
- 
 
 1034 
}
- 
 
 1035 
 
- 
 
 1036 
 
- 
 
 1037 
/* Read PLL register */
- 
 
 1038 
static u32_t RADEONINPLL(int addr)
- 
 
 1039 
{
- 
 
 1040 
    u32_t       data;
- 
 
 1041 
 
- 
 
 1042 
    OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f);
- 
 
 1043 
    RADEONPllErrataAfterIndex();
- 
 
 1044 
    data = INREG(RADEON_CLOCK_CNTL_DATA);
- 
 
 1045 
    RADEONPllErrataAfterData();
- 
 
 1046 
 
- 
 
 1047 
    return data;
- 
 
 1048 
};
- 
 
 1049 
 
- 
 
 1050 
/* Write PLL information */
- 
 
 1051 
static void RADEONOUTPLL(int addr, u32_t data)
- 
 
 1052 
{
- 
 
 1053 
    OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) |
- 
 
 1054 
				      RADEON_PLL_WR_EN));
- 
 
 1055 
    RADEONPllErrataAfterIndex();
- 
 
 1056 
    OUTREG(RADEON_CLOCK_CNTL_DATA, data);
- 
 
 1057 
    RADEONPllErrataAfterData();
- 
 
 1058 
}
- 
 
 1059 
 
- 
 
 1060 
static void init_pipes(RHDPtr info)
- 
 
 1061 
{
- 
 
 1062 
    u32_t gb_tile_config = 0;
- 
 
 1063 
 
- 
 
 1064 
    if ( (info->ChipFamily == CHIP_FAMILY_RV410) ||
- 
 
 1065 
         (info->ChipFamily == CHIP_FAMILY_R420)  ||
- 
 
 1066 
         (info->ChipFamily == CHIP_FAMILY_RS600) ||
- 
 
 1067 
         (info->ChipFamily == CHIP_FAMILY_RS690) ||
- 
 
 1068 
         (info->ChipFamily == CHIP_FAMILY_RS740) ||
- 
 
 1069 
         (info->ChipFamily == CHIP_FAMILY_RS400) ||
- 
 
 1070 
         (info->ChipFamily == CHIP_FAMILY_RS480) || IS_R500_3D)
- 
 
 1071 
    {
- 
 
 1072 
        u32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT);
- 
 
 1073 
 
- 
 
 1074 
        info->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
- 
 
 1075 
        if (IS_R500_3D)
- 
 
 1076 
            OUTPLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
- 
 
 1077 
    }
- 
 
 1078 
    else
- 
 
 1079 
    {
- 
 
 1080 
        if ((info->ChipFamily == CHIP_FAMILY_R300) ||
- 
 
 1081 
           (info->ChipFamily == CHIP_FAMILY_R350))
- 
 
 1082 
        {
- 
 
 1083 
        /* R3xx chips */
- 
 
 1084 
            info->num_gb_pipes = 2;
- 
 
 1085 
        }
- 
 
 1086 
        else {
- 
 
 1087 
        /* RV3xx chips */
- 
 
 1088 
            info->num_gb_pipes = 1;
- 
 
 1089 
        }
- 
 
 1090 
    }
- 
 
 1091 
 
- 
 
 1092 
    if (IS_R300_3D || IS_R500_3D)
- 
 
 1093 
    {
- 
 
 1094 
 
- 
 
 1095 
        dbgprintf("num quad-pipes is %d\n", info->num_gb_pipes);
- 
 
 1096 
 
- 
 
 1097 
        switch(info->num_gb_pipes) {
- 
 
 1098 
            case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
- 
 
 1099 
            case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
- 
 
 1100 
            case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
- 
 
 1101 
            default:
- 
 
 1102 
                case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
- 
 
 1103 
        }
- 
 
 1104 
 
- 
 
 1105 
        OUTREG(R300_GB_TILE_CONFIG, gb_tile_config);
- 
 
 1106 
        OUTREG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
- 
 
 1107 
        OUTREG(R300_DST_PIPE_CONFIG, INREG(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
- 
 
 1108 
        OUTREG(R300_RB2D_DSTCACHE_MODE, (INREG(R300_RB2D_DSTCACHE_MODE) |
- 
 
 1109 
                                       R300_DC_AUTOFLUSH_ENABLE |
- 
 
 1110 
                                       R300_DC_DC_DISABLE_IGNORE_PE));
- 
 
 1111 
    }