Rev 883 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 883 | Rev 885 | ||
|---|---|---|---|
| Line 320... | Line 320... | ||
| 320 | ring[1] = (val); \ |
320 | ring[1] = (val); \ |
| 321 | ring+= 2; \ |
321 | ring+= 2; \ |
| 322 | } while (0) |
322 | } while (0) |
| 323 | 323 | ||
| Line 324... | Line 324... | ||
| 324 | #define DRM_MEMORYBARRIER() __asm volatile("lock; addl $0,0(%%esp)" : : : "memory"); |
324 | #define DRM_MEMORYBARRIER() __asm__ volatile("lock; addl $0,0(%%esp)" : : : "memory"); |
| Line 325... | Line 325... | ||
| 325 | 325 | ||
| 326 | #define COMMIT_RING() do { \ |
326 | #define COMMIT_RING() do { \ |
| 327 | rhd.ring_wp = (ring - rhd.ringBase) & 0x3FFF; \ |
327 | rhd.ring_wp = (ring - rhd.ringBase) & 0x3FFF; \ |
| 328 | /* Flush writes to ring */ \ |
328 | /* Flush writes to ring */ \ |
| Line 332... | Line 332... | ||
| 332 | /* read from PCI bus to ensure correct posting */ \ |
332 | /* read from PCI bus to ensure correct posting */ \ |
| 333 | /* INREG( RADEON_CP_RB_RPTR ); */ \ |
333 | /* INREG( RADEON_CP_RB_RPTR ); */ \ |
| 334 | } while (0) |
334 | } while (0) |
| 335 | 335 | ||
| Line -... | Line 336... | ||
| - | 336 | #define BEGIN_ACCEL(n) BEGIN_RING(2*(n)) |
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| - | 337 | #define FINISH_ACCEL() COMMIT_RING() |
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| - | 338 | ||
| - | 339 | #define OUT_ACCEL_REG(reg, val) CP_REG((reg), (val)) |
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| Line 336... | Line 340... | ||
| 336 | 340 | ||
| 337 | 341 | ||
| 338 | typedef struct { |
342 | typedef struct { |