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1 
#include "radeon_reg.h"
 - 
 
2 
 
 1 
#define BEGIN_ACCEL(n)          BEGIN_RING(2*(n))
3 
#define BEGIN_ACCEL(n)          BEGIN_RING(2*(n))
 2 
//#define FINISH_ACCEL()          ADVANCE_RING()
4 
//#define FINISH_ACCEL()          ADVANCE_RING()
 3 
#define FINISH_ACCEL()          COMMIT_RING()
5 
#define FINISH_ACCEL()          COMMIT_RING()
 4 
 
6 
 
 5 
#define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val)
7 
#define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val)
 6 
 
8 
 
 7 
#define RADEON_SWITCH_TO_3D()                                           \
9 
#define RADEON_SWITCH_TO_3D()                                           \
 8 
do {									\
10 
do {									\
 9 
        u32_t wait_until = 0;                        \
11 
        u32_t wait_until = 0;                        \
 10 
	BEGIN_ACCEL(1);							\
12 
	BEGIN_ACCEL(1);							\
 11 
        wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN;        \
13 
        wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN;        \
 12 
	OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until);			\
14 
	OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until);			\
 13 
	FINISH_ACCEL();							\
15 
	FINISH_ACCEL();							\
 14 
} while (0);
16 
} while (0);
 15 
 
17 
 
 16 
 
18 
 
 17 
struct blendinfo {
19 
struct blendinfo {
 18 
    Bool dst_alpha;
20 
    Bool dst_alpha;
 19 
    Bool src_alpha;
21 
    Bool src_alpha;
 20 
    u32_t blend_cntl;
22 
    u32_t blend_cntl;
 21 
};
23 
};
 22 
 
24 
 
 23 
static struct blendinfo RadeonBlendOp[] = {
25 
static struct blendinfo RadeonBlendOp[] = {
 24 
    /* 0 - Clear */
26 
    /* 0 - Clear */
 25 
    {0, 0, RADEON_SRC_BLEND_GL_ZERO	      | RADEON_DST_BLEND_GL_ZERO},
27 
    {0, 0, RADEON_SRC_BLEND_GL_ZERO	      | RADEON_DST_BLEND_GL_ZERO},
 26 
    /* 1 - Src */
28 
    /* 1 - Src */
 27 
    {0, 0, RADEON_SRC_BLEND_GL_ONE	      | RADEON_DST_BLEND_GL_ZERO},
29 
    {0, 0, RADEON_SRC_BLEND_GL_ONE	      | RADEON_DST_BLEND_GL_ZERO},
 28 
    /* 2 - Dst */
30 
    /* 2 - Dst */
 29 
    {0, 0, RADEON_SRC_BLEND_GL_ZERO	      | RADEON_DST_BLEND_GL_ONE},
31 
    {0, 0, RADEON_SRC_BLEND_GL_ZERO	      | RADEON_DST_BLEND_GL_ONE},
 30 
    /* 3 - Over */
32 
    /* 3 - Over */
 31 
    {0, 1, RADEON_SRC_BLEND_GL_ONE	      | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
33 
    {0, 1, RADEON_SRC_BLEND_GL_ONE	      | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
 32 
    /* 4 - OverReverse */
34 
    /* 4 - OverReverse */
 33 
    {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE},
35 
    {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE},
 34 
    /* 5 - In */
36 
    /* 5 - In */
 35 
    {1, 0, RADEON_SRC_BLEND_GL_DST_ALPHA     | RADEON_DST_BLEND_GL_ZERO},
37 
    {1, 0, RADEON_SRC_BLEND_GL_DST_ALPHA     | RADEON_DST_BLEND_GL_ZERO},
 36 
    /* 6 - InReverse */
38 
    /* 6 - InReverse */
 37 
    {0, 1, RADEON_SRC_BLEND_GL_ZERO	      | RADEON_DST_BLEND_GL_SRC_ALPHA},
39 
    {0, 1, RADEON_SRC_BLEND_GL_ZERO	      | RADEON_DST_BLEND_GL_SRC_ALPHA},
 38 
    /* 7 - Out */
40 
    /* 7 - Out */
 39 
    {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ZERO},
41 
    {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ZERO},
 40 
    /* 8 - OutReverse */
42 
    /* 8 - OutReverse */
 41 
    {0, 1, RADEON_SRC_BLEND_GL_ZERO	      | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
43 
    {0, 1, RADEON_SRC_BLEND_GL_ZERO	      | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
 42 
    /* 9 - Atop */
44 
    /* 9 - Atop */
 43 
    {1, 1, RADEON_SRC_BLEND_GL_DST_ALPHA     | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
45 
    {1, 1, RADEON_SRC_BLEND_GL_DST_ALPHA     | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
 44 
    /* 10- AtopReverse */
46 
    /* 10- AtopReverse */
 45 
    {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_SRC_ALPHA},
47 
    {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_SRC_ALPHA},
 46 
    /* 11 - Xor */
48 
    /* 11 - Xor */
 47 
    {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
49 
    {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
 48 
    /* 12 - Add */
50 
    /* 12 - Add */
 49 
    {0, 0, RADEON_SRC_BLEND_GL_ONE	      | RADEON_DST_BLEND_GL_ONE},
51 
    {0, 0, RADEON_SRC_BLEND_GL_ONE	      | RADEON_DST_BLEND_GL_ONE},
 50 
};
52 
};
 51 
 
53 
 
 52 
 
54 
 
 53 
static void Init3DEngine(RHDPtr rhdPtr)
55 
static void Init3DEngine(RHDPtr rhdPtr)
 54 
{
56 
{
 55 
   // RADEONInfoPtr  info       = RADEONPTR(pScrn);
57 
   // RADEONInfoPtr  info       = RADEONPTR(pScrn);
 56 
    u32_t gb_tile_config, su_reg_dest, vap_cntl;
58 
    u32_t gb_tile_config, su_reg_dest, vap_cntl;
 57 
   // ACCEL_PREAMBLE();
59 
   // ACCEL_PREAMBLE();
 58 
 
60 
 
 59 
    u32_t *ring, write;
61 
    u32_t *ring, write;
 60 
 
62 
 
 61 
   // info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1;
63 
   // info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1;
 62 
 
64 
 
 63 
    if (IS_R300_3D || IS_R500_3D)
65 
    if (IS_R300_3D || IS_R500_3D)
 64 
    {
66 
    {
 65 
 
67 
 
 66 
        BEGIN_ACCEL(3);
68 
        BEGIN_ACCEL(3);
 67 
	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
69 
	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
 68 
	OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
70 
	OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
 69 
	OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
71 
	OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 70 
	FINISH_ACCEL();
72 
	FINISH_ACCEL();
 71 
 
73 
 
 72 
        if ( IS_R500_3D)
74 
        if ( IS_R500_3D)
 73 
        {
75 
        {
 74 
           u32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT);
76 
           u32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT);
 75 
 
77 
 
 76 
           rhdPtr->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
78 
           rhdPtr->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
 77 
           RADEONOUTPLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
79 
           RADEONOUTPLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
 78 
	}
80 
	}
 79 
 
81 
 
 80 
        dbgprintf("Pipes count %d\n", rhdPtr->num_gb_pipes );
82 
        dbgprintf("Pipes count %d\n", rhdPtr->num_gb_pipes );
 81 
 
83 
 
 82 
	gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16);
84 
	gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16);
 83 
 
85 
 
 84 
        switch(rhdPtr->num_gb_pipes) {
86 
        switch(rhdPtr->num_gb_pipes) {
 85 
	case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
87 
	case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
 86 
	case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
88 
	case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
 87 
	case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
89 
	case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
 88 
	default:
90 
	default:
 89 
	case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
91 
	case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
 90 
	}
92 
	}
 91 
 
93 
 
 92 
	BEGIN_ACCEL(5);
94 
	BEGIN_ACCEL(5);
 93 
	OUT_ACCEL_REG(R300_GB_TILE_CONFIG, gb_tile_config);
95 
	OUT_ACCEL_REG(R300_GB_TILE_CONFIG, gb_tile_config);
 94 
	OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
96 
	OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 95 
	OUT_ACCEL_REG(R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG);
97 
	OUT_ACCEL_REG(R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG);
 96 
	OUT_ACCEL_REG(R300_GB_SELECT, 0);
98 
	OUT_ACCEL_REG(R300_GB_SELECT, 0);
 97 
	OUT_ACCEL_REG(R300_GB_ENABLE, 0);
99 
	OUT_ACCEL_REG(R300_GB_ENABLE, 0);
 98 
	FINISH_ACCEL();
100 
	FINISH_ACCEL();
 99 
 
101 
 
 100 
	if (IS_R500_3D) {
102 
	if (IS_R500_3D) {
 101 
            su_reg_dest = ((1 << rhdPtr->num_gb_pipes) - 1);
103 
            su_reg_dest = ((1 << rhdPtr->num_gb_pipes) - 1);
 102 
	    BEGIN_ACCEL(2);
104 
	    BEGIN_ACCEL(2);
 103 
	    OUT_ACCEL_REG(R500_SU_REG_DEST, su_reg_dest);
105 
	    OUT_ACCEL_REG(R500_SU_REG_DEST, su_reg_dest);
 104 
	    OUT_ACCEL_REG(R500_VAP_INDEX_OFFSET, 0);
106 
	    OUT_ACCEL_REG(R500_VAP_INDEX_OFFSET, 0);
 105 
	    FINISH_ACCEL();
107 
	    FINISH_ACCEL();
 106 
	}
108 
	}
 107 
 
109 
 
 108 
	BEGIN_ACCEL(3);
110 
	BEGIN_ACCEL(3);
 109 
	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
111 
	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
 110 
	OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
112 
	OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
 111 
	OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
113 
	OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 112 
	FINISH_ACCEL();
114 
	FINISH_ACCEL();
 113 
 
115 
 
 114 
	BEGIN_ACCEL(5);
116 
	BEGIN_ACCEL(5);
 115 
	OUT_ACCEL_REG(R300_GB_AA_CONFIG, 0);
117 
	OUT_ACCEL_REG(R300_GB_AA_CONFIG, 0);
 116 
	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
118 
	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
 117 
	OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
119 
	OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
 118 
	OUT_ACCEL_REG(R300_GB_MSPOS0, ((8 << R300_MS_X0_SHIFT) |
120 
	OUT_ACCEL_REG(R300_GB_MSPOS0, ((8 << R300_MS_X0_SHIFT) |
 119 
				       (8 << R300_MS_Y0_SHIFT) |
121 
				       (8 << R300_MS_Y0_SHIFT) |
 120 
				       (8 << R300_MS_X1_SHIFT) |
122 
				       (8 << R300_MS_X1_SHIFT) |
 121 
				       (8 << R300_MS_Y1_SHIFT) |
123 
				       (8 << R300_MS_Y1_SHIFT) |
 122 
				       (8 << R300_MS_X2_SHIFT) |
124 
				       (8 << R300_MS_X2_SHIFT) |
 123 
				       (8 << R300_MS_Y2_SHIFT) |
125 
				       (8 << R300_MS_Y2_SHIFT) |
 124 
				       (8 << R300_MSBD0_Y_SHIFT) |
126 
				       (8 << R300_MSBD0_Y_SHIFT) |
 125 
				       (7 << R300_MSBD0_X_SHIFT)));
127 
				       (7 << R300_MSBD0_X_SHIFT)));
 126 
	OUT_ACCEL_REG(R300_GB_MSPOS1, ((8 << R300_MS_X3_SHIFT) |
128 
	OUT_ACCEL_REG(R300_GB_MSPOS1, ((8 << R300_MS_X3_SHIFT) |
 127 
				       (8 << R300_MS_Y3_SHIFT) |
129 
				       (8 << R300_MS_Y3_SHIFT) |
 128 
				       (8 << R300_MS_X4_SHIFT) |
130 
				       (8 << R300_MS_X4_SHIFT) |
 129 
				       (8 << R300_MS_Y4_SHIFT) |
131 
				       (8 << R300_MS_Y4_SHIFT) |
 130 
				       (8 << R300_MS_X5_SHIFT) |
132 
				       (8 << R300_MS_X5_SHIFT) |
 131 
				       (8 << R300_MS_Y5_SHIFT) |
133 
				       (8 << R300_MS_Y5_SHIFT) |
 132 
				       (8 << R300_MSBD1_SHIFT)));
134 
				       (8 << R300_MSBD1_SHIFT)));
 133 
	FINISH_ACCEL();
135 
	FINISH_ACCEL();
 134 
 
136 
 
 135 
	BEGIN_ACCEL(5);
137 
	BEGIN_ACCEL(5);
 136 
	OUT_ACCEL_REG(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
138 
	OUT_ACCEL_REG(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
 137 
	OUT_ACCEL_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
139 
	OUT_ACCEL_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
 138 
	OUT_ACCEL_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST |
140 
	OUT_ACCEL_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST |
 139 
					   R300_COLOR_ROUND_NEAREST));
141 
					   R300_COLOR_ROUND_NEAREST));
 140 
	OUT_ACCEL_REG(R300_GA_COLOR_CONTROL, (R300_RGB0_SHADING_GOURAUD |
142 
	OUT_ACCEL_REG(R300_GA_COLOR_CONTROL, (R300_RGB0_SHADING_GOURAUD |
 141 
					      R300_ALPHA0_SHADING_GOURAUD |
143 
					      R300_ALPHA0_SHADING_GOURAUD |
 142 
					      R300_RGB1_SHADING_GOURAUD |
144 
					      R300_RGB1_SHADING_GOURAUD |
 143 
					      R300_ALPHA1_SHADING_GOURAUD |
145 
					      R300_ALPHA1_SHADING_GOURAUD |
 144 
					      R300_RGB2_SHADING_GOURAUD |
146 
					      R300_RGB2_SHADING_GOURAUD |
 145 
					      R300_ALPHA2_SHADING_GOURAUD |
147 
					      R300_ALPHA2_SHADING_GOURAUD |
 146 
					      R300_RGB3_SHADING_GOURAUD |
148 
					      R300_RGB3_SHADING_GOURAUD |
 147 
					      R300_ALPHA3_SHADING_GOURAUD));
149 
					      R300_ALPHA3_SHADING_GOURAUD));
 148 
	OUT_ACCEL_REG(R300_GA_OFFSET, 0);
150 
	OUT_ACCEL_REG(R300_GA_OFFSET, 0);
 149 
	FINISH_ACCEL();
151 
	FINISH_ACCEL();
 150 
 
152 
 
 151 
	BEGIN_ACCEL(5);
153 
	BEGIN_ACCEL(5);
 152 
	OUT_ACCEL_REG(R300_SU_TEX_WRAP, 0);
154 
	OUT_ACCEL_REG(R300_SU_TEX_WRAP, 0);
 153 
	OUT_ACCEL_REG(R300_SU_POLY_OFFSET_ENABLE, 0);
155 
	OUT_ACCEL_REG(R300_SU_POLY_OFFSET_ENABLE, 0);
 154 
	OUT_ACCEL_REG(R300_SU_CULL_MODE, R300_FACE_NEG);
156 
	OUT_ACCEL_REG(R300_SU_CULL_MODE, R300_FACE_NEG);
 155 
	OUT_ACCEL_REG(R300_SU_DEPTH_SCALE, 0x4b7fffff);
157 
	OUT_ACCEL_REG(R300_SU_DEPTH_SCALE, 0x4b7fffff);
 156 
	OUT_ACCEL_REG(R300_SU_DEPTH_OFFSET, 0);
158 
	OUT_ACCEL_REG(R300_SU_DEPTH_OFFSET, 0);
 157 
	FINISH_ACCEL();
159 
	FINISH_ACCEL();
 158 
 
160 
 
 159 
	/* setup the VAP */
161 
	/* setup the VAP */
 160 
        if (rhdPtr->has_tcl)
162 
        if (rhdPtr->has_tcl)
 161 
	    vap_cntl = ((5 << R300_PVS_NUM_SLOTS_SHIFT) |
163 
	    vap_cntl = ((5 << R300_PVS_NUM_SLOTS_SHIFT) |
 162 
			(5 << R300_PVS_NUM_CNTLRS_SHIFT) |
164 
			(5 << R300_PVS_NUM_CNTLRS_SHIFT) |
 163 
			(9 << R300_VF_MAX_VTX_NUM_SHIFT));
165 
			(9 << R300_VF_MAX_VTX_NUM_SHIFT));
 164 
	else
166 
	else
 165 
	    vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
167 
	    vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
 166 
			(5 << R300_PVS_NUM_CNTLRS_SHIFT) |
168 
			(5 << R300_PVS_NUM_CNTLRS_SHIFT) |
 167 
			(5 << R300_VF_MAX_VTX_NUM_SHIFT));
169 
			(5 << R300_VF_MAX_VTX_NUM_SHIFT));
 168 
 
170 
 
 169 
        if (rhdPtr->ChipSet == RHD_FAMILY_RV515)
171 
        if (rhdPtr->ChipSet == RHD_FAMILY_RV515)
 170 
	    vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT);
172 
	    vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT);
 171 
        else if ((rhdPtr->ChipSet == RHD_FAMILY_RV530) ||
173 
        else if ((rhdPtr->ChipSet == RHD_FAMILY_RV530) ||
 172 
                 (rhdPtr->ChipSet == RHD_FAMILY_RV560))
174 
                 (rhdPtr->ChipSet == RHD_FAMILY_RV560))
 173 
	    vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT);
175 
	    vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT);
 174 
        else if (rhdPtr->ChipSet == RHD_FAMILY_R420)
176 
        else if (rhdPtr->ChipSet == RHD_FAMILY_R420)
 175 
	    vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT);
177 
	    vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT);
 176 
        else if ((rhdPtr->ChipSet == RHD_FAMILY_R520) ||
178 
        else if ((rhdPtr->ChipSet == RHD_FAMILY_R520) ||
 177 
                 (rhdPtr->ChipSet == RHD_FAMILY_R580) ||
179 
                 (rhdPtr->ChipSet == RHD_FAMILY_R580) ||
 178 
                 (rhdPtr->ChipSet == RHD_FAMILY_RV570))
180 
                 (rhdPtr->ChipSet == RHD_FAMILY_RV570))
 179 
	    vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT);
181 
	    vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT);
 180 
	else
182 
	else
 181 
	    vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT);
183 
	    vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT);
 182 
 
184 
 
 183 
        if (rhdPtr->has_tcl)
185 
        if (rhdPtr->has_tcl)
 184 
	    BEGIN_ACCEL(15);
186 
	    BEGIN_ACCEL(15);
 185 
	else
187 
	else
 186 
	    BEGIN_ACCEL(9);
188 
	    BEGIN_ACCEL(9);
 187 
	OUT_ACCEL_REG(R300_VAP_VTX_STATE_CNTL, 0);
189 
	OUT_ACCEL_REG(R300_VAP_VTX_STATE_CNTL, 0);
 188 
	OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
190 
	OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
 189 
 
191 
 
 190 
        if (rhdPtr->has_tcl)
192 
        if (rhdPtr->has_tcl)
 191 
	    OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0);
193 
	    OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0);
 192 
	else
194 
	else
 193 
	    OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
195 
	    OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
 194 
	OUT_ACCEL_REG(R300_VAP_CNTL, vap_cntl);
196 
	OUT_ACCEL_REG(R300_VAP_CNTL, vap_cntl);
 195 
	OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
197 
	OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
 196 
	OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT);
198 
	OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT);
 197 
	OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0);
199 
	OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0);
 198 
 
200 
 
 199 
	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
201 
	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
 200 
		      ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
202 
		      ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
 201 
		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
203 
		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
 202 
		       (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
204 
		       (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
 203 
		       (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) |
205 
		       (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) |
 204 
		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
206 
		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
 205 
			<< R300_WRITE_ENA_0_SHIFT) |
207 
			<< R300_WRITE_ENA_0_SHIFT) |
 206 
		       (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
208 
		       (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
 207 
		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
209 
		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
 208 
		       (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
210 
		       (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
 209 
		       (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) |
211 
		       (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) |
 210 
		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
212 
		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
 211 
			<< R300_WRITE_ENA_1_SHIFT)));
213 
			<< R300_WRITE_ENA_1_SHIFT)));
 212 
	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
214 
	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
 213 
		      ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) |
215 
		      ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) |
 214 
		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) |
216 
		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) |
 215 
		       (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
217 
		       (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
 216 
		       (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) |
218 
		       (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) |
 217 
		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
219 
		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
 218 
			<< R300_WRITE_ENA_2_SHIFT)));
220 
			<< R300_WRITE_ENA_2_SHIFT)));
 219 
 
221 
 
 220 
        if (rhdPtr->has_tcl) {
222 
        if (rhdPtr->has_tcl) {
 221 
	    OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
223 
	    OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
 222 
	    OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
224 
	    OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
 223 
	    OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
225 
	    OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
 224 
	    OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
226 
	    OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
 225 
	    OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
227 
	    OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
 226 
	    OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
228 
	    OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
 227 
	}
229 
	}
 228 
	FINISH_ACCEL();
230 
	FINISH_ACCEL();
 229 
 
231 
 
 230 
	/* pre-load the vertex shaders */
232 
	/* pre-load the vertex shaders */
 231 
        if (rhdPtr->has_tcl) {
233 
        if (rhdPtr->has_tcl) {
 232 
	    /* exa mask shader program */
234 
	    /* exa mask shader program */
 233 
	    BEGIN_ACCEL(13);
235 
	    BEGIN_ACCEL(13);
 234 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
236 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
 235 
	    /* PVS inst 0 */
237 
	    /* PVS inst 0 */
 236 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
238 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 237 
			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
239 
			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
 238 
			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
240 
			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
 239 
			   R300_PVS_DST_OFFSET(0) |
241 
			   R300_PVS_DST_OFFSET(0) |
 240 
			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
242 
			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
 241 
			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
243 
			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
 242 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
244 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 243 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
245 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 244 
			   R300_PVS_SRC_OFFSET(0) |
246 
			   R300_PVS_SRC_OFFSET(0) |
 245 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
247 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
 246 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
248 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
 247 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
249 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
 248 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
250 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
 249 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
251 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 250 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
252 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 251 
			   R300_PVS_SRC_OFFSET(0) |
253 
			   R300_PVS_SRC_OFFSET(0) |
 252 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
254 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
 253 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
255 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
 254 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
256 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
 255 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
257 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
 256 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
258 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 257 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
259 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 258 
			   R300_PVS_SRC_OFFSET(0) |
260 
			   R300_PVS_SRC_OFFSET(0) |
 259 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
261 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
 260 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
262 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
 261 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
263 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
 262 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
264 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
 263 
 
265 
 
 264 
	    /* PVS inst 1 */
266 
	    /* PVS inst 1 */
 265 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
267 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 266 
			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
268 
			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
 267 
			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
269 
			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
 268 
			   R300_PVS_DST_OFFSET(1) |
270 
			   R300_PVS_DST_OFFSET(1) |
 269 
			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
271 
			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
 270 
			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
272 
			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
 271 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
273 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 272 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
274 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 273 
			   R300_PVS_SRC_OFFSET(6) |
275 
			   R300_PVS_SRC_OFFSET(6) |
 274 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
276 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
 275 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
277 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
 276 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
278 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
 277 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
279 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
 278 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
280 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 279 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
281 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 280 
			   R300_PVS_SRC_OFFSET(6) |
282 
			   R300_PVS_SRC_OFFSET(6) |
 281 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
283 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
 282 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
284 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
 283 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
285 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
 284 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
286 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
 285 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
287 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 286 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
288 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 287 
			   R300_PVS_SRC_OFFSET(6) |
289 
			   R300_PVS_SRC_OFFSET(6) |
 288 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
290 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
 289 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
291 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
 290 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
292 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
 291 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
293 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
 292 
 
294 
 
 293 
	    /* PVS inst 2 */
295 
	    /* PVS inst 2 */
 294 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
296 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 295 
			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
297 
			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
 296 
			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
298 
			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
 297 
			   R300_PVS_DST_OFFSET(2) |
299 
			   R300_PVS_DST_OFFSET(2) |
 298 
			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
300 
			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
 299 
			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
301 
			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
 300 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
302 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 301 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
303 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 302 
			   R300_PVS_SRC_OFFSET(7) |
304 
			   R300_PVS_SRC_OFFSET(7) |
 303 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
305 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
 304 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
306 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
 305 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
307 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
 306 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
308 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
 307 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
309 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 308 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
310 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 309 
			   R300_PVS_SRC_OFFSET(7) |
311 
			   R300_PVS_SRC_OFFSET(7) |
 310 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
312 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
 311 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
313 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
 312 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
314 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
 313 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
315 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
 314 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
316 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 315 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
317 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 316 
			   R300_PVS_SRC_OFFSET(7) |
318 
			   R300_PVS_SRC_OFFSET(7) |
 317 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
319 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
 318 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
320 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
 319 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
321 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
 320 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
322 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
 321 
	    FINISH_ACCEL();
323 
	    FINISH_ACCEL();
 322 
 
324 
 
 323 
	    BEGIN_ACCEL(9);
325 
	    BEGIN_ACCEL(9);
 324 
	    /* exa no mask instruction */
326 
	    /* exa no mask instruction */
 325 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 3);
327 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 3);
 326 
	    /* PVS inst 0 */
328 
	    /* PVS inst 0 */
 327 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
329 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 328 
			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
330 
			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
 329 
			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
331 
			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
 330 
			   R300_PVS_DST_OFFSET(0) |
332 
			   R300_PVS_DST_OFFSET(0) |
 331 
			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
333 
			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
 332 
			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
334 
			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
 333 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
335 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 334 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
336 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 335 
			   R300_PVS_SRC_OFFSET(0) |
337 
			   R300_PVS_SRC_OFFSET(0) |
 336 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
338 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
 337 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
339 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
 338 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
340 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
 339 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
341 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
 340 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
342 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 341 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
343 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 342 
			   R300_PVS_SRC_OFFSET(0) |
344 
			   R300_PVS_SRC_OFFSET(0) |
 343 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
345 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
 344 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
346 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
 345 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
347 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
 346 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
348 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
 347 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
349 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 348 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
350 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 349 
			   R300_PVS_SRC_OFFSET(0) |
351 
			   R300_PVS_SRC_OFFSET(0) |
 350 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
352 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
 351 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
353 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
 352 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
354 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
 353 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
355 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
 354 
 
356 
 
 355 
	    /* PVS inst 1 */
357 
	    /* PVS inst 1 */
 356 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
358 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 357 
			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
359 
			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
 358 
			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
360 
			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
 359 
			   R300_PVS_DST_OFFSET(1) |
361 
			   R300_PVS_DST_OFFSET(1) |
 360 
			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
362 
			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
 361 
			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
363 
			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
 362 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
364 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 363 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
365 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 364 
			   R300_PVS_SRC_OFFSET(6) |
366 
			   R300_PVS_SRC_OFFSET(6) |
 365 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
367 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
 366 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
368 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
 367 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
369 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
 368 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
370 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
 369 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
371 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 370 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
372 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 371 
			   R300_PVS_SRC_OFFSET(6) |
373 
			   R300_PVS_SRC_OFFSET(6) |
 372 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
374 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
 373 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
375 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
 374 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
376 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
 375 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
377 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
 376 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
378 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 377 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
379 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 378 
			   R300_PVS_SRC_OFFSET(6) |
380 
			   R300_PVS_SRC_OFFSET(6) |
 379 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
381 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
 380 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
382 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
 381 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
383 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
 382 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
384 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
 383 
	    FINISH_ACCEL();
385 
	    FINISH_ACCEL();
 384 
 
386 
 
 385 
	    /* Xv shader program */
387 
	    /* Xv shader program */
 386 
	    BEGIN_ACCEL(9);
388 
	    BEGIN_ACCEL(9);
 387 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 5);
389 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 5);
 388 
 
390 
 
 389 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
391 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 390 
			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
392 
			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
 391 
			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
393 
			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
 392 
			   R300_PVS_DST_OFFSET(0) |
394 
			   R300_PVS_DST_OFFSET(0) |
 393 
			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
395 
			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
 394 
			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
396 
			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
 395 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
397 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 396 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
398 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 397 
			   R300_PVS_SRC_OFFSET(0) |
399 
			   R300_PVS_SRC_OFFSET(0) |
 398 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
400 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
 399 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
401 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
 400 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
402 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
 401 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
403 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
 402 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
404 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 403 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
405 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 404 
			   R300_PVS_SRC_OFFSET(0) |
406 
			   R300_PVS_SRC_OFFSET(0) |
 405 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
407 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
 406 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
408 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
 407 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
409 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
 408 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
410 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
 409 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
411 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 410 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
412 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 411 
			   R300_PVS_SRC_OFFSET(0) |
413 
			   R300_PVS_SRC_OFFSET(0) |
 412 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
414 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
 413 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
415 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
 414 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
416 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
 415 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
417 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
 416 
 
418 
 
 417 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
419 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 418 
			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
420 
			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
 419 
			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
421 
			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
 420 
			   R300_PVS_DST_OFFSET(1) |
422 
			   R300_PVS_DST_OFFSET(1) |
 421 
			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
423 
			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
 422 
			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
424 
			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
 423 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
425 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 424 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
426 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 425 
			   R300_PVS_SRC_OFFSET(6) |
427 
			   R300_PVS_SRC_OFFSET(6) |
 426 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
428 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
 427 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
429 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
 428 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
430 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
 429 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
431 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
 430 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
432 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 431 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
433 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 432 
			   R300_PVS_SRC_OFFSET(6) |
434 
			   R300_PVS_SRC_OFFSET(6) |
 433 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
435 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
 434 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
436 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
 435 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
437 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
 436 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
438 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
 437 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
439 
	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
 438 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
440 
			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
 439 
			   R300_PVS_SRC_OFFSET(6) |
441 
			   R300_PVS_SRC_OFFSET(6) |
 440 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
442 
			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
 441 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
443 
			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
 442 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
444 
			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
 443 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
445 
			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
 444 
	    FINISH_ACCEL();
446 
	    FINISH_ACCEL();
 445 
	}
447 
	}
 446 
 
448 
 
 447 
	/* pre-load the RS instructions */
449 
	/* pre-load the RS instructions */
 448 
	BEGIN_ACCEL(4);
450 
	BEGIN_ACCEL(4);
 449 
	if (IS_R300_3D) {
451 
	if (IS_R300_3D) {
 450 
	    /* rasterizer source table
452 
	    /* rasterizer source table
 451 
	     * R300_RS_TEX_PTR is the offset into the input RS stream
453 
	     * R300_RS_TEX_PTR is the offset into the input RS stream
 452 
	     * 0,1 are tex0
454 
	     * 0,1 are tex0
 453 
	     * 2,3 are tex1
455 
	     * 2,3 are tex1
 454 
	     */
456 
	     */
 455 
	    OUT_ACCEL_REG(R300_RS_IP_0,
457 
	    OUT_ACCEL_REG(R300_RS_IP_0,
 456 
			  (R300_RS_TEX_PTR(0) |
458 
			  (R300_RS_TEX_PTR(0) |
 457 
			   R300_RS_SEL_S(R300_RS_SEL_C0) |
459 
			   R300_RS_SEL_S(R300_RS_SEL_C0) |
 458 
			   R300_RS_SEL_T(R300_RS_SEL_C1) |
460 
			   R300_RS_SEL_T(R300_RS_SEL_C1) |
 459 
			   R300_RS_SEL_R(R300_RS_SEL_K0) |
461 
			   R300_RS_SEL_R(R300_RS_SEL_K0) |
 460 
			   R300_RS_SEL_Q(R300_RS_SEL_K1)));
462 
			   R300_RS_SEL_Q(R300_RS_SEL_K1)));
 461 
	    OUT_ACCEL_REG(R300_RS_IP_1,
463 
	    OUT_ACCEL_REG(R300_RS_IP_1,
 462 
			  (R300_RS_TEX_PTR(2) |
464 
			  (R300_RS_TEX_PTR(2) |
 463 
			   R300_RS_SEL_S(R300_RS_SEL_C0) |
465 
			   R300_RS_SEL_S(R300_RS_SEL_C0) |
 464 
			   R300_RS_SEL_T(R300_RS_SEL_C1) |
466 
			   R300_RS_SEL_T(R300_RS_SEL_C1) |
 465 
			   R300_RS_SEL_R(R300_RS_SEL_K0) |
467 
			   R300_RS_SEL_R(R300_RS_SEL_K0) |
 466 
			   R300_RS_SEL_Q(R300_RS_SEL_K1)));
468 
			   R300_RS_SEL_Q(R300_RS_SEL_K1)));
 467 
	    /* src tex */
469 
	    /* src tex */
 468 
	    /* R300_INST_TEX_ID - select the RS source table entry
470 
	    /* R300_INST_TEX_ID - select the RS source table entry
 469 
	     * R300_INST_TEX_ADDR - the FS temp register for the texture data
471 
	     * R300_INST_TEX_ADDR - the FS temp register for the texture data
 470 
	     */
472 
	     */
 471 
	    OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) |
473 
	    OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) |
 472 
					   R300_RS_INST_TEX_CN_WRITE |
474 
					   R300_RS_INST_TEX_CN_WRITE |
 473 
					   R300_INST_TEX_ADDR(0)));
475 
					   R300_INST_TEX_ADDR(0)));
 474 
	    /* mask tex */
476 
	    /* mask tex */
 475 
	    OUT_ACCEL_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) |
477 
	    OUT_ACCEL_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) |
 476 
					   R300_RS_INST_TEX_CN_WRITE |
478 
					   R300_RS_INST_TEX_CN_WRITE |
 477 
					   R300_INST_TEX_ADDR(1)));
479 
					   R300_INST_TEX_ADDR(1)));
 478 
 
480 
 
 479 
	} else {
481 
	} else {
 480 
	    /* rasterizer source table
482 
	    /* rasterizer source table
 481 
	     * R300_RS_TEX_PTR is the offset into the input RS stream
483 
	     * R300_RS_TEX_PTR is the offset into the input RS stream
 482 
	     * 0,1 are tex0
484 
	     * 0,1 are tex0
 483 
	     * 2,3 are tex1
485 
	     * 2,3 are tex1
 484 
	     */
486 
	     */
 485 
	    OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
487 
	    OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
 486 
					 (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
488 
					 (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
 487 
					 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
489 
					 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
 488 
					 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
490 
					 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
 489 
 
491 
 
 490 
	    OUT_ACCEL_REG(R500_RS_IP_1, ((2 << R500_RS_IP_TEX_PTR_S_SHIFT) |
492 
	    OUT_ACCEL_REG(R500_RS_IP_1, ((2 << R500_RS_IP_TEX_PTR_S_SHIFT) |
 491 
					 (3 << R500_RS_IP_TEX_PTR_T_SHIFT) |
493 
					 (3 << R500_RS_IP_TEX_PTR_T_SHIFT) |
 492 
					 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
494 
					 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
 493 
					 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
495 
					 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
 494 
	    /* src tex */
496 
	    /* src tex */
 495 
	    /* R500_RS_INST_TEX_ID_SHIFT - select the RS source table entry
497 
	    /* R500_RS_INST_TEX_ID_SHIFT - select the RS source table entry
 496 
	     * R500_RS_INST_TEX_ADDR_SHIFT - the FS temp register for the texture data
498 
	     * R500_RS_INST_TEX_ADDR_SHIFT - the FS temp register for the texture data
 497 
	     */
499 
	     */
 498 
	    OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) |
500 
	    OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) |
 499 
					   R500_RS_INST_TEX_CN_WRITE |
501 
					   R500_RS_INST_TEX_CN_WRITE |
 500 
					   (0 << R500_RS_INST_TEX_ADDR_SHIFT)));
502 
					   (0 << R500_RS_INST_TEX_ADDR_SHIFT)));
 501 
	    /* mask tex */
503 
	    /* mask tex */
 502 
	    OUT_ACCEL_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) |
504 
	    OUT_ACCEL_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) |
 503 
					   R500_RS_INST_TEX_CN_WRITE |
505 
					   R500_RS_INST_TEX_CN_WRITE |
 504 
					   (1 << R500_RS_INST_TEX_ADDR_SHIFT)));
506 
					   (1 << R500_RS_INST_TEX_ADDR_SHIFT)));
 505 
	}
507 
	}
 506 
	FINISH_ACCEL();
508 
	FINISH_ACCEL();
 507 
 
509 
 
 508 
	/* pre-load FS tex instructions */
510 
	/* pre-load FS tex instructions */
 509 
	if (IS_R300_3D) {
511 
	if (IS_R300_3D) {
 510 
	    BEGIN_ACCEL(2);
512 
	    BEGIN_ACCEL(2);
 511 
	    /* tex inst for src texture */
513 
	    /* tex inst for src texture */
 512 
	    OUT_ACCEL_REG(R300_US_TEX_INST_0,
514 
	    OUT_ACCEL_REG(R300_US_TEX_INST_0,
 513 
			  (R300_TEX_SRC_ADDR(0) |
515 
			  (R300_TEX_SRC_ADDR(0) |
 514 
			   R300_TEX_DST_ADDR(0) |
516 
			   R300_TEX_DST_ADDR(0) |
 515 
			   R300_TEX_ID(0) |
517 
			   R300_TEX_ID(0) |
 516 
			   R300_TEX_INST(R300_TEX_INST_LD)));
518 
			   R300_TEX_INST(R300_TEX_INST_LD)));
 517 
 
519 
 
 518 
	    /* tex inst for mask texture */
520 
	    /* tex inst for mask texture */
 519 
	    OUT_ACCEL_REG(R300_US_TEX_INST_1,
521 
	    OUT_ACCEL_REG(R300_US_TEX_INST_1,
 520 
			  (R300_TEX_SRC_ADDR(1) |
522 
			  (R300_TEX_SRC_ADDR(1) |
 521 
			   R300_TEX_DST_ADDR(1) |
523 
			   R300_TEX_DST_ADDR(1) |
 522 
			   R300_TEX_ID(1) |
524 
			   R300_TEX_ID(1) |
 523 
			   R300_TEX_INST(R300_TEX_INST_LD)));
525 
			   R300_TEX_INST(R300_TEX_INST_LD)));
 524 
	    FINISH_ACCEL();
526 
	    FINISH_ACCEL();
 525 
	}
527 
	}
 526 
 
528 
 
 527 
	if (IS_R300_3D) {
529 
	if (IS_R300_3D) {
 528 
	    BEGIN_ACCEL(9);
530 
	    BEGIN_ACCEL(9);
 529 
	    OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
531 
	    OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
 530 
	    OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */
532 
	    OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */
 531 
	    OUT_ACCEL_REG(R300_US_CODE_ADDR_0,
533 
	    OUT_ACCEL_REG(R300_US_CODE_ADDR_0,
 532 
			  (R300_ALU_START(0) |
534 
			  (R300_ALU_START(0) |
 533 
			   R300_ALU_SIZE(0) |
535 
			   R300_ALU_SIZE(0) |
 534 
			   R300_TEX_START(0) |
536 
			   R300_TEX_START(0) |
 535 
			   R300_TEX_SIZE(0)));
537 
			   R300_TEX_SIZE(0)));
 536 
	    OUT_ACCEL_REG(R300_US_CODE_ADDR_1,
538 
	    OUT_ACCEL_REG(R300_US_CODE_ADDR_1,
 537 
			  (R300_ALU_START(0) |
539 
			  (R300_ALU_START(0) |
 538 
			   R300_ALU_SIZE(0) |
540 
			   R300_ALU_SIZE(0) |
 539 
			   R300_TEX_START(0) |
541 
			   R300_TEX_START(0) |
 540 
			   R300_TEX_SIZE(0)));
542 
			   R300_TEX_SIZE(0)));
 541 
	    OUT_ACCEL_REG(R300_US_CODE_ADDR_2,
543 
	    OUT_ACCEL_REG(R300_US_CODE_ADDR_2,
 542 
			  (R300_ALU_START(0) |
544 
			  (R300_ALU_START(0) |
 543 
			   R300_ALU_SIZE(0) |
545 
			   R300_ALU_SIZE(0) |
 544 
			   R300_TEX_START(0) |
546 
			   R300_TEX_START(0) |
 545 
			   R300_TEX_SIZE(0)));
547 
			   R300_TEX_SIZE(0)));
 546 
	} else {
548 
	} else {
 547 
	    BEGIN_ACCEL(7);
549 
	    BEGIN_ACCEL(7);
 548 
	    OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
550 
	    OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
 549 
	    OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */
551 
	    OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */
 550 
	    OUT_ACCEL_REG(R500_US_FC_CTRL, 0);
552 
	    OUT_ACCEL_REG(R500_US_FC_CTRL, 0);
 551 
	}
553 
	}
 552 
	OUT_ACCEL_REG(R300_US_W_FMT, 0);
554 
	OUT_ACCEL_REG(R300_US_W_FMT, 0);
 553 
	OUT_ACCEL_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED |
555 
	OUT_ACCEL_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED |
 554 
					  R300_OUT_FMT_C0_SEL_BLUE |
556 
					  R300_OUT_FMT_C0_SEL_BLUE |
 555 
					  R300_OUT_FMT_C1_SEL_GREEN |
557 
					  R300_OUT_FMT_C1_SEL_GREEN |
 556 
					  R300_OUT_FMT_C2_SEL_RED |
558 
					  R300_OUT_FMT_C2_SEL_RED |
 557 
					  R300_OUT_FMT_C3_SEL_ALPHA));
559 
					  R300_OUT_FMT_C3_SEL_ALPHA));
 558 
	OUT_ACCEL_REG(R300_US_OUT_FMT_2, (R300_OUT_FMT_UNUSED |
560 
	OUT_ACCEL_REG(R300_US_OUT_FMT_2, (R300_OUT_FMT_UNUSED |
 559 
					  R300_OUT_FMT_C0_SEL_BLUE |
561 
					  R300_OUT_FMT_C0_SEL_BLUE |
 560 
					  R300_OUT_FMT_C1_SEL_GREEN |
562 
					  R300_OUT_FMT_C1_SEL_GREEN |
 561 
					  R300_OUT_FMT_C2_SEL_RED |
563 
					  R300_OUT_FMT_C2_SEL_RED |
 562 
					  R300_OUT_FMT_C3_SEL_ALPHA));
564 
					  R300_OUT_FMT_C3_SEL_ALPHA));
 563 
	OUT_ACCEL_REG(R300_US_OUT_FMT_3, (R300_OUT_FMT_UNUSED |
565 
	OUT_ACCEL_REG(R300_US_OUT_FMT_3, (R300_OUT_FMT_UNUSED |
 564 
					  R300_OUT_FMT_C0_SEL_BLUE |
566 
					  R300_OUT_FMT_C0_SEL_BLUE |
 565 
					  R300_OUT_FMT_C1_SEL_GREEN |
567 
					  R300_OUT_FMT_C1_SEL_GREEN |
 566 
					  R300_OUT_FMT_C2_SEL_RED |
568 
					  R300_OUT_FMT_C2_SEL_RED |
 567 
					  R300_OUT_FMT_C3_SEL_ALPHA));
569 
					  R300_OUT_FMT_C3_SEL_ALPHA));
 568 
	FINISH_ACCEL();
570 
	FINISH_ACCEL();
 569 
 
571 
 
 570 
 
572 
 
 571 
	BEGIN_ACCEL(3);
573 
	BEGIN_ACCEL(3);
 572 
	OUT_ACCEL_REG(R300_FG_DEPTH_SRC, 0);
574 
	OUT_ACCEL_REG(R300_FG_DEPTH_SRC, 0);
 573 
	OUT_ACCEL_REG(R300_FG_FOG_BLEND, 0);
575 
	OUT_ACCEL_REG(R300_FG_FOG_BLEND, 0);
 574 
	OUT_ACCEL_REG(R300_FG_ALPHA_FUNC, 0);
576 
	OUT_ACCEL_REG(R300_FG_ALPHA_FUNC, 0);
 575 
	FINISH_ACCEL();
577 
	FINISH_ACCEL();
 576 
 
578 
 
 577 
	BEGIN_ACCEL(13);
579 
	BEGIN_ACCEL(13);
 578 
	OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0);
580 
	OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0);
 579 
	OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0);
581 
	OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0);
 580 
	OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
582 
	OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
 581 
	OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0);
583 
	OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0);
 582 
	OUT_ACCEL_REG(R300_RB3D_ZCNTL, 0);
584 
	OUT_ACCEL_REG(R300_RB3D_ZCNTL, 0);
 583 
	OUT_ACCEL_REG(R300_RB3D_ZTOP, 0);
585 
	OUT_ACCEL_REG(R300_RB3D_ZTOP, 0);
 584 
	OUT_ACCEL_REG(R300_RB3D_ROPCNTL, 0);
586 
	OUT_ACCEL_REG(R300_RB3D_ROPCNTL, 0);
 585 
 
587 
 
 586 
	OUT_ACCEL_REG(R300_RB3D_AARESOLVE_CTL, 0);
588 
	OUT_ACCEL_REG(R300_RB3D_AARESOLVE_CTL, 0);
 587 
	OUT_ACCEL_REG(R300_RB3D_COLOR_CHANNEL_MASK, (R300_BLUE_MASK_EN |
589 
	OUT_ACCEL_REG(R300_RB3D_COLOR_CHANNEL_MASK, (R300_BLUE_MASK_EN |
 588 
						     R300_GREEN_MASK_EN |
590 
						     R300_GREEN_MASK_EN |
 589 
						     R300_RED_MASK_EN |
591 
						     R300_RED_MASK_EN |
 590 
						     R300_ALPHA_MASK_EN));
592 
						     R300_ALPHA_MASK_EN));
 591 
	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
593 
	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
 592 
	OUT_ACCEL_REG(R300_RB3D_CCTL, 0);
594 
	OUT_ACCEL_REG(R300_RB3D_CCTL, 0);
 593 
	OUT_ACCEL_REG(R300_RB3D_DITHER_CTL, 0);
595 
	OUT_ACCEL_REG(R300_RB3D_DITHER_CTL, 0);
 594 
	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
596 
	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
 595 
	FINISH_ACCEL();
597 
	FINISH_ACCEL();
 596 
 
598 
 
 597 
	BEGIN_ACCEL(7);
599 
	BEGIN_ACCEL(7);
 598 
	OUT_ACCEL_REG(R300_SC_EDGERULE, 0xA5294A5);
600 
	OUT_ACCEL_REG(R300_SC_EDGERULE, 0xA5294A5);
 599 
	OUT_ACCEL_REG(R300_SC_SCISSOR0, ((0 << R300_SCISSOR_X_SHIFT) |
601 
	OUT_ACCEL_REG(R300_SC_SCISSOR0, ((0 << R300_SCISSOR_X_SHIFT) |
 600 
					 (0 << R300_SCISSOR_Y_SHIFT)));
602 
					 (0 << R300_SCISSOR_Y_SHIFT)));
 601 
	OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) |
603 
	OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) |
 602 
					 (8191 << R300_SCISSOR_Y_SHIFT)));
604 
					 (8191 << R300_SCISSOR_Y_SHIFT)));
 603 
 
605 
 
 604 
	if (IS_R300_3D) {
606 
	if (IS_R300_3D) {
 605 
	    /* clip has offset 1440 */
607 
	    /* clip has offset 1440 */
 606 
	    OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1088 << R300_CLIP_X_SHIFT) |
608 
	    OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1088 << R300_CLIP_X_SHIFT) |
 607 
					     (1088 << R300_CLIP_Y_SHIFT)));
609 
					     (1088 << R300_CLIP_Y_SHIFT)));
 608 
	    OUT_ACCEL_REG(R300_SC_CLIP_0_B, (((1080 + 2920) << R300_CLIP_X_SHIFT) |
610 
	    OUT_ACCEL_REG(R300_SC_CLIP_0_B, (((1080 + 2920) << R300_CLIP_X_SHIFT) |
 609 
					     ((1080 + 2920) << R300_CLIP_Y_SHIFT)));
611 
					     ((1080 + 2920) << R300_CLIP_Y_SHIFT)));
 610 
	} else {
612 
	} else {
 611 
	    OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) |
613 
	    OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) |
 612 
					     (0 << R300_CLIP_Y_SHIFT)));
614 
					     (0 << R300_CLIP_Y_SHIFT)));
 613 
	    OUT_ACCEL_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) |
615 
	    OUT_ACCEL_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) |
 614 
					     (4080 << R300_CLIP_Y_SHIFT)));
616 
					     (4080 << R300_CLIP_Y_SHIFT)));
 615 
	}
617 
	}
 616 
	OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA);
618 
	OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA);
 617 
	OUT_ACCEL_REG(R300_SC_SCREENDOOR, 0xffffff);
619 
	OUT_ACCEL_REG(R300_SC_SCREENDOOR, 0xffffff);
 618 
	FINISH_ACCEL();
620 
	FINISH_ACCEL();
 619 
    } else if ((rhdPtr->ChipSet == RHD_FAMILY_RV250) ||
621 
    } else if ((rhdPtr->ChipSet == RHD_FAMILY_RV250) ||
 620 
               (rhdPtr->ChipSet == RHD_FAMILY_RV280) ||
622 
               (rhdPtr->ChipSet == RHD_FAMILY_RV280) ||
 621 
               (rhdPtr->ChipSet == RHD_FAMILY_RS300) ||
623 
               (rhdPtr->ChipSet == RHD_FAMILY_RS300) ||
 622 
               (rhdPtr->ChipSet == RHD_FAMILY_R200)) {
624 
               (rhdPtr->ChipSet == RHD_FAMILY_R200)) {
 623 
 
625 
 
 624 
	BEGIN_ACCEL(7);
626 
	BEGIN_ACCEL(7);
 625 
        if (rhdPtr->ChipSet == RHD_FAMILY_RS300) {
627 
        if (rhdPtr->ChipSet == RHD_FAMILY_RS300) {
 626 
	    OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS);
628 
	    OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS);
 627 
	} else {
629 
	} else {
 628 
	    OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0);
630 
	    OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0);
 629 
	}
631 
	}
 630 
	OUT_ACCEL_REG(R200_PP_CNTL_X, 0);
632 
	OUT_ACCEL_REG(R200_PP_CNTL_X, 0);
 631 
	OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0);
633 
	OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0);
 632 
	OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0);
634 
	OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0);
 633 
	OUT_ACCEL_REG(R200_RE_CNTL, 0x0);
635 
	OUT_ACCEL_REG(R200_RE_CNTL, 0x0);
 634 
	OUT_ACCEL_REG(R200_SE_VTE_CNTL, 0);
636 
	OUT_ACCEL_REG(R200_SE_VTE_CNTL, 0);
 635 
	OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE |
637 
	OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE |
 636 
	    R200_VAP_VF_MAX_VTX_NUM);
638 
	    R200_VAP_VF_MAX_VTX_NUM);
 637 
	FINISH_ACCEL();
639 
	FINISH_ACCEL();
 638 
 
640 
 
 639 
	BEGIN_ACCEL(5);
641 
	BEGIN_ACCEL(5);
 640 
	OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0);
642 
	OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0);
 641 
	OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff);
643 
	OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff);
 642 
	OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0);
644 
	OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0);
 643 
	OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff);
645 
	OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff);
 644 
	OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
646 
	OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
 645 
				       RADEON_BFACE_SOLID |
647 
				       RADEON_BFACE_SOLID |
 646 
				       RADEON_FFACE_SOLID |
648 
				       RADEON_FFACE_SOLID |
 647 
				       RADEON_VTX_PIX_CENTER_OGL |
649 
				       RADEON_VTX_PIX_CENTER_OGL |
 648 
				       RADEON_ROUND_MODE_ROUND |
650 
				       RADEON_ROUND_MODE_ROUND |
 649 
				       RADEON_ROUND_PREC_4TH_PIX));
651 
				       RADEON_ROUND_PREC_4TH_PIX));
 650 
	FINISH_ACCEL();
652 
	FINISH_ACCEL();
 651 
    } else {
653 
    } else {
 652 
	BEGIN_ACCEL(2);
654 
	BEGIN_ACCEL(2);
 653 
        if ((rhdPtr->ChipSet == RHD_FAMILY_RADEON) ||
655 
        if ((rhdPtr->ChipSet == RHD_FAMILY_RADEON) ||
 654 
            (rhdPtr->ChipSet == RHD_FAMILY_RV200))
656 
            (rhdPtr->ChipSet == RHD_FAMILY_RV200))
 655 
	    OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, 0);
657 
	    OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, 0);
 656 
	else
658 
	else
 657 
	    OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS);
659 
	    OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS);
 658 
	OUT_ACCEL_REG(RADEON_SE_COORD_FMT,
660 
	OUT_ACCEL_REG(RADEON_SE_COORD_FMT,
 659 
	    RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
661 
	    RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 660 
	    RADEON_VTX_ST0_NONPARAMETRIC |
662 
	    RADEON_VTX_ST0_NONPARAMETRIC |
 661 
	    RADEON_VTX_ST1_NONPARAMETRIC |
663 
	    RADEON_VTX_ST1_NONPARAMETRIC |
 662 
	    RADEON_TEX1_W_ROUTING_USE_W0);
664 
	    RADEON_TEX1_W_ROUTING_USE_W0);
 663 
	FINISH_ACCEL();
665 
	FINISH_ACCEL();
 664 
 
666 
 
 665 
	BEGIN_ACCEL(5);
667 
	BEGIN_ACCEL(5);
 666 
	OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0);
668 
	OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0);
 667 
	OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff);
669 
	OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff);
 668 
	OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0);
670 
	OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0);
 669 
	OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff);
671 
	OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff);
 670 
	OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
672 
	OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
 671 
				       RADEON_BFACE_SOLID |
673 
				       RADEON_BFACE_SOLID |
 672 
				       RADEON_FFACE_SOLID |
674 
				       RADEON_FFACE_SOLID |
 673 
				       RADEON_VTX_PIX_CENTER_OGL |
675 
				       RADEON_VTX_PIX_CENTER_OGL |
 674 
				       RADEON_ROUND_MODE_ROUND |
676 
				       RADEON_ROUND_MODE_ROUND |
 675 
				       RADEON_ROUND_PREC_4TH_PIX));
677 
				       RADEON_ROUND_PREC_4TH_PIX));
 676 
	FINISH_ACCEL();
678 
	FINISH_ACCEL();
 677 
    }
679 
    }
 678 
 
680 
 
 679 
}
681 
}
 680 
 
682 
 
 681 
static Bool R300TextureSetup(int w, int h, int unit)
683 
static Bool R300TextureSetup(int w, int h, int unit)
 682 
{
684 
{
 683 
    //RINFO_FROM_SCREEN(pPix->drawable.pScreen);
685 
    //RINFO_FROM_SCREEN(pPix->drawable.pScreen);
 684 
    u32_t txfilter, txformat0, txformat1, txoffset, txpitch;
686 
    u32_t txfilter, txformat0, txformat1, txoffset, txpitch;
 685 
 //   int w = pPict->pDrawable->width;
687 
 //   int w = pPict->pDrawable->width;
 686 
 //   int h = pPict->pDrawable->height;
688 
 //   int h = pPict->pDrawable->height;
 687 
    int i, pixel_shift;
689 
    int i, pixel_shift;
 688 
 
690 
 
 689 
    //ACCEL_PREAMBLE();
691 
    //ACCEL_PREAMBLE();
 690 
 
692 
 
 691 
    //TRACE;
693 
    //TRACE;
 692 
 
694 
 
 693 
    //txpitch = exaGetPixmapPitch(pPix);
695 
    //txpitch = exaGetPixmapPitch(pPix);
 694 
    txpitch = rhd.displayWidth * 4;
696 
    txpitch = rhd.displayWidth * 4;
 695 
 
697 
 
 696 
   // txoffset = exaGetPixmapOffset(pPix) + info->fbLocation + pScrn->fbOffset;
698 
   // txoffset = exaGetPixmapOffset(pPix) + info->fbLocation + pScrn->fbOffset;
 697 
    txoffset = rhd.FbIntAddress + rhd.FbScanoutStart;
699 
    txoffset = rhd.FbIntAddress + rhd.FbScanoutStart;
 698 
 
700 
 
 699 
    if ((txoffset & 0x1f) != 0)
701 
    if ((txoffset & 0x1f) != 0)
 700 
        dbgprintf("Bad texture offset 0x%x\n", (int)txoffset);
702 
        dbgprintf("Bad texture offset 0x%x\n", (int)txoffset);
 701 
    if ((txpitch & 0x1f) != 0)
703 
    if ((txpitch & 0x1f) != 0)
 702 
        dbgprintf("Bad texture pitch 0x%x\n", (int)txpitch);
704 
        dbgprintf("Bad texture pitch 0x%x\n", (int)txpitch);
 703 
 
705 
 
 704 
    /* TXPITCH = pixels (texels) per line - 1 */
706 
    /* TXPITCH = pixels (texels) per line - 1 */
 705 
    pixel_shift = 32 >> 4;
707 
    pixel_shift = 32 >> 4;
 706 
    txpitch >>= pixel_shift;
708 
    txpitch >>= pixel_shift;
 707 
    txpitch -= 1;
709 
    txpitch -= 1;
 708 
 
710 
 
 709 
  //  if (RADEONPixmapIsColortiled(pPix))
711 
  //  if (RADEONPixmapIsColortiled(pPix))
 710 
  //      txoffset |= R300_MACRO_TILE;
712 
  //      txoffset |= R300_MACRO_TILE;
 711 
 
713 
 
 712 
 //   for (i = 0; i < sizeof(R300TexFormats) / sizeof(R300TexFormats[0]); i++)
714 
 //   for (i = 0; i < sizeof(R300TexFormats) / sizeof(R300TexFormats[0]); i++)
 713 
 //   {
715 
 //   {
 714 
 //       if (R300TexFormats[i].fmt == pPict->format)
716 
 //       if (R300TexFormats[i].fmt == pPict->format)
 715 
 //           break;
717 
 //           break;
 716 
 //   }
718 
 //   }
 717 
 
719 
 
 718 
    //txformat1 = R300TexFormats[i].card_fmt;
720 
    //txformat1 = R300TexFormats[i].card_fmt;
 719 
    txformat1 = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8);
721 
    txformat1 = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8);
 720 
 
722 
 
 721 
    txformat0 = ((((w - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) |
723 
    txformat0 = ((((w - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) |
 722 
		 (((h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT));
724 
		 (((h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT));
 723 
 
725 
 
 724 
    if (IS_R500_3D && ((w - 1) & 0x800))
726 
    if (IS_R500_3D && ((w - 1) & 0x800))
 725 
	txpitch |= R500_TXWIDTH_11;
727 
	txpitch |= R500_TXWIDTH_11;
 726 
 
728 
 
 727 
    if (IS_R500_3D && ((h - 1) & 0x800))
729 
    if (IS_R500_3D && ((h - 1) & 0x800))
 728 
	txpitch |= R500_TXHEIGHT_11;
730 
	txpitch |= R500_TXHEIGHT_11;
 729 
 
731 
 
 730 
    /* Use TXPITCH instead of TXWIDTH for address computations: we could
732 
    /* Use TXPITCH instead of TXWIDTH for address computations: we could
 731 
     * omit this if there is no padding, but there is no apparent advantage
733 
     * omit this if there is no padding, but there is no apparent advantage
 732 
     * in doing so.
734 
     * in doing so.
 733 
     */
735 
     */
 734 
    txformat0 |= R300_TXPITCH_EN;
736 
    txformat0 |= R300_TXPITCH_EN;
 735 
 
737 
 
 736 
  //  info->texW[unit] = w;
738 
  //  info->texW[unit] = w;
 737 
  //  info->texH[unit] = h;
739 
  //  info->texH[unit] = h;
 738 
 
740 
 
 739 
  //  if (pPict->repeat && !(unit == 0 && need_src_tile_x))
741 
  //  if (pPict->repeat && !(unit == 0 && need_src_tile_x))
 740 
  //    txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_WRAP);
742 
  //    txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_WRAP);
 741 
  //  else
743 
  //  else
 742 
      txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_GL);
744 
      txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_GL);
 743 
 
745 
 
 744 
  //  if (pPict->repeat && !(unit == 0 && need_src_tile_y))
746 
  //  if (pPict->repeat && !(unit == 0 && need_src_tile_y))
 745 
  //    txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_WRAP);
747 
  //    txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_WRAP);
 746 
  //  else
748 
  //  else
 747 
      txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_GL);
749 
      txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_GL);
 748 
 
750 
 
 749 
    txfilter |= (unit << R300_TX_ID_SHIFT);
751 
    txfilter |= (unit << R300_TX_ID_SHIFT);
 750 
 
752 
 
 751 
//    switch (pPict->filter) {
753 
//    switch (pPict->filter) {
 752 
//    case PictFilterNearest:
754 
//    case PictFilterNearest:
 753 
	txfilter |= (R300_TX_MAG_FILTER_NEAREST | R300_TX_MIN_FILTER_NEAREST);
755 
	txfilter |= (R300_TX_MAG_FILTER_NEAREST | R300_TX_MIN_FILTER_NEAREST);
 754 
//        break;
756 
//        break;
 755 
//    case PictFilterBilinear:
757 
//    case PictFilterBilinear:
 756 
//        txfilter |= (R300_TX_MAG_FILTER_LINEAR | R300_TX_MIN_FILTER_LINEAR);
758 
//        txfilter |= (R300_TX_MAG_FILTER_LINEAR | R300_TX_MIN_FILTER_LINEAR);
 757 
//        break;
759 
//        break;
 758 
//    default:
760 
//    default:
 759 
//        RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter));
761 
//        RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter));
 760 
//    }
762 
//    }
 761 
 
763 
 
 762 
    {
764 
    {
 763 
      u32_t *ring, write;
765 
      u32_t *ring, write;
 764 
 
766 
 
 765 
      BEGIN_ACCEL(7);
767 
      BEGIN_ACCEL(7);
 766 
      OUT_ACCEL_REG(R300_TX_FILTER0_0 + (unit * 4), txfilter);
768 
      OUT_ACCEL_REG(R300_TX_FILTER0_0 + (unit * 4), txfilter);
 767 
      OUT_ACCEL_REG(R300_TX_FILTER1_0 + (unit * 4), 0);
769 
      OUT_ACCEL_REG(R300_TX_FILTER1_0 + (unit * 4), 0);
 768 
      OUT_ACCEL_REG(R300_TX_FORMAT0_0 + (unit * 4), txformat0);
770 
      OUT_ACCEL_REG(R300_TX_FORMAT0_0 + (unit * 4), txformat0);
 769 
      OUT_ACCEL_REG(R300_TX_FORMAT1_0 + (unit * 4), txformat1);
771 
      OUT_ACCEL_REG(R300_TX_FORMAT1_0 + (unit * 4), txformat1);
 770 
      OUT_ACCEL_REG(R300_TX_FORMAT2_0 + (unit * 4), txpitch);
772 
      OUT_ACCEL_REG(R300_TX_FORMAT2_0 + (unit * 4), txpitch);
 771 
      OUT_ACCEL_REG(R300_TX_OFFSET_0 + (unit * 4), txoffset);
773 
      OUT_ACCEL_REG(R300_TX_OFFSET_0 + (unit * 4), txoffset);
 772 
//    if (!pPict->repeat)
774 
//    if (!pPict->repeat)
 773 
      OUT_ACCEL_REG(R300_TX_BORDER_COLOR_0 + (unit * 4), 0);
775 
      OUT_ACCEL_REG(R300_TX_BORDER_COLOR_0 + (unit * 4), 0);
 774 
      FINISH_ACCEL();
776 
      FINISH_ACCEL();
 775 
    }
777 
    }
 776 
//    if (pPict->transform != 0) {
778 
//    if (pPict->transform != 0) {
 777 
//        is_transform[unit] = TRUE;
779 
//        is_transform[unit] = TRUE;
 778 
//        transform[unit] = pPict->transform;
780 
//        transform[unit] = pPict->transform;
 779 
//    } else {
781 
//    } else {
 780 
//        is_transform[unit] = FALSE;
782 
//        is_transform[unit] = FALSE;
 781 
//    }
783 
//    }
 782 
 
784 
 
 783 
    return TRUE;
785 
    return TRUE;
 784 
}
786 
}
 785 
 
787 
 
 786 
static u32_t RADEONGetBlendCntl(int op, u32_t dst_format)
788 
static u32_t RADEONGetBlendCntl(int op, u32_t dst_format)
 787 
{
789 
{
 788 
    u32_t sblend, dblend;
790 
    u32_t sblend, dblend;
 789 
 
791 
 
 790 
    sblend = RadeonBlendOp[op].blend_cntl & RADEON_SRC_BLEND_MASK;
792 
    sblend = RadeonBlendOp[op].blend_cntl & RADEON_SRC_BLEND_MASK;
 791 
    dblend = RadeonBlendOp[op].blend_cntl & RADEON_DST_BLEND_MASK;
793 
    dblend = RadeonBlendOp[op].blend_cntl & RADEON_DST_BLEND_MASK;
 792 
 
794 
 
 793 
    /* If there's no dst alpha channel, adjust the blend op so that we'll treat
795 
    /* If there's no dst alpha channel, adjust the blend op so that we'll treat
 794 
     * it as always 1.
796 
     * it as always 1.
 795 
     */
797 
     */
 796 
    if (PICT_FORMAT_A(dst_format) == 0 && RadeonBlendOp[op].dst_alpha) {
798 
    if (PICT_FORMAT_A(dst_format) == 0 && RadeonBlendOp[op].dst_alpha) {
 797 
	if (sblend == RADEON_SRC_BLEND_GL_DST_ALPHA)
799 
	if (sblend == RADEON_SRC_BLEND_GL_DST_ALPHA)
 798 
	    sblend = RADEON_SRC_BLEND_GL_ONE;
800 
	    sblend = RADEON_SRC_BLEND_GL_ONE;
 799 
	else if (sblend == RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA)
801 
	else if (sblend == RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA)
 800 
	    sblend = RADEON_SRC_BLEND_GL_ZERO;
802 
	    sblend = RADEON_SRC_BLEND_GL_ZERO;
 801 
    }
803 
    }
 802 
 
804 
 
 803 
    return sblend | dblend;
805 
    return sblend | dblend;
 804 
}
806 
}
 805 
 
807 
 
 806 
static Bool R300PrepareComposite(int op, int srcX, int srcY,
808 
static Bool R300PrepareComposite(int op, int srcX, int srcY,
 807 
                                int dstX, int dstY,
809 
                                int dstX, int dstY,
 808 
                                int w, int h)
810 
                                int w, int h)
 809 
{
811 
{
 810 
  //  RINFO_FROM_SCREEN(pDst->drawable.pScreen);
812 
  //  RINFO_FROM_SCREEN(pDst->drawable.pScreen);
 811 
    u32_t dst_format, dst_offset, dst_pitch;
813 
    u32_t dst_format, dst_offset, dst_pitch;
 812 
    u32_t txenable, colorpitch;
814 
    u32_t txenable, colorpitch;
 813 
    u32_t blendcntl;
815 
    u32_t blendcntl;
 814 
    int pixel_shift;
816 
    int pixel_shift;
 815 
    u32_t *ring, write;
817 
    u32_t *ring, write;
 816 
 
818 
 
 817 
    //ACCEL_PREAMBLE();
819 
    //ACCEL_PREAMBLE();
 818 
 
820 
 
 819 
    //TRACE;
821 
    //TRACE;
 820 
 
822 
 
 821 
    //if (!info->XInited3D)
823 
    //if (!info->XInited3D)
 822 
    //    RADEONInit3DEngine(pScrn);
824 
    //    RADEONInit3DEngine(pScrn);
 823 
 
825 
 
 824 
    //if (!R300GetDestFormat(pDstPicture, &dst_format))
826 
    //if (!R300GetDestFormat(pDstPicture, &dst_format))
 825 
    //    return FALSE;
827 
    //    return FALSE;
 826 
    dst_format = R300_COLORFORMAT_ARGB8888;
828 
    dst_format = R300_COLORFORMAT_ARGB8888;
 827 
 
829 
 
 828 
    pixel_shift = 32 >> 4;
830 
    pixel_shift = 32 >> 4;
 829 
 
831 
 
 830 
    //dst_offset = exaGetPixmapOffset(pDst) + info->fbLocation + pScrn->fbOffset;
832 
    //dst_offset = exaGetPixmapOffset(pDst) + info->fbLocation + pScrn->fbOffset;
 831 
    dst_offset = rhd.FbIntAddress + rhd.FbScanoutStart;
833 
    dst_offset = rhd.FbIntAddress + rhd.FbScanoutStart;
 832 
 
834 
 
 833 
    //dst_pitch = exaGetPixmapPitch(pDst);
835 
    //dst_pitch = exaGetPixmapPitch(pDst);
 834 
    dst_pitch = rhd.displayWidth * 4;
836 
    dst_pitch = rhd.displayWidth * 4;
 835 
    colorpitch = dst_pitch >> pixel_shift;
837 
    colorpitch = dst_pitch >> pixel_shift;
 836 
 
838 
 
 837 
  //  if (RADEONPixmapIsColortiled(pDst))
839 
  //  if (RADEONPixmapIsColortiled(pDst))
 838 
  //      colorpitch |= R300_COLORTILE;
840 
  //      colorpitch |= R300_COLORTILE;
 839 
 
841 
 
 840 
    colorpitch |= dst_format;
842 
    colorpitch |= dst_format;
 841 
 
843 
 
 842 
    if ((dst_offset & 0x0f) != 0)
844 
    if ((dst_offset & 0x0f) != 0)
 843 
        dbgprintf("Bad destination offset 0x%x\n", (int)dst_offset);
845 
        dbgprintf("Bad destination offset 0x%x\n", (int)dst_offset);
 844 
    if (((dst_pitch >> pixel_shift) & 0x7) != 0)
846 
    if (((dst_pitch >> pixel_shift) & 0x7) != 0)
 845 
        dbgprintf("Bad destination pitch 0x%x\n", (int)dst_pitch);
847 
        dbgprintf("Bad destination pitch 0x%x\n", (int)dst_pitch);
 846 
 
848 
 
 847 
  //  if (!RADEONSetupSourceTile(pSrcPicture, pSrc, TRUE, FALSE))
849 
  //  if (!RADEONSetupSourceTile(pSrcPicture, pSrc, TRUE, FALSE))
 848 
  //      return FALSE;
850 
  //      return FALSE;
 849 
 
851 
 
 850 
    if (!R300TextureSetup(w, h, 0))
852 
    if (!R300TextureSetup(w, h, 0))
 851 
	return FALSE;
853 
	return FALSE;
 852 
 
854 
 
 853 
    txenable = R300_TEX_0_ENABLE;
855 
    txenable = R300_TEX_0_ENABLE;
 854 
 
856 
 
 855 
  //  RADEON_SWITCH_TO_3D();
857 
  //  RADEON_SWITCH_TO_3D();
 856 
 
858 
 
 857 
    /* setup the VAP */
859 
    /* setup the VAP */
 858 
    BEGIN_ACCEL(7);
860 
    BEGIN_ACCEL(7);
 859 
 
861 
 
 860 
    /* These registers define the number, type, and location of data submitted
862 
    /* These registers define the number, type, and location of data submitted
 861 
     * to the PVS unit of GA input (when PVS is disabled)
863 
     * to the PVS unit of GA input (when PVS is disabled)
 862 
     * DST_VEC_LOC is the slot in the PVS input vector memory when PVS/TCL is
864 
     * DST_VEC_LOC is the slot in the PVS input vector memory when PVS/TCL is
 863 
     * enabled.  This memory provides the imputs to the vertex shader program
865 
     * enabled.  This memory provides the imputs to the vertex shader program
 864 
     * and ordering is not important.  When PVS/TCL is disabled, this field maps
866 
     * and ordering is not important.  When PVS/TCL is disabled, this field maps
 865 
     * directly to the GA input memory and the order is signifigant.  In
867 
     * directly to the GA input memory and the order is signifigant.  In
 866 
     * PVS_BYPASS mode the order is as follows:
868 
     * PVS_BYPASS mode the order is as follows:
 867 
     * Position
869 
     * Position
 868 
     * Point Size
870 
     * Point Size
 869 
     * Color 0-3
871 
     * Color 0-3
 870 
     * Textures 0-7
872 
     * Textures 0-7
 871 
     * Fog
873 
     * Fog
 872 
     */
874 
     */
 873 
 
875 
 
 874 
     OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0,
876 
     OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0,
 875 
                   ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
877 
                   ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
 876 
                    (0 << R300_SKIP_DWORDS_0_SHIFT) |
878 
                    (0 << R300_SKIP_DWORDS_0_SHIFT) |
 877 
                    (0 << R300_DST_VEC_LOC_0_SHIFT) |
879 
                    (0 << R300_DST_VEC_LOC_0_SHIFT) |
 878 
                     R300_SIGNED_0 |
880 
                     R300_SIGNED_0 |
 879 
                    (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
881 
                    (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
 880 
                    (0 << R300_SKIP_DWORDS_1_SHIFT) |
882 
                    (0 << R300_SKIP_DWORDS_1_SHIFT) |
 881 
                    (6 << R300_DST_VEC_LOC_1_SHIFT) |
883 
                    (6 << R300_DST_VEC_LOC_1_SHIFT) |
 882 
                     R300_LAST_VEC_1 |
884 
                     R300_LAST_VEC_1 |
 883 
                     R300_SIGNED_1));
885 
                     R300_SIGNED_1));
 884 
 
886 
 
 885 
    /* load the vertex shader
887 
    /* load the vertex shader
 886 
     * We pre-load vertex programs in RADEONInit3DEngine():
888 
     * We pre-load vertex programs in RADEONInit3DEngine():
 887 
     * - exa no mask
889 
     * - exa no mask
 888 
     * - exa mask
890 
     * - exa mask
 889 
     * - Xv
891 
     * - Xv
 890 
     * Here we select the offset of the vertex program we want to use
892 
     * Here we select the offset of the vertex program we want to use
 891 
     */
893 
     */
 892 
	    OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
894 
	    OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
 893 
			  ((3 << R300_PVS_FIRST_INST_SHIFT) |
895 
			  ((3 << R300_PVS_FIRST_INST_SHIFT) |
 894 
			   (4 << R300_PVS_XYZW_VALID_INST_SHIFT) |
896 
			   (4 << R300_PVS_XYZW_VALID_INST_SHIFT) |
 895 
			   (4 << R300_PVS_LAST_INST_SHIFT)));
897 
			   (4 << R300_PVS_LAST_INST_SHIFT)));
 896 
	    OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1,
898 
	    OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1,
 897 
			  (4 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
899 
			  (4 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
 898 
 
900 
 
 899 
    /* Position and one or two sets of 2 texture coordinates */
901 
    /* Position and one or two sets of 2 texture coordinates */
 900 
    OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT);
902 
    OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT);
 901 
    OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT));
903 
    OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT));
 902 
 
904 
 
 903 
    OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0);
905 
    OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0);
 904 
    OUT_ACCEL_REG(R300_TX_ENABLE, txenable);
906 
    OUT_ACCEL_REG(R300_TX_ENABLE, txenable);
 905 
    FINISH_ACCEL();
907 
    FINISH_ACCEL();
 906 
 
908 
 
 907 
    /* setup pixel shader */
909 
    /* setup pixel shader */
 908 
    if (IS_R300_3D) {
910 
    if (IS_R300_3D) {
 909 
    } else {
911 
    } else {
 910 
        u32_t output_fmt;
912 
        u32_t output_fmt;
 911 
        u32_t src_color, src_alpha;
913 
        u32_t src_color, src_alpha;
 912 
        u32_t mask_color, mask_alpha;
914 
        u32_t mask_color, mask_alpha;
 913 
 
915 
 
 914 
        if (PICT_FORMAT_RGB(PICT_a8r8g8b8) == 0)
916 
        if (PICT_FORMAT_RGB(PICT_a8r8g8b8) == 0)
 915 
	    src_color = (R500_ALU_RGB_R_SWIZ_A_0 |
917 
	    src_color = (R500_ALU_RGB_R_SWIZ_A_0 |
 916 
			 R500_ALU_RGB_G_SWIZ_A_0 |
918 
			 R500_ALU_RGB_G_SWIZ_A_0 |
 917 
			 R500_ALU_RGB_B_SWIZ_A_0);
919 
			 R500_ALU_RGB_B_SWIZ_A_0);
 918 
	else
920 
	else
 919 
	    src_color = (R500_ALU_RGB_R_SWIZ_A_R |
921 
	    src_color = (R500_ALU_RGB_R_SWIZ_A_R |
 920 
			 R500_ALU_RGB_G_SWIZ_A_G |
922 
			 R500_ALU_RGB_G_SWIZ_A_G |
 921 
			 R500_ALU_RGB_B_SWIZ_A_B);
923 
			 R500_ALU_RGB_B_SWIZ_A_B);
 922 
 
924 
 
 923 
        if (PICT_FORMAT_A(PICT_a8r8g8b8) == 0)
925 
        if (PICT_FORMAT_A(PICT_a8r8g8b8) == 0)
 924 
	    src_alpha = R500_ALPHA_SWIZ_A_1;
926 
	    src_alpha = R500_ALPHA_SWIZ_A_1;
 925 
	else
927 
	else
 926 
	    src_alpha = R500_ALPHA_SWIZ_A_A;
928 
	    src_alpha = R500_ALPHA_SWIZ_A_A;
 927 
 
929 
 
 928 
        mask_color = (R500_ALU_RGB_R_SWIZ_B_1 |
930 
        mask_color = (R500_ALU_RGB_R_SWIZ_B_1 |
 929 
                      R500_ALU_RGB_G_SWIZ_B_1 |
931 
                      R500_ALU_RGB_G_SWIZ_B_1 |
 930 
                      R500_ALU_RGB_B_SWIZ_B_1);
932 
                      R500_ALU_RGB_B_SWIZ_B_1);
 931 
        mask_alpha = R500_ALPHA_SWIZ_B_1;
933 
        mask_alpha = R500_ALPHA_SWIZ_B_1;
 932 
 
934 
 
 933 
	/* shader output swizzling */
935 
	/* shader output swizzling */
 934 
        output_fmt = (R300_OUT_FMT_C4_8         |
936 
        output_fmt = (R300_OUT_FMT_C4_8         |
 935 
                      R300_OUT_FMT_C0_SEL_BLUE  |
937 
                      R300_OUT_FMT_C0_SEL_BLUE  |
 936 
                      R300_OUT_FMT_C1_SEL_GREEN |
938 
                      R300_OUT_FMT_C1_SEL_GREEN |
 937 
                      R300_OUT_FMT_C2_SEL_RED   |
939 
                      R300_OUT_FMT_C2_SEL_RED   |
 938 
                      R300_OUT_FMT_C3_SEL_ALPHA);
940 
                      R300_OUT_FMT_C3_SEL_ALPHA);
 939 
 
941 
 
 940 
	BEGIN_ACCEL(6);
942 
	BEGIN_ACCEL(6);
 941 
        OUT_ACCEL_REG(R300_RS_COUNT,
943 
        OUT_ACCEL_REG(R300_RS_COUNT,
 942 
                     ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
944 
                     ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
 943 
                       R300_RS_COUNT_HIRES_EN));
945 
                       R300_RS_COUNT_HIRES_EN));
 944 
 
946 
 
 945 
        OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
947 
        OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
 946 
 
948 
 
 947 
        OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
949 
        OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
 948 
                                          R500_US_CODE_END_ADDR(1)));
950 
                                          R500_US_CODE_END_ADDR(1)));
 949 
        OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
951 
        OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
 950 
                                           R500_US_CODE_RANGE_SIZE(1)));
952 
                                           R500_US_CODE_RANGE_SIZE(1)));
 951 
        OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0);
953 
        OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0);
 952 
 
954 
 
 953 
	OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt);
955 
	OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt);
 954 
	FINISH_ACCEL();
956 
	FINISH_ACCEL();
 955 
 
957 
 
 956 
        BEGIN_ACCEL(13);
958 
        BEGIN_ACCEL(13);
 957 
        OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0);
959 
        OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0);
 958 
	    /* tex inst for src texture */
960 
	    /* tex inst for src texture */
 959 
        OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX     |
961 
        OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX     |
 960 
                                               R500_INST_TEX_SEM_WAIT |
962 
                                               R500_INST_TEX_SEM_WAIT |
 961 
                                               R500_INST_RGB_WMASK_R  |
963 
                                               R500_INST_RGB_WMASK_R  |
 962 
                                               R500_INST_RGB_WMASK_G  |
964 
                                               R500_INST_RGB_WMASK_G  |
 963 
                                               R500_INST_RGB_WMASK_B  |
965 
                                               R500_INST_RGB_WMASK_B  |
 964 
                                               R500_INST_ALPHA_WMASK  |
966 
                                               R500_INST_ALPHA_WMASK  |
 965 
                                               R500_INST_RGB_CLAMP |
967 
                                               R500_INST_RGB_CLAMP |
 966 
                                               R500_INST_ALPHA_CLAMP));
968 
                                               R500_INST_ALPHA_CLAMP));
 967 
 
969 
 
 968 
       OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
970 
       OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
 969 
						   R500_TEX_INST_LD |
971 
						   R500_TEX_INST_LD |
 970 
						   R500_TEX_SEM_ACQUIRE |
972 
						   R500_TEX_SEM_ACQUIRE |
 971 
						   R500_TEX_IGNORE_UNCOVERED));
973 
						   R500_TEX_IGNORE_UNCOVERED));
 972 
 
974 
 
 973 
	    OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
975 
	    OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
 974 
						   R500_TEX_SRC_S_SWIZ_R |
976 
						   R500_TEX_SRC_S_SWIZ_R |
 975 
						   R500_TEX_SRC_T_SWIZ_G |
977 
						   R500_TEX_SRC_T_SWIZ_G |
 976 
						   R500_TEX_DST_ADDR(0) |
978 
						   R500_TEX_DST_ADDR(0) |
 977 
						   R500_TEX_DST_R_SWIZ_R |
979 
						   R500_TEX_DST_R_SWIZ_R |
 978 
						   R500_TEX_DST_G_SWIZ_G |
980 
						   R500_TEX_DST_G_SWIZ_G |
 979 
						   R500_TEX_DST_B_SWIZ_B |
981 
						   R500_TEX_DST_B_SWIZ_B |
 980 
						   R500_TEX_DST_A_SWIZ_A));
982 
						   R500_TEX_DST_A_SWIZ_A));
 981 
	    OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
983 
	    OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
 982 
						   R500_DX_S_SWIZ_R |
984 
						   R500_DX_S_SWIZ_R |
 983 
						   R500_DX_T_SWIZ_R |
985 
						   R500_DX_T_SWIZ_R |
 984 
						   R500_DX_R_SWIZ_R |
986 
						   R500_DX_R_SWIZ_R |
 985 
						   R500_DX_Q_SWIZ_R |
987 
						   R500_DX_Q_SWIZ_R |
 986 
						   R500_DY_ADDR(0) |
988 
						   R500_DY_ADDR(0) |
 987 
						   R500_DY_S_SWIZ_R |
989 
						   R500_DY_S_SWIZ_R |
 988 
						   R500_DY_T_SWIZ_R |
990 
						   R500_DY_T_SWIZ_R |
 989 
						   R500_DY_R_SWIZ_R |
991 
						   R500_DY_R_SWIZ_R |
 990 
						   R500_DY_Q_SWIZ_R));
992 
						   R500_DY_Q_SWIZ_R));
 991 
	    OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
993 
	    OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
 992 
	    OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
994 
	    OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
 993 
 
995 
 
 994 
	/* ALU inst */
996 
	/* ALU inst */
 995 
	/* *_OMASK* - output component write mask */
997 
	/* *_OMASK* - output component write mask */
 996 
	OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
998 
	OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
 997 
					       R500_INST_TEX_SEM_WAIT |
999 
					       R500_INST_TEX_SEM_WAIT |
 998 
					       R500_INST_LAST |
1000 
					       R500_INST_LAST |
 999 
					       R500_INST_RGB_OMASK_R |
1001 
					       R500_INST_RGB_OMASK_R |
 1000 
					       R500_INST_RGB_OMASK_G |
1002 
					       R500_INST_RGB_OMASK_G |
 1001 
					       R500_INST_RGB_OMASK_B |
1003 
					       R500_INST_RGB_OMASK_B |
 1002 
					       R500_INST_ALPHA_OMASK |
1004 
					       R500_INST_ALPHA_OMASK |
 1003 
					       R500_INST_RGB_CLAMP |
1005 
					       R500_INST_RGB_CLAMP |
 1004 
					       R500_INST_ALPHA_CLAMP));
1006 
					       R500_INST_ALPHA_CLAMP));
 1005 
	/* ALU inst
1007 
	/* ALU inst
 1006 
	 * temp addresses for texture inputs
1008 
	 * temp addresses for texture inputs
 1007 
	 * RGB_ADDR0 is src tex (temp 0)
1009 
	 * RGB_ADDR0 is src tex (temp 0)
 1008 
	 * RGB_ADDR1 is mask tex (temp 1)
1010 
	 * RGB_ADDR1 is mask tex (temp 1)
 1009 
	 */
1011 
	 */
 1010 
	OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
1012 
	OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
 1011 
					       R500_RGB_ADDR1(1) |
1013 
					       R500_RGB_ADDR1(1) |
 1012 
					       R500_RGB_ADDR2(0)));
1014 
					       R500_RGB_ADDR2(0)));
 1013 
	/* ALU inst
1015 
	/* ALU inst
 1014 
	 * temp addresses for texture inputs
1016 
	 * temp addresses for texture inputs
 1015 
	 * ALPHA_ADDR0 is src tex (temp 0)
1017 
	 * ALPHA_ADDR0 is src tex (temp 0)
 1016 
	 * ALPHA_ADDR1 is mask tex (temp 1)
1018 
	 * ALPHA_ADDR1 is mask tex (temp 1)
 1017 
	 */
1019 
	 */
 1018 
	OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
1020 
	OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
 1019 
					       R500_ALPHA_ADDR1(1) |
1021 
					       R500_ALPHA_ADDR1(1) |
 1020 
					       R500_ALPHA_ADDR2(0)));
1022 
					       R500_ALPHA_ADDR2(0)));
 1021 
 
1023 
 
 1022 
	/* R500_ALU_RGB_TARGET - RGB render target */
1024 
	/* R500_ALU_RGB_TARGET - RGB render target */
 1023 
	OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
1025 
	OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
 1024 
					       src_color |
1026 
					       src_color |
 1025 
					       R500_ALU_RGB_SEL_B_SRC1 |
1027 
					       R500_ALU_RGB_SEL_B_SRC1 |
 1026 
					       mask_color |
1028 
					       mask_color |
 1027 
					       R500_ALU_RGB_TARGET(0)));
1029 
					       R500_ALU_RGB_TARGET(0)));
 1028 
 
1030 
 
 1029 
	/* R500_ALPHA_RGB_TARGET - alpha render target */
1031 
	/* R500_ALPHA_RGB_TARGET - alpha render target */
 1030 
	OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
1032 
	OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
 1031 
					       R500_ALPHA_ADDRD(0) |
1033 
					       R500_ALPHA_ADDRD(0) |
 1032 
					       R500_ALPHA_SEL_A_SRC0 |
1034 
					       R500_ALPHA_SEL_A_SRC0 |
 1033 
					       src_alpha |
1035 
					       src_alpha |
 1034 
					       R500_ALPHA_SEL_B_SRC1 |
1036 
					       R500_ALPHA_SEL_B_SRC1 |
 1035 
					       mask_alpha |
1037 
					       mask_alpha |
 1036 
					       R500_ALPHA_TARGET(0)));
1038 
					       R500_ALPHA_TARGET(0)));
 1037 
 
1039 
 
 1038 
	OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
1040 
	OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
 1039 
					       R500_ALU_RGBA_ADDRD(0) |
1041 
					       R500_ALU_RGBA_ADDRD(0) |
 1040 
					       R500_ALU_RGBA_R_SWIZ_0 |
1042 
					       R500_ALU_RGBA_R_SWIZ_0 |
 1041 
					       R500_ALU_RGBA_G_SWIZ_0 |
1043 
					       R500_ALU_RGBA_G_SWIZ_0 |
 1042 
					       R500_ALU_RGBA_B_SWIZ_0 |
1044 
					       R500_ALU_RGBA_B_SWIZ_0 |
 1043 
					       R500_ALU_RGBA_A_SWIZ_0));
1045 
					       R500_ALU_RGBA_A_SWIZ_0));
 1044 
	FINISH_ACCEL();
1046 
	FINISH_ACCEL();
 1045 
    }
1047 
    }
 1046 
 
1048 
 
 1047 
    BEGIN_ACCEL(3);
1049 
    BEGIN_ACCEL(3);
 1048 
 
1050 
 
 1049 
    OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset);
1051 
    OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset);
 1050 
    OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch);
1052 
    OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch);
 1051 
 
1053 
 
 1052 
    blendcntl = RADEONGetBlendCntl(op, PICT_a8r8g8b8);
1054 
    blendcntl = RADEONGetBlendCntl(op, PICT_a8r8g8b8);
 1053 
    OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl | R300_ALPHA_BLEND_ENABLE | R300_READ_ENABLE);
1055 
    OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl | R300_ALPHA_BLEND_ENABLE | R300_READ_ENABLE);
 1054 
 
1056 
 
 1055 
    FINISH_ACCEL();
1057 
    FINISH_ACCEL();
 1056 
 
1058 
 
 1057 
    return TRUE;
1059 
    return TRUE;
 1058 
}
1060 
}
 1059 
 
1061 
 
 1060 
 
1062 
 
 1061 
 
1063 
 
 1062 
 
1064 
 
 1063 
 
1065 
 
 1064 
 
1066 
 
 1065 
#define VTX_COUNT 4
1067 
#define VTX_COUNT 4
 1066 
 
1068 
 
 1067 
static __inline__ u32_t F_TO_DW(float val)
1069 
static __inline__ u32_t F_TO_DW(float val)
 1068 
{
1070 
{
 1069 
    union {
1071 
    union {
 1070 
	float f;
1072 
	float f;
 1071 
        u32_t l;
1073 
        u32_t l;
 1072 
    } tmp;
1074 
    } tmp;
 1073 
    tmp.f = val;
1075 
    tmp.f = val;
 1074 
    return tmp.l;
1076 
    return tmp.l;
 1075 
}
1077 
}
 1076 
 
1078 
 
 1077 
#define OUT_RING_F(x) OUT_RING(F_TO_DW(x))
1079 
#define OUT_RING_F(x) OUT_RING(F_TO_DW(x))
 1078 
 
1080 
 
 1079 
#define VTX_OUT(_dstX, _dstY, _srcX, _srcY)     \
1081 
#define VTX_OUT(_dstX, _dstY, _srcX, _srcY)     \
 1080 
do {								\
1082 
do {								\
 1081 
    OUT_RING_F(_dstX);						\
1083 
    OUT_RING_F(_dstX);						\
 1082 
    OUT_RING_F(_dstY);						\
1084 
    OUT_RING_F(_dstY);						\
 1083 
    OUT_RING_F(_srcX);						\
1085 
    OUT_RING_F(_srcX);						\
 1084 
    OUT_RING_F(_srcY);						\
1086 
    OUT_RING_F(_srcY);						\
 1085 
} while (0)
1087 
} while (0)
 1086 
 
1088 
 
 1087 
 
1089 
 
 1088 
 
1090 
 
 1089 
static void RadeonCompositeTile(int srcX, int srcY,
1091 
static void RadeonCompositeTile(int srcX, int srcY,
 1090 
                                int dstX, int dstY,
1092 
                                int dstX, int dstY,
 1091 
                                int w, int h)
1093 
                                int w, int h)
 1092 
{
1094 
{
 1093 
  //  RINFO_FROM_SCREEN(pDst->drawable.pScreen);
1095 
  //  RINFO_FROM_SCREEN(pDst->drawable.pScreen);
 1094 
    int vtx_count;
1096 
    int vtx_count;
 1095 
    xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight;
1097 
    xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight;
 1096 
    xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight;
1098 
    xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight;
 1097 
 
1099 
 
 1098 
    u32_t *ring, write;
1100 
    u32_t *ring, write;
 1099 
 
1101 
 
 1100 
 
1102 
 
 1101 
 //   ACCEL_PREAMBLE();
1103 
 //   ACCEL_PREAMBLE();
 1102 
 
1104 
 
 1103 
 //   ENTER_DRAW(0);
1105 
 //   ENTER_DRAW(0);
 1104 
 
1106 
 
 1105 
    /* ErrorF("RadeonComposite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n",
1107 
    /* ErrorF("RadeonComposite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n",
 1106 
       srcX, srcY, maskX, maskY,dstX, dstY, w, h); */
1108 
       srcX, srcY, maskX, maskY,dstX, dstY, w, h); */
 1107 
 
1109 
 
 1108 
    srcTopLeft.x     = IntToxFixed(srcX);
1110 
    srcTopLeft.x     = IntToxFixed(srcX);
 1109 
    srcTopLeft.y     = IntToxFixed(srcY);
1111 
    srcTopLeft.y     = IntToxFixed(srcY);
 1110 
    srcTopRight.x    = IntToxFixed(srcX + w);
1112 
    srcTopRight.x    = IntToxFixed(srcX + w);
 1111 
    srcTopRight.y    = IntToxFixed(srcY);
1113 
    srcTopRight.y    = IntToxFixed(srcY);
 1112 
    srcBottomLeft.x  = IntToxFixed(srcX);
1114 
    srcBottomLeft.x  = IntToxFixed(srcX);
 1113 
    srcBottomLeft.y  = IntToxFixed(srcY + h);
1115 
    srcBottomLeft.y  = IntToxFixed(srcY + h);
 1114 
    srcBottomRight.x = IntToxFixed(srcX + w);
1116 
    srcBottomRight.x = IntToxFixed(srcX + w);
 1115 
    srcBottomRight.y = IntToxFixed(srcY + h);
1117 
    srcBottomRight.y = IntToxFixed(srcY + h);
 1116 
 
1118 
 
 1117 
/*
1119 
/*
 1118 
    if (is_transform[0]) {
1120 
    if (is_transform[0]) {
 1119 
	transformPoint(transform[0], &srcTopLeft);
1121 
	transformPoint(transform[0], &srcTopLeft);
 1120 
	transformPoint(transform[0], &srcTopRight);
1122 
	transformPoint(transform[0], &srcTopRight);
 1121 
	transformPoint(transform[0], &srcBottomLeft);
1123 
	transformPoint(transform[0], &srcBottomLeft);
 1122 
	transformPoint(transform[0], &srcBottomRight);
1124 
	transformPoint(transform[0], &srcBottomRight);
 1123 
    }
1125 
    }
 1124 
    if (is_transform[1]) {
1126 
    if (is_transform[1]) {
 1125 
	transformPoint(transform[1], &maskTopLeft);
1127 
	transformPoint(transform[1], &maskTopLeft);
 1126 
	transformPoint(transform[1], &maskTopRight);
1128 
	transformPoint(transform[1], &maskTopRight);
 1127 
	transformPoint(transform[1], &maskBottomLeft);
1129 
	transformPoint(transform[1], &maskBottomLeft);
 1128 
	transformPoint(transform[1], &maskBottomRight);
1130 
	transformPoint(transform[1], &maskBottomRight);
 1129 
    }
1131 
    }
 1130 
*/
1132 
*/
 1131 
    vtx_count = VTX_COUNT;
1133 
    vtx_count = VTX_COUNT;
 1132 
 
1134 
 
 1133 
    BEGIN_ACCEL(1);
1135 
    BEGIN_ACCEL(1);
 1134 
    OUT_ACCEL_REG(R300_VAP_VTX_SIZE, vtx_count);
1136 
    OUT_ACCEL_REG(R300_VAP_VTX_SIZE, vtx_count);
 1135 
    FINISH_ACCEL();
1137 
    FINISH_ACCEL();
 1136 
 
1138 
 
 1137 
    BEGIN_RING(4 * vtx_count + 4);
1139 
    BEGIN_RING(4 * vtx_count + 4);
 1138 
 
1140 
 
 1139 
      OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2,
1141 
      OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2,
 1140 
                        4 * vtx_count));
1142 
                        4 * vtx_count));
 1141 
      OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN |
1143 
      OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN |
 1142 
              RADEON_CP_VC_CNTL_PRIM_WALK_RING |
1144 
              RADEON_CP_VC_CNTL_PRIM_WALK_RING |
 1143 
              (4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
1145 
              (4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
 1144 
 
1146 
 
 1145 
 
1147 
 
 1146 
      VTX_OUT((float)dstX, (float)dstY,
1148 
      VTX_OUT((float)dstX, (float)dstY,
 1147 
              xFixedToFloat(srcTopLeft.x) / w,      // info->texW[0],
1149 
              xFixedToFloat(srcTopLeft.x) / w,      // info->texW[0],
 1148 
              xFixedToFloat(srcTopLeft.y) / h);     // info->texH[0]);
1150 
              xFixedToFloat(srcTopLeft.y) / h);     // info->texH[0]);
 1149 
 
1151 
 
 1150 
      VTX_OUT((float)dstX, (float)(dstY + h),
1152 
      VTX_OUT((float)dstX, (float)(dstY + h),
 1151 
              xFixedToFloat(srcBottomLeft.x) / w,   // info->texW[0],
1153 
              xFixedToFloat(srcBottomLeft.x) / w,   // info->texW[0],
 1152 
              xFixedToFloat(srcBottomLeft.y) / h);  // info->texH[0]);
1154 
              xFixedToFloat(srcBottomLeft.y) / h);  // info->texH[0]);
 1153 
 
1155 
 
 1154 
      VTX_OUT((float)(dstX + w), (float)(dstY + h),
1156 
      VTX_OUT((float)(dstX + w), (float)(dstY + h),
 1155 
              xFixedToFloat(srcBottomRight.x) / w,  // info->texW[0],
1157 
              xFixedToFloat(srcBottomRight.x) / w,  // info->texW[0],
 1156 
              xFixedToFloat(srcBottomRight.y) / h); // info->texH[0]);
1158 
              xFixedToFloat(srcBottomRight.y) / h); // info->texH[0]);
 1157 
 
1159 
 
 1158 
      VTX_OUT((float)(dstX + w), (float)dstY,
1160 
      VTX_OUT((float)(dstX + w), (float)dstY,
 1159 
              xFixedToFloat(srcTopRight.x) / w,     // info->texW[0],
1161 
              xFixedToFloat(srcTopRight.x) / w,     // info->texW[0],
 1160 
              xFixedToFloat(srcTopRight.y) / h);    // info->texH[0]);
1162 
              xFixedToFloat(srcTopRight.y) / h);    // info->texH[0]);
 1161 
 
1163 
 
 1162 
          /* flushing is pipelined, free/finish is not */
1164 
          /* flushing is pipelined, free/finish is not */
 1163 
      OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D);
1165 
      OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D);
 1164 
 
1166 
 
 1165 
 //     OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
1167 
 //     OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
 1166 
 
1168 
 
 1167 
    COMMIT_RING();
1169 
    COMMIT_RING();
 1168 
 
1170 
 
 1169 
 //   LEAVE_DRAW(0);
1171 
 //   LEAVE_DRAW(0);
 1170 
}
1172 
}
 1171 
#undef VTX_OUT
1173 
#undef VTX_OUT
 1172 
#undef VTX_OUT_MASK
1174 
#undef VTX_OUT_MASK
 1173 
 
1175 
 
 1174 
#if 0
1176 
#if 0
 1175 
 
1177 
 
 1176 
int RadeonComposite( blit_t *blit)
1178 
int RadeonComposite( blit_t *blit)
 1177 
{
1179 
{
 1178 
    int tileSrcY, tileMaskY, tileDstY;
1180 
    int tileSrcY, tileMaskY, tileDstY;
 1179 
    int remainingHeight;
1181 
    int remainingHeight;
 1180 
 
1182 
 
 1181 
    R300PrepareComposite(3, blit->src_x, blit->src_y,
1183 
    R300PrepareComposite(3, blit->src_x, blit->src_y,
 1182 
                             blit->dst_x, blit->dst_y,
1184 
                             blit->dst_x, blit->dst_y,
 1183 
                             blit->w, blit->h);
1185 
                             blit->w, blit->h);
 1184 
 
1186 
 
 1185 
//    if (!need_src_tile_x && !need_src_tile_y) {
1187 
//    if (!need_src_tile_x && !need_src_tile_y) {
 1186 
        RadeonCompositeTile( blit->src_x, blit->src_y,
1188 
        RadeonCompositeTile( blit->src_x, blit->src_y,
 1187 
                             blit->dst_x, blit->dst_y,
1189 
                             blit->dst_x, blit->dst_y,
 1188 
                             blit->w, blit->h);
1190 
                             blit->w, blit->h);
 1189 
        return 0;
1191 
        return 0;
 1190 
  //  }
1192 
  //  }
 1191 
 
1193 
 
 1192 
    /* Tiling logic borrowed from exaFillRegionTiled */
1194 
    /* Tiling logic borrowed from exaFillRegionTiled */
 1193 
 
1195 
 
 1194 
#if 0
1196 
#if 0
 1195 
    modulus(srcY, src_tile_height, tileSrcY);
1197 
    modulus(srcY, src_tile_height, tileSrcY);
 1196 
    tileMaskY = maskY;
1198 
    tileMaskY = maskY;
 1197 
    tileDstY = dstY;
1199 
    tileDstY = dstY;
 1198 
 
1200 
 
 1199 
    remainingHeight = height;
1201 
    remainingHeight = height;
 1200 
    while (remainingHeight > 0) {
1202 
    while (remainingHeight > 0) {
 1201 
	int remainingWidth = width;
1203 
	int remainingWidth = width;
 1202 
	int tileSrcX, tileMaskX, tileDstX;
1204 
	int tileSrcX, tileMaskX, tileDstX;
 1203 
	int h = src_tile_height - tileSrcY;
1205 
	int h = src_tile_height - tileSrcY;
 1204 
 
1206 
 
 1205 
	if (h > remainingHeight)
1207 
	if (h > remainingHeight)
 1206 
	    h = remainingHeight;
1208 
	    h = remainingHeight;
 1207 
	remainingHeight -= h;
1209 
	remainingHeight -= h;
 1208 
 
1210 
 
 1209 
	modulus(srcX, src_tile_width, tileSrcX);
1211 
	modulus(srcX, src_tile_width, tileSrcX);
 1210 
	tileMaskX = maskX;
1212 
	tileMaskX = maskX;
 1211 
	tileDstX = dstX;
1213 
	tileDstX = dstX;
 1212 
 
1214 
 
 1213 
	while (remainingWidth > 0) {
1215 
	while (remainingWidth > 0) {
 1214 
	    int w = src_tile_width - tileSrcX;
1216 
	    int w = src_tile_width - tileSrcX;
 1215 
	    if (w > remainingWidth)
1217 
	    if (w > remainingWidth)
 1216 
		w = remainingWidth;
1218 
		w = remainingWidth;
 1217 
	    remainingWidth -= w;
1219 
	    remainingWidth -= w;
 1218 
 
1220 
 
 1219 
	    FUNC_NAME(RadeonCompositeTile)(pDst,
1221 
	    FUNC_NAME(RadeonCompositeTile)(pDst,
 1220 
					   tileSrcX, tileSrcY,
1222 
					   tileSrcX, tileSrcY,
 1221 
					   tileMaskX, tileMaskY,
1223 
					   tileMaskX, tileMaskY,
 1222 
					   tileDstX, tileDstY,
1224 
					   tileDstX, tileDstY,
 1223 
					   w, h);
1225 
					   w, h);
 1224 
 
1226 
 
 1225 
	    tileSrcX = 0;
1227 
	    tileSrcX = 0;
 1226 
	    tileMaskX += w;
1228 
	    tileMaskX += w;
 1227 
	    tileDstX += w;
1229 
	    tileDstX += w;
 1228 
	}
1230 
	}
 1229 
	tileSrcY = 0;
1231 
	tileSrcY = 0;
 1230 
	tileMaskY += h;
1232 
	tileMaskY += h;
 1231 
	tileDstY += h;
1233 
	tileDstY += h;
 1232 
    }
1234 
    }
 1233 
#endif
1235 
#endif
 1234 
}
1236 
}
 1235 
 
1237 
 
 1236 
#endif
1238 
#endif
 -