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1 | #include "radeon_reg.h" |
1 | #include "radeon_reg.h" |
2 | 2 | ||
3 | #define BEGIN_ACCEL(n) BEGIN_RING(2*(n)) |
3 | #define BEGIN_ACCEL(n) BEGIN_RING(2*(n)) |
4 | //#define FINISH_ACCEL() ADVANCE_RING() |
4 | //#define FINISH_ACCEL() ADVANCE_RING() |
5 | #define FINISH_ACCEL() COMMIT_RING() |
5 | #define FINISH_ACCEL() COMMIT_RING() |
6 | 6 | ||
7 | #define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val) |
7 | #define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val) |
8 | 8 | ||
9 | #define RADEON_SWITCH_TO_3D() \ |
9 | #define RADEON_SWITCH_TO_3D() \ |
10 | do { \ |
10 | do { \ |
11 | u32_t wait_until = 0; \ |
11 | u32_t wait_until = 0; \ |
12 | BEGIN_ACCEL(1); \ |
12 | BEGIN_ACCEL(1); \ |
13 | wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN; \ |
13 | wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN; \ |
14 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \ |
14 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \ |
15 | FINISH_ACCEL(); \ |
15 | FINISH_ACCEL(); \ |
16 | } while (0); |
16 | } while (0); |
17 | 17 | ||
18 | 18 | ||
19 | struct blendinfo { |
19 | struct blendinfo { |
20 | Bool dst_alpha; |
20 | Bool dst_alpha; |
21 | Bool src_alpha; |
21 | Bool src_alpha; |
22 | u32_t blend_cntl; |
22 | u32_t blend_cntl; |
23 | }; |
23 | }; |
24 | 24 | ||
25 | static struct blendinfo RadeonBlendOp[] = { |
25 | static struct blendinfo RadeonBlendOp[] = { |
26 | /* 0 - Clear */ |
26 | /* 0 - Clear */ |
27 | {0, 0, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ZERO}, |
27 | {0, 0, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ZERO}, |
28 | /* 1 - Src */ |
28 | /* 1 - Src */ |
29 | {0, 0, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO}, |
29 | {0, 0, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO}, |
30 | /* 2 - Dst */ |
30 | /* 2 - Dst */ |
31 | {0, 0, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ONE}, |
31 | {0, 0, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ONE}, |
32 | /* 3 - Over */ |
32 | /* 3 - Over */ |
33 | {0, 1, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
33 | {0, 1, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
34 | /* 4 - OverReverse */ |
34 | /* 4 - OverReverse */ |
35 | {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE}, |
35 | {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE}, |
36 | /* 5 - In */ |
36 | /* 5 - In */ |
37 | {1, 0, RADEON_SRC_BLEND_GL_DST_ALPHA | RADEON_DST_BLEND_GL_ZERO}, |
37 | {1, 0, RADEON_SRC_BLEND_GL_DST_ALPHA | RADEON_DST_BLEND_GL_ZERO}, |
38 | /* 6 - InReverse */ |
38 | /* 6 - InReverse */ |
39 | {0, 1, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_SRC_ALPHA}, |
39 | {0, 1, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_SRC_ALPHA}, |
40 | /* 7 - Out */ |
40 | /* 7 - Out */ |
41 | {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ZERO}, |
41 | {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ZERO}, |
42 | /* 8 - OutReverse */ |
42 | /* 8 - OutReverse */ |
43 | {0, 1, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
43 | {0, 1, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
44 | /* 9 - Atop */ |
44 | /* 9 - Atop */ |
45 | {1, 1, RADEON_SRC_BLEND_GL_DST_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
45 | {1, 1, RADEON_SRC_BLEND_GL_DST_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
46 | /* 10- AtopReverse */ |
46 | /* 10- AtopReverse */ |
47 | {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_SRC_ALPHA}, |
47 | {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_SRC_ALPHA}, |
48 | /* 11 - Xor */ |
48 | /* 11 - Xor */ |
49 | {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
49 | {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
50 | /* 12 - Add */ |
50 | /* 12 - Add */ |
51 | {0, 0, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ONE}, |
51 | {0, 0, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ONE}, |
52 | }; |
52 | }; |
53 | 53 | ||
54 | 54 | ||
55 | static void Init3DEngine(RHDPtr rhdPtr) |
55 | static void Init3DEngine(RHDPtr rhdPtr) |
56 | { |
56 | { |
57 | // RADEONInfoPtr info = RADEONPTR(pScrn); |
57 | // RADEONInfoPtr info = RADEONPTR(pScrn); |
58 | u32_t gb_tile_config, su_reg_dest, vap_cntl; |
58 | u32_t gb_tile_config, su_reg_dest, vap_cntl; |
59 | // ACCEL_PREAMBLE(); |
59 | // ACCEL_PREAMBLE(); |
60 | 60 | ||
61 | u32 *ring, write; |
61 | u32_t *ring, write; |
62 | 62 | ||
63 | // info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1; |
63 | // info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1; |
64 | 64 | ||
65 | if (IS_R300_3D || IS_R500_3D) |
65 | if (IS_R300_3D || IS_R500_3D) |
66 | { |
66 | { |
67 | 67 | ||
68 | BEGIN_ACCEL(3); |
68 | BEGIN_ACCEL(3); |
69 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
69 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
70 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
70 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
71 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
71 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
72 | FINISH_ACCEL(); |
72 | FINISH_ACCEL(); |
73 | 73 | ||
74 | if ( IS_R500_3D) |
74 | if ( IS_R500_3D) |
75 | { |
75 | { |
76 | u32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT); |
76 | u32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT); |
77 | 77 | ||
78 | rhdPtr->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; |
78 | rhdPtr->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; |
79 | RADEONOUTPLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); |
79 | RADEONOUTPLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); |
80 | } |
80 | } |
81 | 81 | ||
82 | dbgprintf("Pipes count %d\n", rhdPtr->num_gb_pipes ); |
82 | dbgprintf("Pipes count %d\n", rhdPtr->num_gb_pipes ); |
83 | 83 | ||
84 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16); |
84 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16); |
85 | 85 | ||
86 | switch(rhdPtr->num_gb_pipes) { |
86 | switch(rhdPtr->num_gb_pipes) { |
87 | case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; |
87 | case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; |
88 | case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; |
88 | case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; |
89 | case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; |
89 | case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; |
90 | default: |
90 | default: |
91 | case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; |
91 | case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; |
92 | } |
92 | } |
93 | 93 | ||
94 | BEGIN_ACCEL(5); |
94 | BEGIN_ACCEL(5); |
95 | OUT_ACCEL_REG(R300_GB_TILE_CONFIG, gb_tile_config); |
95 | OUT_ACCEL_REG(R300_GB_TILE_CONFIG, gb_tile_config); |
96 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
96 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
97 | OUT_ACCEL_REG(R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG); |
97 | OUT_ACCEL_REG(R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG); |
98 | OUT_ACCEL_REG(R300_GB_SELECT, 0); |
98 | OUT_ACCEL_REG(R300_GB_SELECT, 0); |
99 | OUT_ACCEL_REG(R300_GB_ENABLE, 0); |
99 | OUT_ACCEL_REG(R300_GB_ENABLE, 0); |
100 | FINISH_ACCEL(); |
100 | FINISH_ACCEL(); |
101 | 101 | ||
102 | if (IS_R500_3D) { |
102 | if (IS_R500_3D) { |
103 | su_reg_dest = ((1 << rhdPtr->num_gb_pipes) - 1); |
103 | su_reg_dest = ((1 << rhdPtr->num_gb_pipes) - 1); |
104 | BEGIN_ACCEL(2); |
104 | BEGIN_ACCEL(2); |
105 | OUT_ACCEL_REG(R500_SU_REG_DEST, su_reg_dest); |
105 | OUT_ACCEL_REG(R500_SU_REG_DEST, su_reg_dest); |
106 | OUT_ACCEL_REG(R500_VAP_INDEX_OFFSET, 0); |
106 | OUT_ACCEL_REG(R500_VAP_INDEX_OFFSET, 0); |
107 | FINISH_ACCEL(); |
107 | FINISH_ACCEL(); |
108 | } |
108 | } |
109 | 109 | ||
110 | BEGIN_ACCEL(3); |
110 | BEGIN_ACCEL(3); |
111 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
111 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
112 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
112 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
113 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
113 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
114 | FINISH_ACCEL(); |
114 | FINISH_ACCEL(); |
115 | 115 | ||
116 | BEGIN_ACCEL(5); |
116 | BEGIN_ACCEL(5); |
117 | OUT_ACCEL_REG(R300_GB_AA_CONFIG, 0); |
117 | OUT_ACCEL_REG(R300_GB_AA_CONFIG, 0); |
118 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
118 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
119 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
119 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
120 | OUT_ACCEL_REG(R300_GB_MSPOS0, ((8 << R300_MS_X0_SHIFT) | |
120 | OUT_ACCEL_REG(R300_GB_MSPOS0, ((8 << R300_MS_X0_SHIFT) | |
121 | (8 << R300_MS_Y0_SHIFT) | |
121 | (8 << R300_MS_Y0_SHIFT) | |
122 | (8 << R300_MS_X1_SHIFT) | |
122 | (8 << R300_MS_X1_SHIFT) | |
123 | (8 << R300_MS_Y1_SHIFT) | |
123 | (8 << R300_MS_Y1_SHIFT) | |
124 | (8 << R300_MS_X2_SHIFT) | |
124 | (8 << R300_MS_X2_SHIFT) | |
125 | (8 << R300_MS_Y2_SHIFT) | |
125 | (8 << R300_MS_Y2_SHIFT) | |
126 | (8 << R300_MSBD0_Y_SHIFT) | |
126 | (8 << R300_MSBD0_Y_SHIFT) | |
127 | (7 << R300_MSBD0_X_SHIFT))); |
127 | (7 << R300_MSBD0_X_SHIFT))); |
128 | OUT_ACCEL_REG(R300_GB_MSPOS1, ((8 << R300_MS_X3_SHIFT) | |
128 | OUT_ACCEL_REG(R300_GB_MSPOS1, ((8 << R300_MS_X3_SHIFT) | |
129 | (8 << R300_MS_Y3_SHIFT) | |
129 | (8 << R300_MS_Y3_SHIFT) | |
130 | (8 << R300_MS_X4_SHIFT) | |
130 | (8 << R300_MS_X4_SHIFT) | |
131 | (8 << R300_MS_Y4_SHIFT) | |
131 | (8 << R300_MS_Y4_SHIFT) | |
132 | (8 << R300_MS_X5_SHIFT) | |
132 | (8 << R300_MS_X5_SHIFT) | |
133 | (8 << R300_MS_Y5_SHIFT) | |
133 | (8 << R300_MS_Y5_SHIFT) | |
134 | (8 << R300_MSBD1_SHIFT))); |
134 | (8 << R300_MSBD1_SHIFT))); |
135 | FINISH_ACCEL(); |
135 | FINISH_ACCEL(); |
136 | 136 | ||
137 | BEGIN_ACCEL(5); |
137 | BEGIN_ACCEL(5); |
138 | OUT_ACCEL_REG(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); |
138 | OUT_ACCEL_REG(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); |
139 | OUT_ACCEL_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); |
139 | OUT_ACCEL_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); |
140 | OUT_ACCEL_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST | |
140 | OUT_ACCEL_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST | |
141 | R300_COLOR_ROUND_NEAREST)); |
141 | R300_COLOR_ROUND_NEAREST)); |
142 | OUT_ACCEL_REG(R300_GA_COLOR_CONTROL, (R300_RGB0_SHADING_GOURAUD | |
142 | OUT_ACCEL_REG(R300_GA_COLOR_CONTROL, (R300_RGB0_SHADING_GOURAUD | |
143 | R300_ALPHA0_SHADING_GOURAUD | |
143 | R300_ALPHA0_SHADING_GOURAUD | |
144 | R300_RGB1_SHADING_GOURAUD | |
144 | R300_RGB1_SHADING_GOURAUD | |
145 | R300_ALPHA1_SHADING_GOURAUD | |
145 | R300_ALPHA1_SHADING_GOURAUD | |
146 | R300_RGB2_SHADING_GOURAUD | |
146 | R300_RGB2_SHADING_GOURAUD | |
147 | R300_ALPHA2_SHADING_GOURAUD | |
147 | R300_ALPHA2_SHADING_GOURAUD | |
148 | R300_RGB3_SHADING_GOURAUD | |
148 | R300_RGB3_SHADING_GOURAUD | |
149 | R300_ALPHA3_SHADING_GOURAUD)); |
149 | R300_ALPHA3_SHADING_GOURAUD)); |
150 | OUT_ACCEL_REG(R300_GA_OFFSET, 0); |
150 | OUT_ACCEL_REG(R300_GA_OFFSET, 0); |
151 | FINISH_ACCEL(); |
151 | FINISH_ACCEL(); |
152 | 152 | ||
153 | BEGIN_ACCEL(5); |
153 | BEGIN_ACCEL(5); |
154 | OUT_ACCEL_REG(R300_SU_TEX_WRAP, 0); |
154 | OUT_ACCEL_REG(R300_SU_TEX_WRAP, 0); |
155 | OUT_ACCEL_REG(R300_SU_POLY_OFFSET_ENABLE, 0); |
155 | OUT_ACCEL_REG(R300_SU_POLY_OFFSET_ENABLE, 0); |
156 | OUT_ACCEL_REG(R300_SU_CULL_MODE, R300_FACE_NEG); |
156 | OUT_ACCEL_REG(R300_SU_CULL_MODE, R300_FACE_NEG); |
157 | OUT_ACCEL_REG(R300_SU_DEPTH_SCALE, 0x4b7fffff); |
157 | OUT_ACCEL_REG(R300_SU_DEPTH_SCALE, 0x4b7fffff); |
158 | OUT_ACCEL_REG(R300_SU_DEPTH_OFFSET, 0); |
158 | OUT_ACCEL_REG(R300_SU_DEPTH_OFFSET, 0); |
159 | FINISH_ACCEL(); |
159 | FINISH_ACCEL(); |
160 | 160 | ||
161 | /* setup the VAP */ |
161 | /* setup the VAP */ |
162 | if (rhdPtr->has_tcl) |
162 | if (rhdPtr->has_tcl) |
163 | vap_cntl = ((5 << R300_PVS_NUM_SLOTS_SHIFT) | |
163 | vap_cntl = ((5 << R300_PVS_NUM_SLOTS_SHIFT) | |
164 | (5 << R300_PVS_NUM_CNTLRS_SHIFT) | |
164 | (5 << R300_PVS_NUM_CNTLRS_SHIFT) | |
165 | (9 << R300_VF_MAX_VTX_NUM_SHIFT)); |
165 | (9 << R300_VF_MAX_VTX_NUM_SHIFT)); |
166 | else |
166 | else |
167 | vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | |
167 | vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | |
168 | (5 << R300_PVS_NUM_CNTLRS_SHIFT) | |
168 | (5 << R300_PVS_NUM_CNTLRS_SHIFT) | |
169 | (5 << R300_VF_MAX_VTX_NUM_SHIFT)); |
169 | (5 << R300_VF_MAX_VTX_NUM_SHIFT)); |
170 | 170 | ||
171 | if (rhdPtr->ChipSet == RHD_FAMILY_RV515) |
171 | if (rhdPtr->ChipSet == RHD_FAMILY_RV515) |
172 | vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT); |
172 | vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT); |
173 | else if ((rhdPtr->ChipSet == RHD_FAMILY_RV530) || |
173 | else if ((rhdPtr->ChipSet == RHD_FAMILY_RV530) || |
174 | (rhdPtr->ChipSet == RHD_FAMILY_RV560)) |
174 | (rhdPtr->ChipSet == RHD_FAMILY_RV560)) |
175 | vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT); |
175 | vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT); |
176 | else if (rhdPtr->ChipSet == RHD_FAMILY_R420) |
176 | else if (rhdPtr->ChipSet == RHD_FAMILY_R420) |
177 | vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT); |
177 | vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT); |
178 | else if ((rhdPtr->ChipSet == RHD_FAMILY_R520) || |
178 | else if ((rhdPtr->ChipSet == RHD_FAMILY_R520) || |
179 | (rhdPtr->ChipSet == RHD_FAMILY_R580) || |
179 | (rhdPtr->ChipSet == RHD_FAMILY_R580) || |
180 | (rhdPtr->ChipSet == RHD_FAMILY_RV570)) |
180 | (rhdPtr->ChipSet == RHD_FAMILY_RV570)) |
181 | vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT); |
181 | vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT); |
182 | else |
182 | else |
183 | vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT); |
183 | vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT); |
184 | 184 | ||
185 | if (rhdPtr->has_tcl) |
185 | if (rhdPtr->has_tcl) |
186 | BEGIN_ACCEL(15); |
186 | BEGIN_ACCEL(15); |
187 | else |
187 | else |
188 | BEGIN_ACCEL(9); |
188 | BEGIN_ACCEL(9); |
189 | OUT_ACCEL_REG(R300_VAP_VTX_STATE_CNTL, 0); |
189 | OUT_ACCEL_REG(R300_VAP_VTX_STATE_CNTL, 0); |
190 | OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); |
190 | OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); |
191 | 191 | ||
192 | if (rhdPtr->has_tcl) |
192 | if (rhdPtr->has_tcl) |
193 | OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0); |
193 | OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0); |
194 | else |
194 | else |
195 | OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS); |
195 | OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS); |
196 | OUT_ACCEL_REG(R300_VAP_CNTL, vap_cntl); |
196 | OUT_ACCEL_REG(R300_VAP_CNTL, vap_cntl); |
197 | OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); |
197 | OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); |
198 | OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT); |
198 | OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT); |
199 | OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0); |
199 | OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0); |
200 | 200 | ||
201 | OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, |
201 | OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, |
202 | ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) | |
202 | ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) | |
203 | (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | |
203 | (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | |
204 | (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) | |
204 | (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) | |
205 | (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) | |
205 | (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) | |
206 | ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
206 | ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
207 | << R300_WRITE_ENA_0_SHIFT) | |
207 | << R300_WRITE_ENA_0_SHIFT) | |
208 | (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | |
208 | (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | |
209 | (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | |
209 | (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | |
210 | (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) | |
210 | (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) | |
211 | (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) | |
211 | (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) | |
212 | ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
212 | ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
213 | << R300_WRITE_ENA_1_SHIFT))); |
213 | << R300_WRITE_ENA_1_SHIFT))); |
214 | OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, |
214 | OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, |
215 | ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) | |
215 | ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) | |
216 | (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) | |
216 | (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) | |
217 | (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) | |
217 | (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) | |
218 | (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) | |
218 | (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) | |
219 | ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
219 | ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
220 | << R300_WRITE_ENA_2_SHIFT))); |
220 | << R300_WRITE_ENA_2_SHIFT))); |
221 | 221 | ||
222 | if (rhdPtr->has_tcl) { |
222 | if (rhdPtr->has_tcl) { |
223 | OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0); |
223 | OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0); |
224 | OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000); |
224 | OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000); |
225 | OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000); |
225 | OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000); |
226 | OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000); |
226 | OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000); |
227 | OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000); |
227 | OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000); |
228 | OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE); |
228 | OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE); |
229 | } |
229 | } |
230 | FINISH_ACCEL(); |
230 | FINISH_ACCEL(); |
231 | 231 | ||
232 | /* pre-load the vertex shaders */ |
232 | /* pre-load the vertex shaders */ |
233 | if (rhdPtr->has_tcl) { |
233 | if (rhdPtr->has_tcl) { |
234 | /* exa mask shader program */ |
234 | /* exa mask shader program */ |
235 | BEGIN_ACCEL(13); |
235 | BEGIN_ACCEL(13); |
236 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0); |
236 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0); |
237 | /* PVS inst 0 */ |
237 | /* PVS inst 0 */ |
238 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
238 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
239 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
239 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
240 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
240 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
241 | R300_PVS_DST_OFFSET(0) | |
241 | R300_PVS_DST_OFFSET(0) | |
242 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
242 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
243 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
243 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
244 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
244 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
245 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
245 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
246 | R300_PVS_SRC_OFFSET(0) | |
246 | R300_PVS_SRC_OFFSET(0) | |
247 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
247 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
248 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
248 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
249 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
249 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
250 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
250 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
251 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
251 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
252 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
252 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
253 | R300_PVS_SRC_OFFSET(0) | |
253 | R300_PVS_SRC_OFFSET(0) | |
254 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
254 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
255 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
255 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
256 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
256 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
257 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
257 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
258 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
258 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
259 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
259 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
260 | R300_PVS_SRC_OFFSET(0) | |
260 | R300_PVS_SRC_OFFSET(0) | |
261 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
261 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
262 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
262 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
263 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
263 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
264 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
264 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
265 | 265 | ||
266 | /* PVS inst 1 */ |
266 | /* PVS inst 1 */ |
267 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
267 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
268 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
268 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
269 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
269 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
270 | R300_PVS_DST_OFFSET(1) | |
270 | R300_PVS_DST_OFFSET(1) | |
271 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
271 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
272 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
272 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
273 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
273 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
274 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
274 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
275 | R300_PVS_SRC_OFFSET(6) | |
275 | R300_PVS_SRC_OFFSET(6) | |
276 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
276 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
277 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
277 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
278 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
278 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
279 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
279 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
280 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
280 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
281 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
281 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
282 | R300_PVS_SRC_OFFSET(6) | |
282 | R300_PVS_SRC_OFFSET(6) | |
283 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
283 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
284 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
284 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
285 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
285 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
286 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
286 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
287 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
287 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
288 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
288 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
289 | R300_PVS_SRC_OFFSET(6) | |
289 | R300_PVS_SRC_OFFSET(6) | |
290 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
290 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
291 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
291 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
292 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
292 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
293 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
293 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
294 | 294 | ||
295 | /* PVS inst 2 */ |
295 | /* PVS inst 2 */ |
296 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
296 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
297 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
297 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
298 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
298 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
299 | R300_PVS_DST_OFFSET(2) | |
299 | R300_PVS_DST_OFFSET(2) | |
300 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
300 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
301 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
301 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
302 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
302 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
303 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
303 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
304 | R300_PVS_SRC_OFFSET(7) | |
304 | R300_PVS_SRC_OFFSET(7) | |
305 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
305 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
306 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
306 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
307 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
307 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
308 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
308 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
309 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
309 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
310 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
310 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
311 | R300_PVS_SRC_OFFSET(7) | |
311 | R300_PVS_SRC_OFFSET(7) | |
312 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
312 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
313 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
313 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
314 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
314 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
315 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
315 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
316 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
316 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
317 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
317 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
318 | R300_PVS_SRC_OFFSET(7) | |
318 | R300_PVS_SRC_OFFSET(7) | |
319 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
319 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
320 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
320 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
321 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
321 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
322 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
322 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
323 | FINISH_ACCEL(); |
323 | FINISH_ACCEL(); |
324 | 324 | ||
325 | BEGIN_ACCEL(9); |
325 | BEGIN_ACCEL(9); |
326 | /* exa no mask instruction */ |
326 | /* exa no mask instruction */ |
327 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 3); |
327 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 3); |
328 | /* PVS inst 0 */ |
328 | /* PVS inst 0 */ |
329 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
329 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
330 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
330 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
331 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
331 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
332 | R300_PVS_DST_OFFSET(0) | |
332 | R300_PVS_DST_OFFSET(0) | |
333 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
333 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
334 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
334 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
335 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
335 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
336 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
336 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
337 | R300_PVS_SRC_OFFSET(0) | |
337 | R300_PVS_SRC_OFFSET(0) | |
338 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
338 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
339 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
339 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
340 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
340 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
341 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
341 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
342 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
342 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
343 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
343 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
344 | R300_PVS_SRC_OFFSET(0) | |
344 | R300_PVS_SRC_OFFSET(0) | |
345 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
345 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
346 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
346 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
347 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
347 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
348 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
348 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
349 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
349 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
350 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
350 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
351 | R300_PVS_SRC_OFFSET(0) | |
351 | R300_PVS_SRC_OFFSET(0) | |
352 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
352 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
353 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
353 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
354 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
354 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
355 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
355 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
356 | 356 | ||
357 | /* PVS inst 1 */ |
357 | /* PVS inst 1 */ |
358 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
358 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
359 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
359 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
360 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
360 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
361 | R300_PVS_DST_OFFSET(1) | |
361 | R300_PVS_DST_OFFSET(1) | |
362 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
362 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
363 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
363 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
364 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
364 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
365 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
365 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
366 | R300_PVS_SRC_OFFSET(6) | |
366 | R300_PVS_SRC_OFFSET(6) | |
367 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
367 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
368 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
368 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
369 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
369 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
370 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
370 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
371 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
371 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
372 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
372 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
373 | R300_PVS_SRC_OFFSET(6) | |
373 | R300_PVS_SRC_OFFSET(6) | |
374 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
374 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
375 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
375 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
376 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
376 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
377 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
377 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
378 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
378 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
379 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
379 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
380 | R300_PVS_SRC_OFFSET(6) | |
380 | R300_PVS_SRC_OFFSET(6) | |
381 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
381 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
382 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
382 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
383 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
383 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
384 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
384 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
385 | FINISH_ACCEL(); |
385 | FINISH_ACCEL(); |
386 | 386 | ||
387 | /* Xv shader program */ |
387 | /* Xv shader program */ |
388 | BEGIN_ACCEL(9); |
388 | BEGIN_ACCEL(9); |
389 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 5); |
389 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 5); |
390 | 390 | ||
391 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
391 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
392 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
392 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
393 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
393 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
394 | R300_PVS_DST_OFFSET(0) | |
394 | R300_PVS_DST_OFFSET(0) | |
395 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
395 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
396 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
396 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
397 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
397 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
398 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
398 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
399 | R300_PVS_SRC_OFFSET(0) | |
399 | R300_PVS_SRC_OFFSET(0) | |
400 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
400 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
401 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
401 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
402 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
402 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
403 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
403 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
404 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
404 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
405 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
405 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
406 | R300_PVS_SRC_OFFSET(0) | |
406 | R300_PVS_SRC_OFFSET(0) | |
407 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
407 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
408 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
408 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
409 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
409 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
410 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
410 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
411 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
411 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
412 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
412 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
413 | R300_PVS_SRC_OFFSET(0) | |
413 | R300_PVS_SRC_OFFSET(0) | |
414 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
414 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
415 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
415 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
416 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
416 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
417 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
417 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
418 | 418 | ||
419 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
419 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
420 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
420 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
421 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
421 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
422 | R300_PVS_DST_OFFSET(1) | |
422 | R300_PVS_DST_OFFSET(1) | |
423 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
423 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
424 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
424 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
425 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
425 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
426 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
426 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
427 | R300_PVS_SRC_OFFSET(6) | |
427 | R300_PVS_SRC_OFFSET(6) | |
428 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
428 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
429 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
429 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
430 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
430 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
431 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
431 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
432 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
432 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
433 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
433 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
434 | R300_PVS_SRC_OFFSET(6) | |
434 | R300_PVS_SRC_OFFSET(6) | |
435 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
435 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
436 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
436 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
437 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
437 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
438 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
438 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
439 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
439 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
440 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
440 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
441 | R300_PVS_SRC_OFFSET(6) | |
441 | R300_PVS_SRC_OFFSET(6) | |
442 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
442 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
443 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
443 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
444 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
444 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
445 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
445 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
446 | FINISH_ACCEL(); |
446 | FINISH_ACCEL(); |
447 | } |
447 | } |
448 | 448 | ||
449 | /* pre-load the RS instructions */ |
449 | /* pre-load the RS instructions */ |
450 | BEGIN_ACCEL(4); |
450 | BEGIN_ACCEL(4); |
451 | if (IS_R300_3D) { |
451 | if (IS_R300_3D) { |
452 | /* rasterizer source table |
452 | /* rasterizer source table |
453 | * R300_RS_TEX_PTR is the offset into the input RS stream |
453 | * R300_RS_TEX_PTR is the offset into the input RS stream |
454 | * 0,1 are tex0 |
454 | * 0,1 are tex0 |
455 | * 2,3 are tex1 |
455 | * 2,3 are tex1 |
456 | */ |
456 | */ |
457 | OUT_ACCEL_REG(R300_RS_IP_0, |
457 | OUT_ACCEL_REG(R300_RS_IP_0, |
458 | (R300_RS_TEX_PTR(0) | |
458 | (R300_RS_TEX_PTR(0) | |
459 | R300_RS_SEL_S(R300_RS_SEL_C0) | |
459 | R300_RS_SEL_S(R300_RS_SEL_C0) | |
460 | R300_RS_SEL_T(R300_RS_SEL_C1) | |
460 | R300_RS_SEL_T(R300_RS_SEL_C1) | |
461 | R300_RS_SEL_R(R300_RS_SEL_K0) | |
461 | R300_RS_SEL_R(R300_RS_SEL_K0) | |
462 | R300_RS_SEL_Q(R300_RS_SEL_K1))); |
462 | R300_RS_SEL_Q(R300_RS_SEL_K1))); |
463 | OUT_ACCEL_REG(R300_RS_IP_1, |
463 | OUT_ACCEL_REG(R300_RS_IP_1, |
464 | (R300_RS_TEX_PTR(2) | |
464 | (R300_RS_TEX_PTR(2) | |
465 | R300_RS_SEL_S(R300_RS_SEL_C0) | |
465 | R300_RS_SEL_S(R300_RS_SEL_C0) | |
466 | R300_RS_SEL_T(R300_RS_SEL_C1) | |
466 | R300_RS_SEL_T(R300_RS_SEL_C1) | |
467 | R300_RS_SEL_R(R300_RS_SEL_K0) | |
467 | R300_RS_SEL_R(R300_RS_SEL_K0) | |
468 | R300_RS_SEL_Q(R300_RS_SEL_K1))); |
468 | R300_RS_SEL_Q(R300_RS_SEL_K1))); |
469 | /* src tex */ |
469 | /* src tex */ |
470 | /* R300_INST_TEX_ID - select the RS source table entry |
470 | /* R300_INST_TEX_ID - select the RS source table entry |
471 | * R300_INST_TEX_ADDR - the FS temp register for the texture data |
471 | * R300_INST_TEX_ADDR - the FS temp register for the texture data |
472 | */ |
472 | */ |
473 | OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) | |
473 | OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) | |
474 | R300_RS_INST_TEX_CN_WRITE | |
474 | R300_RS_INST_TEX_CN_WRITE | |
475 | R300_INST_TEX_ADDR(0))); |
475 | R300_INST_TEX_ADDR(0))); |
476 | /* mask tex */ |
476 | /* mask tex */ |
477 | OUT_ACCEL_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) | |
477 | OUT_ACCEL_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) | |
478 | R300_RS_INST_TEX_CN_WRITE | |
478 | R300_RS_INST_TEX_CN_WRITE | |
479 | R300_INST_TEX_ADDR(1))); |
479 | R300_INST_TEX_ADDR(1))); |
480 | 480 | ||
481 | } else { |
481 | } else { |
482 | /* rasterizer source table |
482 | /* rasterizer source table |
483 | * R300_RS_TEX_PTR is the offset into the input RS stream |
483 | * R300_RS_TEX_PTR is the offset into the input RS stream |
484 | * 0,1 are tex0 |
484 | * 0,1 are tex0 |
485 | * 2,3 are tex1 |
485 | * 2,3 are tex1 |
486 | */ |
486 | */ |
487 | OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) | |
487 | OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) | |
488 | (1 << R500_RS_IP_TEX_PTR_T_SHIFT) | |
488 | (1 << R500_RS_IP_TEX_PTR_T_SHIFT) | |
489 | (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | |
489 | (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | |
490 | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); |
490 | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); |
491 | 491 | ||
492 | OUT_ACCEL_REG(R500_RS_IP_1, ((2 << R500_RS_IP_TEX_PTR_S_SHIFT) | |
492 | OUT_ACCEL_REG(R500_RS_IP_1, ((2 << R500_RS_IP_TEX_PTR_S_SHIFT) | |
493 | (3 << R500_RS_IP_TEX_PTR_T_SHIFT) | |
493 | (3 << R500_RS_IP_TEX_PTR_T_SHIFT) | |
494 | (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | |
494 | (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | |
495 | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); |
495 | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); |
496 | /* src tex */ |
496 | /* src tex */ |
497 | /* R500_RS_INST_TEX_ID_SHIFT - select the RS source table entry |
497 | /* R500_RS_INST_TEX_ID_SHIFT - select the RS source table entry |
498 | * R500_RS_INST_TEX_ADDR_SHIFT - the FS temp register for the texture data |
498 | * R500_RS_INST_TEX_ADDR_SHIFT - the FS temp register for the texture data |
499 | */ |
499 | */ |
500 | OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) | |
500 | OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) | |
501 | R500_RS_INST_TEX_CN_WRITE | |
501 | R500_RS_INST_TEX_CN_WRITE | |
502 | (0 << R500_RS_INST_TEX_ADDR_SHIFT))); |
502 | (0 << R500_RS_INST_TEX_ADDR_SHIFT))); |
503 | /* mask tex */ |
503 | /* mask tex */ |
504 | OUT_ACCEL_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) | |
504 | OUT_ACCEL_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) | |
505 | R500_RS_INST_TEX_CN_WRITE | |
505 | R500_RS_INST_TEX_CN_WRITE | |
506 | (1 << R500_RS_INST_TEX_ADDR_SHIFT))); |
506 | (1 << R500_RS_INST_TEX_ADDR_SHIFT))); |
507 | } |
507 | } |
508 | FINISH_ACCEL(); |
508 | FINISH_ACCEL(); |
509 | 509 | ||
510 | /* pre-load FS tex instructions */ |
510 | /* pre-load FS tex instructions */ |
511 | if (IS_R300_3D) { |
511 | if (IS_R300_3D) { |
512 | BEGIN_ACCEL(2); |
512 | BEGIN_ACCEL(2); |
513 | /* tex inst for src texture */ |
513 | /* tex inst for src texture */ |
514 | OUT_ACCEL_REG(R300_US_TEX_INST_0, |
514 | OUT_ACCEL_REG(R300_US_TEX_INST_0, |
515 | (R300_TEX_SRC_ADDR(0) | |
515 | (R300_TEX_SRC_ADDR(0) | |
516 | R300_TEX_DST_ADDR(0) | |
516 | R300_TEX_DST_ADDR(0) | |
517 | R300_TEX_ID(0) | |
517 | R300_TEX_ID(0) | |
518 | R300_TEX_INST(R300_TEX_INST_LD))); |
518 | R300_TEX_INST(R300_TEX_INST_LD))); |
519 | 519 | ||
520 | /* tex inst for mask texture */ |
520 | /* tex inst for mask texture */ |
521 | OUT_ACCEL_REG(R300_US_TEX_INST_1, |
521 | OUT_ACCEL_REG(R300_US_TEX_INST_1, |
522 | (R300_TEX_SRC_ADDR(1) | |
522 | (R300_TEX_SRC_ADDR(1) | |
523 | R300_TEX_DST_ADDR(1) | |
523 | R300_TEX_DST_ADDR(1) | |
524 | R300_TEX_ID(1) | |
524 | R300_TEX_ID(1) | |
525 | R300_TEX_INST(R300_TEX_INST_LD))); |
525 | R300_TEX_INST(R300_TEX_INST_LD))); |
526 | FINISH_ACCEL(); |
526 | FINISH_ACCEL(); |
527 | } |
527 | } |
528 | 528 | ||
529 | if (IS_R300_3D) { |
529 | if (IS_R300_3D) { |
530 | BEGIN_ACCEL(9); |
530 | BEGIN_ACCEL(9); |
531 | OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX); |
531 | OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX); |
532 | OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */ |
532 | OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */ |
533 | OUT_ACCEL_REG(R300_US_CODE_ADDR_0, |
533 | OUT_ACCEL_REG(R300_US_CODE_ADDR_0, |
534 | (R300_ALU_START(0) | |
534 | (R300_ALU_START(0) | |
535 | R300_ALU_SIZE(0) | |
535 | R300_ALU_SIZE(0) | |
536 | R300_TEX_START(0) | |
536 | R300_TEX_START(0) | |
537 | R300_TEX_SIZE(0))); |
537 | R300_TEX_SIZE(0))); |
538 | OUT_ACCEL_REG(R300_US_CODE_ADDR_1, |
538 | OUT_ACCEL_REG(R300_US_CODE_ADDR_1, |
539 | (R300_ALU_START(0) | |
539 | (R300_ALU_START(0) | |
540 | R300_ALU_SIZE(0) | |
540 | R300_ALU_SIZE(0) | |
541 | R300_TEX_START(0) | |
541 | R300_TEX_START(0) | |
542 | R300_TEX_SIZE(0))); |
542 | R300_TEX_SIZE(0))); |
543 | OUT_ACCEL_REG(R300_US_CODE_ADDR_2, |
543 | OUT_ACCEL_REG(R300_US_CODE_ADDR_2, |
544 | (R300_ALU_START(0) | |
544 | (R300_ALU_START(0) | |
545 | R300_ALU_SIZE(0) | |
545 | R300_ALU_SIZE(0) | |
546 | R300_TEX_START(0) | |
546 | R300_TEX_START(0) | |
547 | R300_TEX_SIZE(0))); |
547 | R300_TEX_SIZE(0))); |
548 | } else { |
548 | } else { |
549 | BEGIN_ACCEL(7); |
549 | BEGIN_ACCEL(7); |
550 | OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); |
550 | OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); |
551 | OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */ |
551 | OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */ |
552 | OUT_ACCEL_REG(R500_US_FC_CTRL, 0); |
552 | OUT_ACCEL_REG(R500_US_FC_CTRL, 0); |
553 | } |
553 | } |
554 | OUT_ACCEL_REG(R300_US_W_FMT, 0); |
554 | OUT_ACCEL_REG(R300_US_W_FMT, 0); |
555 | OUT_ACCEL_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED | |
555 | OUT_ACCEL_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED | |
556 | R300_OUT_FMT_C0_SEL_BLUE | |
556 | R300_OUT_FMT_C0_SEL_BLUE | |
557 | R300_OUT_FMT_C1_SEL_GREEN | |
557 | R300_OUT_FMT_C1_SEL_GREEN | |
558 | R300_OUT_FMT_C2_SEL_RED | |
558 | R300_OUT_FMT_C2_SEL_RED | |
559 | R300_OUT_FMT_C3_SEL_ALPHA)); |
559 | R300_OUT_FMT_C3_SEL_ALPHA)); |
560 | OUT_ACCEL_REG(R300_US_OUT_FMT_2, (R300_OUT_FMT_UNUSED | |
560 | OUT_ACCEL_REG(R300_US_OUT_FMT_2, (R300_OUT_FMT_UNUSED | |
561 | R300_OUT_FMT_C0_SEL_BLUE | |
561 | R300_OUT_FMT_C0_SEL_BLUE | |
562 | R300_OUT_FMT_C1_SEL_GREEN | |
562 | R300_OUT_FMT_C1_SEL_GREEN | |
563 | R300_OUT_FMT_C2_SEL_RED | |
563 | R300_OUT_FMT_C2_SEL_RED | |
564 | R300_OUT_FMT_C3_SEL_ALPHA)); |
564 | R300_OUT_FMT_C3_SEL_ALPHA)); |
565 | OUT_ACCEL_REG(R300_US_OUT_FMT_3, (R300_OUT_FMT_UNUSED | |
565 | OUT_ACCEL_REG(R300_US_OUT_FMT_3, (R300_OUT_FMT_UNUSED | |
566 | R300_OUT_FMT_C0_SEL_BLUE | |
566 | R300_OUT_FMT_C0_SEL_BLUE | |
567 | R300_OUT_FMT_C1_SEL_GREEN | |
567 | R300_OUT_FMT_C1_SEL_GREEN | |
568 | R300_OUT_FMT_C2_SEL_RED | |
568 | R300_OUT_FMT_C2_SEL_RED | |
569 | R300_OUT_FMT_C3_SEL_ALPHA)); |
569 | R300_OUT_FMT_C3_SEL_ALPHA)); |
570 | FINISH_ACCEL(); |
570 | FINISH_ACCEL(); |
571 | 571 | ||
572 | 572 | ||
573 | BEGIN_ACCEL(3); |
573 | BEGIN_ACCEL(3); |
574 | OUT_ACCEL_REG(R300_FG_DEPTH_SRC, 0); |
574 | OUT_ACCEL_REG(R300_FG_DEPTH_SRC, 0); |
575 | OUT_ACCEL_REG(R300_FG_FOG_BLEND, 0); |
575 | OUT_ACCEL_REG(R300_FG_FOG_BLEND, 0); |
576 | OUT_ACCEL_REG(R300_FG_ALPHA_FUNC, 0); |
576 | OUT_ACCEL_REG(R300_FG_ALPHA_FUNC, 0); |
577 | FINISH_ACCEL(); |
577 | FINISH_ACCEL(); |
578 | 578 | ||
579 | BEGIN_ACCEL(13); |
579 | BEGIN_ACCEL(13); |
580 | OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0); |
580 | OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0); |
581 | OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0); |
581 | OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0); |
582 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
582 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
583 | OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0); |
583 | OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0); |
584 | OUT_ACCEL_REG(R300_RB3D_ZCNTL, 0); |
584 | OUT_ACCEL_REG(R300_RB3D_ZCNTL, 0); |
585 | OUT_ACCEL_REG(R300_RB3D_ZTOP, 0); |
585 | OUT_ACCEL_REG(R300_RB3D_ZTOP, 0); |
586 | OUT_ACCEL_REG(R300_RB3D_ROPCNTL, 0); |
586 | OUT_ACCEL_REG(R300_RB3D_ROPCNTL, 0); |
587 | 587 | ||
588 | OUT_ACCEL_REG(R300_RB3D_AARESOLVE_CTL, 0); |
588 | OUT_ACCEL_REG(R300_RB3D_AARESOLVE_CTL, 0); |
589 | OUT_ACCEL_REG(R300_RB3D_COLOR_CHANNEL_MASK, (R300_BLUE_MASK_EN | |
589 | OUT_ACCEL_REG(R300_RB3D_COLOR_CHANNEL_MASK, (R300_BLUE_MASK_EN | |
590 | R300_GREEN_MASK_EN | |
590 | R300_GREEN_MASK_EN | |
591 | R300_RED_MASK_EN | |
591 | R300_RED_MASK_EN | |
592 | R300_ALPHA_MASK_EN)); |
592 | R300_ALPHA_MASK_EN)); |
593 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
593 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
594 | OUT_ACCEL_REG(R300_RB3D_CCTL, 0); |
594 | OUT_ACCEL_REG(R300_RB3D_CCTL, 0); |
595 | OUT_ACCEL_REG(R300_RB3D_DITHER_CTL, 0); |
595 | OUT_ACCEL_REG(R300_RB3D_DITHER_CTL, 0); |
596 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
596 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
597 | FINISH_ACCEL(); |
597 | FINISH_ACCEL(); |
598 | 598 | ||
599 | BEGIN_ACCEL(7); |
599 | BEGIN_ACCEL(7); |
600 | OUT_ACCEL_REG(R300_SC_EDGERULE, 0xA5294A5); |
600 | OUT_ACCEL_REG(R300_SC_EDGERULE, 0xA5294A5); |
601 | OUT_ACCEL_REG(R300_SC_SCISSOR0, ((0 << R300_SCISSOR_X_SHIFT) | |
601 | OUT_ACCEL_REG(R300_SC_SCISSOR0, ((0 << R300_SCISSOR_X_SHIFT) | |
602 | (0 << R300_SCISSOR_Y_SHIFT))); |
602 | (0 << R300_SCISSOR_Y_SHIFT))); |
603 | OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) | |
603 | OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) | |
604 | (8191 << R300_SCISSOR_Y_SHIFT))); |
604 | (8191 << R300_SCISSOR_Y_SHIFT))); |
605 | 605 | ||
606 | if (IS_R300_3D) { |
606 | if (IS_R300_3D) { |
607 | /* clip has offset 1440 */ |
607 | /* clip has offset 1440 */ |
608 | OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1088 << R300_CLIP_X_SHIFT) | |
608 | OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1088 << R300_CLIP_X_SHIFT) | |
609 | (1088 << R300_CLIP_Y_SHIFT))); |
609 | (1088 << R300_CLIP_Y_SHIFT))); |
610 | OUT_ACCEL_REG(R300_SC_CLIP_0_B, (((1080 + 2920) << R300_CLIP_X_SHIFT) | |
610 | OUT_ACCEL_REG(R300_SC_CLIP_0_B, (((1080 + 2920) << R300_CLIP_X_SHIFT) | |
611 | ((1080 + 2920) << R300_CLIP_Y_SHIFT))); |
611 | ((1080 + 2920) << R300_CLIP_Y_SHIFT))); |
612 | } else { |
612 | } else { |
613 | OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) | |
613 | OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) | |
614 | (0 << R300_CLIP_Y_SHIFT))); |
614 | (0 << R300_CLIP_Y_SHIFT))); |
615 | OUT_ACCEL_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) | |
615 | OUT_ACCEL_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) | |
616 | (4080 << R300_CLIP_Y_SHIFT))); |
616 | (4080 << R300_CLIP_Y_SHIFT))); |
617 | } |
617 | } |
618 | OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA); |
618 | OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA); |
619 | OUT_ACCEL_REG(R300_SC_SCREENDOOR, 0xffffff); |
619 | OUT_ACCEL_REG(R300_SC_SCREENDOOR, 0xffffff); |
620 | FINISH_ACCEL(); |
620 | FINISH_ACCEL(); |
621 | } else if ((rhdPtr->ChipSet == RHD_FAMILY_RV250) || |
621 | } else if ((rhdPtr->ChipSet == RHD_FAMILY_RV250) || |
622 | (rhdPtr->ChipSet == RHD_FAMILY_RV280) || |
622 | (rhdPtr->ChipSet == RHD_FAMILY_RV280) || |
623 | (rhdPtr->ChipSet == RHD_FAMILY_RS300) || |
623 | (rhdPtr->ChipSet == RHD_FAMILY_RS300) || |
624 | (rhdPtr->ChipSet == RHD_FAMILY_R200)) { |
624 | (rhdPtr->ChipSet == RHD_FAMILY_R200)) { |
625 | 625 | ||
626 | BEGIN_ACCEL(7); |
626 | BEGIN_ACCEL(7); |
627 | if (rhdPtr->ChipSet == RHD_FAMILY_RS300) { |
627 | if (rhdPtr->ChipSet == RHD_FAMILY_RS300) { |
628 | OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS); |
628 | OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS); |
629 | } else { |
629 | } else { |
630 | OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0); |
630 | OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0); |
631 | } |
631 | } |
632 | OUT_ACCEL_REG(R200_PP_CNTL_X, 0); |
632 | OUT_ACCEL_REG(R200_PP_CNTL_X, 0); |
633 | OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0); |
633 | OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0); |
634 | OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0); |
634 | OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0); |
635 | OUT_ACCEL_REG(R200_RE_CNTL, 0x0); |
635 | OUT_ACCEL_REG(R200_RE_CNTL, 0x0); |
636 | OUT_ACCEL_REG(R200_SE_VTE_CNTL, 0); |
636 | OUT_ACCEL_REG(R200_SE_VTE_CNTL, 0); |
637 | OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE | |
637 | OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE | |
638 | R200_VAP_VF_MAX_VTX_NUM); |
638 | R200_VAP_VF_MAX_VTX_NUM); |
639 | FINISH_ACCEL(); |
639 | FINISH_ACCEL(); |
640 | 640 | ||
641 | BEGIN_ACCEL(5); |
641 | BEGIN_ACCEL(5); |
642 | OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0); |
642 | OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0); |
643 | OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); |
643 | OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); |
644 | OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); |
644 | OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); |
645 | OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); |
645 | OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); |
646 | OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | |
646 | OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | |
647 | RADEON_BFACE_SOLID | |
647 | RADEON_BFACE_SOLID | |
648 | RADEON_FFACE_SOLID | |
648 | RADEON_FFACE_SOLID | |
649 | RADEON_VTX_PIX_CENTER_OGL | |
649 | RADEON_VTX_PIX_CENTER_OGL | |
650 | RADEON_ROUND_MODE_ROUND | |
650 | RADEON_ROUND_MODE_ROUND | |
651 | RADEON_ROUND_PREC_4TH_PIX)); |
651 | RADEON_ROUND_PREC_4TH_PIX)); |
652 | FINISH_ACCEL(); |
652 | FINISH_ACCEL(); |
653 | } else { |
653 | } else { |
654 | BEGIN_ACCEL(2); |
654 | BEGIN_ACCEL(2); |
655 | if ((rhdPtr->ChipSet == RHD_FAMILY_RADEON) || |
655 | if ((rhdPtr->ChipSet == RHD_FAMILY_RADEON) || |
656 | (rhdPtr->ChipSet == RHD_FAMILY_RV200)) |
656 | (rhdPtr->ChipSet == RHD_FAMILY_RV200)) |
657 | OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, 0); |
657 | OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, 0); |
658 | else |
658 | else |
659 | OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS); |
659 | OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS); |
660 | OUT_ACCEL_REG(RADEON_SE_COORD_FMT, |
660 | OUT_ACCEL_REG(RADEON_SE_COORD_FMT, |
661 | RADEON_VTX_XY_PRE_MULT_1_OVER_W0 | |
661 | RADEON_VTX_XY_PRE_MULT_1_OVER_W0 | |
662 | RADEON_VTX_ST0_NONPARAMETRIC | |
662 | RADEON_VTX_ST0_NONPARAMETRIC | |
663 | RADEON_VTX_ST1_NONPARAMETRIC | |
663 | RADEON_VTX_ST1_NONPARAMETRIC | |
664 | RADEON_TEX1_W_ROUTING_USE_W0); |
664 | RADEON_TEX1_W_ROUTING_USE_W0); |
665 | FINISH_ACCEL(); |
665 | FINISH_ACCEL(); |
666 | 666 | ||
667 | BEGIN_ACCEL(5); |
667 | BEGIN_ACCEL(5); |
668 | OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0); |
668 | OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0); |
669 | OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); |
669 | OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); |
670 | OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); |
670 | OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); |
671 | OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); |
671 | OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); |
672 | OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | |
672 | OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | |
673 | RADEON_BFACE_SOLID | |
673 | RADEON_BFACE_SOLID | |
674 | RADEON_FFACE_SOLID | |
674 | RADEON_FFACE_SOLID | |
675 | RADEON_VTX_PIX_CENTER_OGL | |
675 | RADEON_VTX_PIX_CENTER_OGL | |
676 | RADEON_ROUND_MODE_ROUND | |
676 | RADEON_ROUND_MODE_ROUND | |
677 | RADEON_ROUND_PREC_4TH_PIX)); |
677 | RADEON_ROUND_PREC_4TH_PIX)); |
678 | FINISH_ACCEL(); |
678 | FINISH_ACCEL(); |
679 | } |
679 | } |
680 | 680 | ||
681 | } |
681 | } |
682 | 682 | ||
683 | static Bool R300TextureSetup(int w, int h, int unit) |
683 | static Bool R300TextureSetup(int w, int h, int unit) |
684 | { |
684 | { |
685 | //RINFO_FROM_SCREEN(pPix->drawable.pScreen); |
685 | //RINFO_FROM_SCREEN(pPix->drawable.pScreen); |
686 | u32_t txfilter, txformat0, txformat1, txoffset, txpitch; |
686 | u32_t txfilter, txformat0, txformat1, txoffset, txpitch; |
687 | // int w = pPict->pDrawable->width; |
687 | // int w = pPict->pDrawable->width; |
688 | // int h = pPict->pDrawable->height; |
688 | // int h = pPict->pDrawable->height; |
689 | int i, pixel_shift; |
689 | int i, pixel_shift; |
690 | 690 | ||
691 | //ACCEL_PREAMBLE(); |
691 | //ACCEL_PREAMBLE(); |
692 | 692 | ||
693 | //TRACE; |
693 | //TRACE; |
694 | 694 | ||
695 | //txpitch = exaGetPixmapPitch(pPix); |
695 | //txpitch = exaGetPixmapPitch(pPix); |
696 | txpitch = rhd.displayWidth * 4; |
696 | txpitch = rhd.displayWidth * 4; |
697 | 697 | ||
698 | // txoffset = exaGetPixmapOffset(pPix) + info->fbLocation + pScrn->fbOffset; |
698 | // txoffset = exaGetPixmapOffset(pPix) + info->fbLocation + pScrn->fbOffset; |
699 | txoffset = rhd.FbIntAddress + rhd.FbScanoutStart; |
699 | txoffset = rhd.FbIntAddress + rhd.FbScanoutStart; |
700 | 700 | ||
701 | if ((txoffset & 0x1f) != 0) |
701 | if ((txoffset & 0x1f) != 0) |
702 | dbgprintf("Bad texture offset 0x%x\n", (int)txoffset); |
702 | dbgprintf("Bad texture offset 0x%x\n", (int)txoffset); |
703 | if ((txpitch & 0x1f) != 0) |
703 | if ((txpitch & 0x1f) != 0) |
704 | dbgprintf("Bad texture pitch 0x%x\n", (int)txpitch); |
704 | dbgprintf("Bad texture pitch 0x%x\n", (int)txpitch); |
705 | 705 | ||
706 | /* TXPITCH = pixels (texels) per line - 1 */ |
706 | /* TXPITCH = pixels (texels) per line - 1 */ |
707 | pixel_shift = 32 >> 4; |
707 | pixel_shift = 32 >> 4; |
708 | txpitch >>= pixel_shift; |
708 | txpitch >>= pixel_shift; |
709 | txpitch -= 1; |
709 | txpitch -= 1; |
710 | 710 | ||
711 | // if (RADEONPixmapIsColortiled(pPix)) |
711 | // if (RADEONPixmapIsColortiled(pPix)) |
712 | // txoffset |= R300_MACRO_TILE; |
712 | // txoffset |= R300_MACRO_TILE; |
713 | 713 | ||
714 | // for (i = 0; i < sizeof(R300TexFormats) / sizeof(R300TexFormats[0]); i++) |
714 | // for (i = 0; i < sizeof(R300TexFormats) / sizeof(R300TexFormats[0]); i++) |
715 | // { |
715 | // { |
716 | // if (R300TexFormats[i].fmt == pPict->format) |
716 | // if (R300TexFormats[i].fmt == pPict->format) |
717 | // break; |
717 | // break; |
718 | // } |
718 | // } |
719 | 719 | ||
720 | //txformat1 = R300TexFormats[i].card_fmt; |
720 | //txformat1 = R300TexFormats[i].card_fmt; |
721 | txformat1 = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8); |
721 | txformat1 = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8); |
722 | 722 | ||
723 | txformat0 = ((((w - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) | |
723 | txformat0 = ((((w - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) | |
724 | (((h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT)); |
724 | (((h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT)); |
725 | 725 | ||
726 | if (IS_R500_3D && ((w - 1) & 0x800)) |
726 | if (IS_R500_3D && ((w - 1) & 0x800)) |
727 | txpitch |= R500_TXWIDTH_11; |
727 | txpitch |= R500_TXWIDTH_11; |
728 | 728 | ||
729 | if (IS_R500_3D && ((h - 1) & 0x800)) |
729 | if (IS_R500_3D && ((h - 1) & 0x800)) |
730 | txpitch |= R500_TXHEIGHT_11; |
730 | txpitch |= R500_TXHEIGHT_11; |
731 | 731 | ||
732 | /* Use TXPITCH instead of TXWIDTH for address computations: we could |
732 | /* Use TXPITCH instead of TXWIDTH for address computations: we could |
733 | * omit this if there is no padding, but there is no apparent advantage |
733 | * omit this if there is no padding, but there is no apparent advantage |
734 | * in doing so. |
734 | * in doing so. |
735 | */ |
735 | */ |
736 | txformat0 |= R300_TXPITCH_EN; |
736 | txformat0 |= R300_TXPITCH_EN; |
737 | 737 | ||
738 | // info->texW[unit] = w; |
738 | // info->texW[unit] = w; |
739 | // info->texH[unit] = h; |
739 | // info->texH[unit] = h; |
740 | 740 | ||
741 | // if (pPict->repeat && !(unit == 0 && need_src_tile_x)) |
741 | // if (pPict->repeat && !(unit == 0 && need_src_tile_x)) |
742 | // txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_WRAP); |
742 | // txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_WRAP); |
743 | // else |
743 | // else |
744 | txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_GL); |
744 | txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_GL); |
745 | 745 | ||
746 | // if (pPict->repeat && !(unit == 0 && need_src_tile_y)) |
746 | // if (pPict->repeat && !(unit == 0 && need_src_tile_y)) |
747 | // txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_WRAP); |
747 | // txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_WRAP); |
748 | // else |
748 | // else |
749 | txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_GL); |
749 | txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_GL); |
750 | 750 | ||
751 | txfilter |= (unit << R300_TX_ID_SHIFT); |
751 | txfilter |= (unit << R300_TX_ID_SHIFT); |
752 | 752 | ||
753 | // switch (pPict->filter) { |
753 | // switch (pPict->filter) { |
754 | // case PictFilterNearest: |
754 | // case PictFilterNearest: |
755 | txfilter |= (R300_TX_MAG_FILTER_NEAREST | R300_TX_MIN_FILTER_NEAREST); |
755 | txfilter |= (R300_TX_MAG_FILTER_NEAREST | R300_TX_MIN_FILTER_NEAREST); |
756 | // break; |
756 | // break; |
757 | // case PictFilterBilinear: |
757 | // case PictFilterBilinear: |
758 | // txfilter |= (R300_TX_MAG_FILTER_LINEAR | R300_TX_MIN_FILTER_LINEAR); |
758 | // txfilter |= (R300_TX_MAG_FILTER_LINEAR | R300_TX_MIN_FILTER_LINEAR); |
759 | // break; |
759 | // break; |
760 | // default: |
760 | // default: |
761 | // RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter)); |
761 | // RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter)); |
762 | // } |
762 | // } |
763 | 763 | ||
764 | { |
764 | { |
765 | u32_t *ring, write; |
765 | u32_t *ring, write; |
766 | 766 | ||
767 | BEGIN_ACCEL(7); |
767 | BEGIN_ACCEL(7); |
768 | OUT_ACCEL_REG(R300_TX_FILTER0_0 + (unit * 4), txfilter); |
768 | OUT_ACCEL_REG(R300_TX_FILTER0_0 + (unit * 4), txfilter); |
769 | OUT_ACCEL_REG(R300_TX_FILTER1_0 + (unit * 4), 0); |
769 | OUT_ACCEL_REG(R300_TX_FILTER1_0 + (unit * 4), 0); |
770 | OUT_ACCEL_REG(R300_TX_FORMAT0_0 + (unit * 4), txformat0); |
770 | OUT_ACCEL_REG(R300_TX_FORMAT0_0 + (unit * 4), txformat0); |
771 | OUT_ACCEL_REG(R300_TX_FORMAT1_0 + (unit * 4), txformat1); |
771 | OUT_ACCEL_REG(R300_TX_FORMAT1_0 + (unit * 4), txformat1); |
772 | OUT_ACCEL_REG(R300_TX_FORMAT2_0 + (unit * 4), txpitch); |
772 | OUT_ACCEL_REG(R300_TX_FORMAT2_0 + (unit * 4), txpitch); |
773 | OUT_ACCEL_REG(R300_TX_OFFSET_0 + (unit * 4), txoffset); |
773 | OUT_ACCEL_REG(R300_TX_OFFSET_0 + (unit * 4), txoffset); |
774 | // if (!pPict->repeat) |
774 | // if (!pPict->repeat) |
775 | OUT_ACCEL_REG(R300_TX_BORDER_COLOR_0 + (unit * 4), 0); |
775 | OUT_ACCEL_REG(R300_TX_BORDER_COLOR_0 + (unit * 4), 0); |
776 | FINISH_ACCEL(); |
776 | FINISH_ACCEL(); |
777 | } |
777 | } |
778 | // if (pPict->transform != 0) { |
778 | // if (pPict->transform != 0) { |
779 | // is_transform[unit] = TRUE; |
779 | // is_transform[unit] = TRUE; |
780 | // transform[unit] = pPict->transform; |
780 | // transform[unit] = pPict->transform; |
781 | // } else { |
781 | // } else { |
782 | // is_transform[unit] = FALSE; |
782 | // is_transform[unit] = FALSE; |
783 | // } |
783 | // } |
784 | 784 | ||
785 | return TRUE; |
785 | return TRUE; |
786 | } |
786 | } |
787 | 787 | ||
788 | static u32_t RADEONGetBlendCntl(int op, u32_t dst_format) |
788 | static u32_t RADEONGetBlendCntl(int op, u32_t dst_format) |
789 | { |
789 | { |
790 | u32_t sblend, dblend; |
790 | u32_t sblend, dblend; |
791 | 791 | ||
792 | sblend = RadeonBlendOp[op].blend_cntl & RADEON_SRC_BLEND_MASK; |
792 | sblend = RadeonBlendOp[op].blend_cntl & RADEON_SRC_BLEND_MASK; |
793 | dblend = RadeonBlendOp[op].blend_cntl & RADEON_DST_BLEND_MASK; |
793 | dblend = RadeonBlendOp[op].blend_cntl & RADEON_DST_BLEND_MASK; |
794 | 794 | ||
795 | /* If there's no dst alpha channel, adjust the blend op so that we'll treat |
795 | /* If there's no dst alpha channel, adjust the blend op so that we'll treat |
796 | * it as always 1. |
796 | * it as always 1. |
797 | */ |
797 | */ |
798 | if (PICT_FORMAT_A(dst_format) == 0 && RadeonBlendOp[op].dst_alpha) { |
798 | if (PICT_FORMAT_A(dst_format) == 0 && RadeonBlendOp[op].dst_alpha) { |
799 | if (sblend == RADEON_SRC_BLEND_GL_DST_ALPHA) |
799 | if (sblend == RADEON_SRC_BLEND_GL_DST_ALPHA) |
800 | sblend = RADEON_SRC_BLEND_GL_ONE; |
800 | sblend = RADEON_SRC_BLEND_GL_ONE; |
801 | else if (sblend == RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA) |
801 | else if (sblend == RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA) |
802 | sblend = RADEON_SRC_BLEND_GL_ZERO; |
802 | sblend = RADEON_SRC_BLEND_GL_ZERO; |
803 | } |
803 | } |
804 | 804 | ||
805 | return sblend | dblend; |
805 | return sblend | dblend; |
806 | } |
806 | } |
807 | 807 | ||
808 | static Bool R300PrepareComposite(int op, int srcX, int srcY, |
808 | static Bool R300PrepareComposite(int op, int srcX, int srcY, |
809 | int dstX, int dstY, |
809 | int dstX, int dstY, |
810 | int w, int h) |
810 | int w, int h) |
811 | { |
811 | { |
812 | // RINFO_FROM_SCREEN(pDst->drawable.pScreen); |
812 | // RINFO_FROM_SCREEN(pDst->drawable.pScreen); |
813 | u32_t dst_format, dst_offset, dst_pitch; |
813 | u32_t dst_format, dst_offset, dst_pitch; |
814 | u32_t txenable, colorpitch; |
814 | u32_t txenable, colorpitch; |
815 | u32_t blendcntl; |
815 | u32_t blendcntl; |
816 | int pixel_shift; |
816 | int pixel_shift; |
817 | u32_t *ring, write; |
817 | u32_t *ring, write; |
818 | 818 | ||
819 | //ACCEL_PREAMBLE(); |
819 | //ACCEL_PREAMBLE(); |
820 | 820 | ||
821 | //TRACE; |
821 | //TRACE; |
822 | 822 | ||
823 | //if (!info->XInited3D) |
823 | //if (!info->XInited3D) |
824 | // RADEONInit3DEngine(pScrn); |
824 | // RADEONInit3DEngine(pScrn); |
825 | 825 | ||
826 | //if (!R300GetDestFormat(pDstPicture, &dst_format)) |
826 | //if (!R300GetDestFormat(pDstPicture, &dst_format)) |
827 | // return FALSE; |
827 | // return FALSE; |
828 | dst_format = R300_COLORFORMAT_ARGB8888; |
828 | dst_format = R300_COLORFORMAT_ARGB8888; |
829 | 829 | ||
830 | pixel_shift = 32 >> 4; |
830 | pixel_shift = 32 >> 4; |
831 | 831 | ||
832 | //dst_offset = exaGetPixmapOffset(pDst) + info->fbLocation + pScrn->fbOffset; |
832 | //dst_offset = exaGetPixmapOffset(pDst) + info->fbLocation + pScrn->fbOffset; |
833 | dst_offset = rhd.FbIntAddress + rhd.FbScanoutStart; |
833 | dst_offset = rhd.FbIntAddress + rhd.FbScanoutStart; |
834 | 834 | ||
835 | //dst_pitch = exaGetPixmapPitch(pDst); |
835 | //dst_pitch = exaGetPixmapPitch(pDst); |
836 | dst_pitch = rhd.displayWidth * 4; |
836 | dst_pitch = rhd.displayWidth * 4; |
837 | colorpitch = dst_pitch >> pixel_shift; |
837 | colorpitch = dst_pitch >> pixel_shift; |
838 | 838 | ||
839 | // if (RADEONPixmapIsColortiled(pDst)) |
839 | // if (RADEONPixmapIsColortiled(pDst)) |
840 | // colorpitch |= R300_COLORTILE; |
840 | // colorpitch |= R300_COLORTILE; |
841 | 841 | ||
842 | colorpitch |= dst_format; |
842 | colorpitch |= dst_format; |
843 | 843 | ||
844 | if ((dst_offset & 0x0f) != 0) |
844 | if ((dst_offset & 0x0f) != 0) |
845 | dbgprintf("Bad destination offset 0x%x\n", (int)dst_offset); |
845 | dbgprintf("Bad destination offset 0x%x\n", (int)dst_offset); |
846 | if (((dst_pitch >> pixel_shift) & 0x7) != 0) |
846 | if (((dst_pitch >> pixel_shift) & 0x7) != 0) |
847 | dbgprintf("Bad destination pitch 0x%x\n", (int)dst_pitch); |
847 | dbgprintf("Bad destination pitch 0x%x\n", (int)dst_pitch); |
848 | 848 | ||
849 | // if (!RADEONSetupSourceTile(pSrcPicture, pSrc, TRUE, FALSE)) |
849 | // if (!RADEONSetupSourceTile(pSrcPicture, pSrc, TRUE, FALSE)) |
850 | // return FALSE; |
850 | // return FALSE; |
851 | 851 | ||
852 | if (!R300TextureSetup(w, h, 0)) |
852 | if (!R300TextureSetup(w, h, 0)) |
853 | return FALSE; |
853 | return FALSE; |
854 | 854 | ||
855 | txenable = R300_TEX_0_ENABLE; |
855 | txenable = R300_TEX_0_ENABLE; |
856 | 856 | ||
857 | // RADEON_SWITCH_TO_3D(); |
857 | // RADEON_SWITCH_TO_3D(); |
858 | 858 | ||
859 | /* setup the VAP */ |
859 | /* setup the VAP */ |
860 | BEGIN_ACCEL(7); |
860 | BEGIN_ACCEL(7); |
861 | 861 | ||
862 | /* These registers define the number, type, and location of data submitted |
862 | /* These registers define the number, type, and location of data submitted |
863 | * to the PVS unit of GA input (when PVS is disabled) |
863 | * to the PVS unit of GA input (when PVS is disabled) |
864 | * DST_VEC_LOC is the slot in the PVS input vector memory when PVS/TCL is |
864 | * DST_VEC_LOC is the slot in the PVS input vector memory when PVS/TCL is |
865 | * enabled. This memory provides the imputs to the vertex shader program |
865 | * enabled. This memory provides the imputs to the vertex shader program |
866 | * and ordering is not important. When PVS/TCL is disabled, this field maps |
866 | * and ordering is not important. When PVS/TCL is disabled, this field maps |
867 | * directly to the GA input memory and the order is signifigant. In |
867 | * directly to the GA input memory and the order is signifigant. In |
868 | * PVS_BYPASS mode the order is as follows: |
868 | * PVS_BYPASS mode the order is as follows: |
869 | * Position |
869 | * Position |
870 | * Point Size |
870 | * Point Size |
871 | * Color 0-3 |
871 | * Color 0-3 |
872 | * Textures 0-7 |
872 | * Textures 0-7 |
873 | * Fog |
873 | * Fog |
874 | */ |
874 | */ |
875 | 875 | ||
876 | OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, |
876 | OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, |
877 | ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | |
877 | ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | |
878 | (0 << R300_SKIP_DWORDS_0_SHIFT) | |
878 | (0 << R300_SKIP_DWORDS_0_SHIFT) | |
879 | (0 << R300_DST_VEC_LOC_0_SHIFT) | |
879 | (0 << R300_DST_VEC_LOC_0_SHIFT) | |
880 | R300_SIGNED_0 | |
880 | R300_SIGNED_0 | |
881 | (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | |
881 | (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | |
882 | (0 << R300_SKIP_DWORDS_1_SHIFT) | |
882 | (0 << R300_SKIP_DWORDS_1_SHIFT) | |
883 | (6 << R300_DST_VEC_LOC_1_SHIFT) | |
883 | (6 << R300_DST_VEC_LOC_1_SHIFT) | |
884 | R300_LAST_VEC_1 | |
884 | R300_LAST_VEC_1 | |
885 | R300_SIGNED_1)); |
885 | R300_SIGNED_1)); |
886 | 886 | ||
887 | /* load the vertex shader |
887 | /* load the vertex shader |
888 | * We pre-load vertex programs in RADEONInit3DEngine(): |
888 | * We pre-load vertex programs in RADEONInit3DEngine(): |
889 | * - exa no mask |
889 | * - exa no mask |
890 | * - exa mask |
890 | * - exa mask |
891 | * - Xv |
891 | * - Xv |
892 | * Here we select the offset of the vertex program we want to use |
892 | * Here we select the offset of the vertex program we want to use |
893 | */ |
893 | */ |
894 | OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, |
894 | OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, |
895 | ((3 << R300_PVS_FIRST_INST_SHIFT) | |
895 | ((3 << R300_PVS_FIRST_INST_SHIFT) | |
896 | (4 << R300_PVS_XYZW_VALID_INST_SHIFT) | |
896 | (4 << R300_PVS_XYZW_VALID_INST_SHIFT) | |
897 | (4 << R300_PVS_LAST_INST_SHIFT))); |
897 | (4 << R300_PVS_LAST_INST_SHIFT))); |
898 | OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, |
898 | OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, |
899 | (4 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); |
899 | (4 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); |
900 | 900 | ||
901 | /* Position and one or two sets of 2 texture coordinates */ |
901 | /* Position and one or two sets of 2 texture coordinates */ |
902 | OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT); |
902 | OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT); |
903 | OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT)); |
903 | OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT)); |
904 | 904 | ||
905 | OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0); |
905 | OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0); |
906 | OUT_ACCEL_REG(R300_TX_ENABLE, txenable); |
906 | OUT_ACCEL_REG(R300_TX_ENABLE, txenable); |
907 | FINISH_ACCEL(); |
907 | FINISH_ACCEL(); |
908 | 908 | ||
909 | /* setup pixel shader */ |
909 | /* setup pixel shader */ |
910 | if (IS_R300_3D) { |
910 | if (IS_R300_3D) { |
911 | } else { |
911 | } else { |
912 | u32_t output_fmt; |
912 | u32_t output_fmt; |
913 | u32_t src_color, src_alpha; |
913 | u32_t src_color, src_alpha; |
914 | u32_t mask_color, mask_alpha; |
914 | u32_t mask_color, mask_alpha; |
915 | 915 | ||
916 | if (PICT_FORMAT_RGB(PICT_a8r8g8b8) == 0) |
916 | if (PICT_FORMAT_RGB(PICT_a8r8g8b8) == 0) |
917 | src_color = (R500_ALU_RGB_R_SWIZ_A_0 | |
917 | src_color = (R500_ALU_RGB_R_SWIZ_A_0 | |
918 | R500_ALU_RGB_G_SWIZ_A_0 | |
918 | R500_ALU_RGB_G_SWIZ_A_0 | |
919 | R500_ALU_RGB_B_SWIZ_A_0); |
919 | R500_ALU_RGB_B_SWIZ_A_0); |
920 | else |
920 | else |
921 | src_color = (R500_ALU_RGB_R_SWIZ_A_R | |
921 | src_color = (R500_ALU_RGB_R_SWIZ_A_R | |
922 | R500_ALU_RGB_G_SWIZ_A_G | |
922 | R500_ALU_RGB_G_SWIZ_A_G | |
923 | R500_ALU_RGB_B_SWIZ_A_B); |
923 | R500_ALU_RGB_B_SWIZ_A_B); |
924 | 924 | ||
925 | if (PICT_FORMAT_A(PICT_a8r8g8b8) == 0) |
925 | if (PICT_FORMAT_A(PICT_a8r8g8b8) == 0) |
926 | src_alpha = R500_ALPHA_SWIZ_A_1; |
926 | src_alpha = R500_ALPHA_SWIZ_A_1; |
927 | else |
927 | else |
928 | src_alpha = R500_ALPHA_SWIZ_A_A; |
928 | src_alpha = R500_ALPHA_SWIZ_A_A; |
929 | 929 | ||
930 | mask_color = (R500_ALU_RGB_R_SWIZ_B_1 | |
930 | mask_color = (R500_ALU_RGB_R_SWIZ_B_1 | |
931 | R500_ALU_RGB_G_SWIZ_B_1 | |
931 | R500_ALU_RGB_G_SWIZ_B_1 | |
932 | R500_ALU_RGB_B_SWIZ_B_1); |
932 | R500_ALU_RGB_B_SWIZ_B_1); |
933 | mask_alpha = R500_ALPHA_SWIZ_B_1; |
933 | mask_alpha = R500_ALPHA_SWIZ_B_1; |
934 | 934 | ||
935 | /* shader output swizzling */ |
935 | /* shader output swizzling */ |
936 | output_fmt = (R300_OUT_FMT_C4_8 | |
936 | output_fmt = (R300_OUT_FMT_C4_8 | |
937 | R300_OUT_FMT_C0_SEL_BLUE | |
937 | R300_OUT_FMT_C0_SEL_BLUE | |
938 | R300_OUT_FMT_C1_SEL_GREEN | |
938 | R300_OUT_FMT_C1_SEL_GREEN | |
939 | R300_OUT_FMT_C2_SEL_RED | |
939 | R300_OUT_FMT_C2_SEL_RED | |
940 | R300_OUT_FMT_C3_SEL_ALPHA); |
940 | R300_OUT_FMT_C3_SEL_ALPHA); |
941 | 941 | ||
942 | BEGIN_ACCEL(6); |
942 | BEGIN_ACCEL(6); |
943 | OUT_ACCEL_REG(R300_RS_COUNT, |
943 | OUT_ACCEL_REG(R300_RS_COUNT, |
944 | ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | |
944 | ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | |
945 | R300_RS_COUNT_HIRES_EN)); |
945 | R300_RS_COUNT_HIRES_EN)); |
946 | 946 | ||
947 | OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6)); |
947 | OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6)); |
948 | 948 | ||
949 | OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) | |
949 | OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) | |
950 | R500_US_CODE_END_ADDR(1))); |
950 | R500_US_CODE_END_ADDR(1))); |
951 | OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) | |
951 | OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) | |
952 | R500_US_CODE_RANGE_SIZE(1))); |
952 | R500_US_CODE_RANGE_SIZE(1))); |
953 | OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0); |
953 | OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0); |
954 | 954 | ||
955 | OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt); |
955 | OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt); |
956 | FINISH_ACCEL(); |
956 | FINISH_ACCEL(); |
957 | 957 | ||
958 | BEGIN_ACCEL(13); |
958 | BEGIN_ACCEL(13); |
959 | OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0); |
959 | OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0); |
960 | /* tex inst for src texture */ |
960 | /* tex inst for src texture */ |
961 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | |
961 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | |
962 | R500_INST_TEX_SEM_WAIT | |
962 | R500_INST_TEX_SEM_WAIT | |
963 | R500_INST_RGB_WMASK_R | |
963 | R500_INST_RGB_WMASK_R | |
964 | R500_INST_RGB_WMASK_G | |
964 | R500_INST_RGB_WMASK_G | |
965 | R500_INST_RGB_WMASK_B | |
965 | R500_INST_RGB_WMASK_B | |
966 | R500_INST_ALPHA_WMASK | |
966 | R500_INST_ALPHA_WMASK | |
967 | R500_INST_RGB_CLAMP | |
967 | R500_INST_RGB_CLAMP | |
968 | R500_INST_ALPHA_CLAMP)); |
968 | R500_INST_ALPHA_CLAMP)); |
969 | 969 | ||
970 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | |
970 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | |
971 | R500_TEX_INST_LD | |
971 | R500_TEX_INST_LD | |
972 | R500_TEX_SEM_ACQUIRE | |
972 | R500_TEX_SEM_ACQUIRE | |
973 | R500_TEX_IGNORE_UNCOVERED)); |
973 | R500_TEX_IGNORE_UNCOVERED)); |
974 | 974 | ||
975 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | |
975 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | |
976 | R500_TEX_SRC_S_SWIZ_R | |
976 | R500_TEX_SRC_S_SWIZ_R | |
977 | R500_TEX_SRC_T_SWIZ_G | |
977 | R500_TEX_SRC_T_SWIZ_G | |
978 | R500_TEX_DST_ADDR(0) | |
978 | R500_TEX_DST_ADDR(0) | |
979 | R500_TEX_DST_R_SWIZ_R | |
979 | R500_TEX_DST_R_SWIZ_R | |
980 | R500_TEX_DST_G_SWIZ_G | |
980 | R500_TEX_DST_G_SWIZ_G | |
981 | R500_TEX_DST_B_SWIZ_B | |
981 | R500_TEX_DST_B_SWIZ_B | |
982 | R500_TEX_DST_A_SWIZ_A)); |
982 | R500_TEX_DST_A_SWIZ_A)); |
983 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) | |
983 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) | |
984 | R500_DX_S_SWIZ_R | |
984 | R500_DX_S_SWIZ_R | |
985 | R500_DX_T_SWIZ_R | |
985 | R500_DX_T_SWIZ_R | |
986 | R500_DX_R_SWIZ_R | |
986 | R500_DX_R_SWIZ_R | |
987 | R500_DX_Q_SWIZ_R | |
987 | R500_DX_Q_SWIZ_R | |
988 | R500_DY_ADDR(0) | |
988 | R500_DY_ADDR(0) | |
989 | R500_DY_S_SWIZ_R | |
989 | R500_DY_S_SWIZ_R | |
990 | R500_DY_T_SWIZ_R | |
990 | R500_DY_T_SWIZ_R | |
991 | R500_DY_R_SWIZ_R | |
991 | R500_DY_R_SWIZ_R | |
992 | R500_DY_Q_SWIZ_R)); |
992 | R500_DY_Q_SWIZ_R)); |
993 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); |
993 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); |
994 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); |
994 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); |
995 | 995 | ||
996 | /* ALU inst */ |
996 | /* ALU inst */ |
997 | /* *_OMASK* - output component write mask */ |
997 | /* *_OMASK* - output component write mask */ |
998 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT | |
998 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT | |
999 | R500_INST_TEX_SEM_WAIT | |
999 | R500_INST_TEX_SEM_WAIT | |
1000 | R500_INST_LAST | |
1000 | R500_INST_LAST | |
1001 | R500_INST_RGB_OMASK_R | |
1001 | R500_INST_RGB_OMASK_R | |
1002 | R500_INST_RGB_OMASK_G | |
1002 | R500_INST_RGB_OMASK_G | |
1003 | R500_INST_RGB_OMASK_B | |
1003 | R500_INST_RGB_OMASK_B | |
1004 | R500_INST_ALPHA_OMASK | |
1004 | R500_INST_ALPHA_OMASK | |
1005 | R500_INST_RGB_CLAMP | |
1005 | R500_INST_RGB_CLAMP | |
1006 | R500_INST_ALPHA_CLAMP)); |
1006 | R500_INST_ALPHA_CLAMP)); |
1007 | /* ALU inst |
1007 | /* ALU inst |
1008 | * temp addresses for texture inputs |
1008 | * temp addresses for texture inputs |
1009 | * RGB_ADDR0 is src tex (temp 0) |
1009 | * RGB_ADDR0 is src tex (temp 0) |
1010 | * RGB_ADDR1 is mask tex (temp 1) |
1010 | * RGB_ADDR1 is mask tex (temp 1) |
1011 | */ |
1011 | */ |
1012 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | |
1012 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | |
1013 | R500_RGB_ADDR1(1) | |
1013 | R500_RGB_ADDR1(1) | |
1014 | R500_RGB_ADDR2(0))); |
1014 | R500_RGB_ADDR2(0))); |
1015 | /* ALU inst |
1015 | /* ALU inst |
1016 | * temp addresses for texture inputs |
1016 | * temp addresses for texture inputs |
1017 | * ALPHA_ADDR0 is src tex (temp 0) |
1017 | * ALPHA_ADDR0 is src tex (temp 0) |
1018 | * ALPHA_ADDR1 is mask tex (temp 1) |
1018 | * ALPHA_ADDR1 is mask tex (temp 1) |
1019 | */ |
1019 | */ |
1020 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | |
1020 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | |
1021 | R500_ALPHA_ADDR1(1) | |
1021 | R500_ALPHA_ADDR1(1) | |
1022 | R500_ALPHA_ADDR2(0))); |
1022 | R500_ALPHA_ADDR2(0))); |
1023 | 1023 | ||
1024 | /* R500_ALU_RGB_TARGET - RGB render target */ |
1024 | /* R500_ALU_RGB_TARGET - RGB render target */ |
1025 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | |
1025 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | |
1026 | src_color | |
1026 | src_color | |
1027 | R500_ALU_RGB_SEL_B_SRC1 | |
1027 | R500_ALU_RGB_SEL_B_SRC1 | |
1028 | mask_color | |
1028 | mask_color | |
1029 | R500_ALU_RGB_TARGET(0))); |
1029 | R500_ALU_RGB_TARGET(0))); |
1030 | 1030 | ||
1031 | /* R500_ALPHA_RGB_TARGET - alpha render target */ |
1031 | /* R500_ALPHA_RGB_TARGET - alpha render target */ |
1032 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD | |
1032 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD | |
1033 | R500_ALPHA_ADDRD(0) | |
1033 | R500_ALPHA_ADDRD(0) | |
1034 | R500_ALPHA_SEL_A_SRC0 | |
1034 | R500_ALPHA_SEL_A_SRC0 | |
1035 | src_alpha | |
1035 | src_alpha | |
1036 | R500_ALPHA_SEL_B_SRC1 | |
1036 | R500_ALPHA_SEL_B_SRC1 | |
1037 | mask_alpha | |
1037 | mask_alpha | |
1038 | R500_ALPHA_TARGET(0))); |
1038 | R500_ALPHA_TARGET(0))); |
1039 | 1039 | ||
1040 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD | |
1040 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD | |
1041 | R500_ALU_RGBA_ADDRD(0) | |
1041 | R500_ALU_RGBA_ADDRD(0) | |
1042 | R500_ALU_RGBA_R_SWIZ_0 | |
1042 | R500_ALU_RGBA_R_SWIZ_0 | |
1043 | R500_ALU_RGBA_G_SWIZ_0 | |
1043 | R500_ALU_RGBA_G_SWIZ_0 | |
1044 | R500_ALU_RGBA_B_SWIZ_0 | |
1044 | R500_ALU_RGBA_B_SWIZ_0 | |
1045 | R500_ALU_RGBA_A_SWIZ_0)); |
1045 | R500_ALU_RGBA_A_SWIZ_0)); |
1046 | FINISH_ACCEL(); |
1046 | FINISH_ACCEL(); |
1047 | } |
1047 | } |
1048 | 1048 | ||
1049 | BEGIN_ACCEL(3); |
1049 | BEGIN_ACCEL(3); |
1050 | 1050 | ||
1051 | OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset); |
1051 | OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset); |
1052 | OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch); |
1052 | OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch); |
1053 | 1053 | ||
1054 | blendcntl = RADEONGetBlendCntl(op, PICT_a8r8g8b8); |
1054 | blendcntl = RADEONGetBlendCntl(op, PICT_a8r8g8b8); |
1055 | OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl | R300_ALPHA_BLEND_ENABLE | R300_READ_ENABLE); |
1055 | OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl | R300_ALPHA_BLEND_ENABLE | R300_READ_ENABLE); |
1056 | 1056 | ||
1057 | FINISH_ACCEL(); |
1057 | FINISH_ACCEL(); |
1058 | 1058 | ||
1059 | return TRUE; |
1059 | return TRUE; |
1060 | } |
1060 | } |
1061 | 1061 | ||
1062 | 1062 | ||
1063 | 1063 | ||
1064 | 1064 | ||
1065 | 1065 | ||
1066 | 1066 | ||
1067 | #define VTX_COUNT 4 |
1067 | #define VTX_COUNT 4 |
1068 | 1068 | ||
1069 | static __inline__ u32_t F_TO_DW(float val) |
1069 | static __inline__ u32_t F_TO_DW(float val) |
1070 | { |
1070 | { |
1071 | union { |
1071 | union { |
1072 | float f; |
1072 | float f; |
1073 | u32_t l; |
1073 | u32_t l; |
1074 | } tmp; |
1074 | } tmp; |
1075 | tmp.f = val; |
1075 | tmp.f = val; |
1076 | return tmp.l; |
1076 | return tmp.l; |
1077 | } |
1077 | } |
1078 | 1078 | ||
1079 | #define OUT_RING_F(x) OUT_RING(F_TO_DW(x)) |
1079 | #define OUT_RING_F(x) OUT_RING(F_TO_DW(x)) |
1080 | 1080 | ||
1081 | #define VTX_OUT(_dstX, _dstY, _srcX, _srcY) \ |
1081 | #define VTX_OUT(_dstX, _dstY, _srcX, _srcY) \ |
1082 | do { \ |
1082 | do { \ |
1083 | OUT_RING_F(_dstX); \ |
1083 | OUT_RING_F(_dstX); \ |
1084 | OUT_RING_F(_dstY); \ |
1084 | OUT_RING_F(_dstY); \ |
1085 | OUT_RING_F(_srcX); \ |
1085 | OUT_RING_F(_srcX); \ |
1086 | OUT_RING_F(_srcY); \ |
1086 | OUT_RING_F(_srcY); \ |
1087 | } while (0) |
1087 | } while (0) |
1088 | 1088 | ||
1089 | 1089 | ||
1090 | 1090 | ||
1091 | static void RadeonCompositeTile(int srcX, int srcY, |
1091 | static void RadeonCompositeTile(int srcX, int srcY, |
1092 | int dstX, int dstY, |
1092 | int dstX, int dstY, |
1093 | int w, int h) |
1093 | int w, int h) |
1094 | { |
1094 | { |
1095 | // RINFO_FROM_SCREEN(pDst->drawable.pScreen); |
1095 | // RINFO_FROM_SCREEN(pDst->drawable.pScreen); |
1096 | int vtx_count; |
1096 | int vtx_count; |
1097 | xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight; |
1097 | xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight; |
1098 | xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight; |
1098 | xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight; |
1099 | 1099 | ||
1100 | u32 *ring, write; |
1100 | u32_t *ring, write; |
1101 | 1101 | ||
1102 | 1102 | ||
1103 | // ACCEL_PREAMBLE(); |
1103 | // ACCEL_PREAMBLE(); |
1104 | 1104 | ||
1105 | // ENTER_DRAW(0); |
1105 | // ENTER_DRAW(0); |
1106 | 1106 | ||
1107 | /* ErrorF("RadeonComposite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n", |
1107 | /* ErrorF("RadeonComposite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n", |
1108 | srcX, srcY, maskX, maskY,dstX, dstY, w, h); */ |
1108 | srcX, srcY, maskX, maskY,dstX, dstY, w, h); */ |
1109 | 1109 | ||
1110 | srcTopLeft.x = IntToxFixed(srcX); |
1110 | srcTopLeft.x = IntToxFixed(srcX); |
1111 | srcTopLeft.y = IntToxFixed(srcY); |
1111 | srcTopLeft.y = IntToxFixed(srcY); |
1112 | srcTopRight.x = IntToxFixed(srcX + w); |
1112 | srcTopRight.x = IntToxFixed(srcX + w); |
1113 | srcTopRight.y = IntToxFixed(srcY); |
1113 | srcTopRight.y = IntToxFixed(srcY); |
1114 | srcBottomLeft.x = IntToxFixed(srcX); |
1114 | srcBottomLeft.x = IntToxFixed(srcX); |
1115 | srcBottomLeft.y = IntToxFixed(srcY + h); |
1115 | srcBottomLeft.y = IntToxFixed(srcY + h); |
1116 | srcBottomRight.x = IntToxFixed(srcX + w); |
1116 | srcBottomRight.x = IntToxFixed(srcX + w); |
1117 | srcBottomRight.y = IntToxFixed(srcY + h); |
1117 | srcBottomRight.y = IntToxFixed(srcY + h); |
1118 | 1118 | ||
1119 | /* |
1119 | /* |
1120 | if (is_transform[0]) { |
1120 | if (is_transform[0]) { |
1121 | transformPoint(transform[0], &srcTopLeft); |
1121 | transformPoint(transform[0], &srcTopLeft); |
1122 | transformPoint(transform[0], &srcTopRight); |
1122 | transformPoint(transform[0], &srcTopRight); |
1123 | transformPoint(transform[0], &srcBottomLeft); |
1123 | transformPoint(transform[0], &srcBottomLeft); |
1124 | transformPoint(transform[0], &srcBottomRight); |
1124 | transformPoint(transform[0], &srcBottomRight); |
1125 | } |
1125 | } |
1126 | if (is_transform[1]) { |
1126 | if (is_transform[1]) { |
1127 | transformPoint(transform[1], &maskTopLeft); |
1127 | transformPoint(transform[1], &maskTopLeft); |
1128 | transformPoint(transform[1], &maskTopRight); |
1128 | transformPoint(transform[1], &maskTopRight); |
1129 | transformPoint(transform[1], &maskBottomLeft); |
1129 | transformPoint(transform[1], &maskBottomLeft); |
1130 | transformPoint(transform[1], &maskBottomRight); |
1130 | transformPoint(transform[1], &maskBottomRight); |
1131 | } |
1131 | } |
1132 | */ |
1132 | */ |
1133 | vtx_count = VTX_COUNT; |
1133 | vtx_count = VTX_COUNT; |
1134 | 1134 | ||
1135 | BEGIN_ACCEL(1); |
1135 | BEGIN_ACCEL(1); |
1136 | OUT_ACCEL_REG(R300_VAP_VTX_SIZE, vtx_count); |
1136 | OUT_ACCEL_REG(R300_VAP_VTX_SIZE, vtx_count); |
1137 | FINISH_ACCEL(); |
1137 | FINISH_ACCEL(); |
1138 | 1138 | ||
1139 | BEGIN_RING(4 * vtx_count + 4); |
1139 | BEGIN_RING(4 * vtx_count + 4); |
1140 | 1140 | ||
1141 | OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, |
1141 | OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, |
1142 | 4 * vtx_count)); |
1142 | 4 * vtx_count)); |
1143 | OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN | |
1143 | OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN | |
1144 | RADEON_CP_VC_CNTL_PRIM_WALK_RING | |
1144 | RADEON_CP_VC_CNTL_PRIM_WALK_RING | |
1145 | (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); |
1145 | (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); |
1146 | 1146 | ||
1147 | 1147 | ||
1148 | VTX_OUT((float)dstX, (float)dstY, |
1148 | VTX_OUT((float)dstX, (float)dstY, |
1149 | xFixedToFloat(srcTopLeft.x) / w, // info->texW[0], |
1149 | xFixedToFloat(srcTopLeft.x) / w, // info->texW[0], |
1150 | xFixedToFloat(srcTopLeft.y) / h); // info->texH[0]); |
1150 | xFixedToFloat(srcTopLeft.y) / h); // info->texH[0]); |
1151 | 1151 | ||
1152 | VTX_OUT((float)dstX, (float)(dstY + h), |
1152 | VTX_OUT((float)dstX, (float)(dstY + h), |
1153 | xFixedToFloat(srcBottomLeft.x) / w, // info->texW[0], |
1153 | xFixedToFloat(srcBottomLeft.x) / w, // info->texW[0], |
1154 | xFixedToFloat(srcBottomLeft.y) / h); // info->texH[0]); |
1154 | xFixedToFloat(srcBottomLeft.y) / h); // info->texH[0]); |
1155 | 1155 | ||
1156 | VTX_OUT((float)(dstX + w), (float)(dstY + h), |
1156 | VTX_OUT((float)(dstX + w), (float)(dstY + h), |
1157 | xFixedToFloat(srcBottomRight.x) / w, // info->texW[0], |
1157 | xFixedToFloat(srcBottomRight.x) / w, // info->texW[0], |
1158 | xFixedToFloat(srcBottomRight.y) / h); // info->texH[0]); |
1158 | xFixedToFloat(srcBottomRight.y) / h); // info->texH[0]); |
1159 | 1159 | ||
1160 | VTX_OUT((float)(dstX + w), (float)dstY, |
1160 | VTX_OUT((float)(dstX + w), (float)dstY, |
1161 | xFixedToFloat(srcTopRight.x) / w, // info->texW[0], |
1161 | xFixedToFloat(srcTopRight.x) / w, // info->texW[0], |
1162 | xFixedToFloat(srcTopRight.y) / h); // info->texH[0]); |
1162 | xFixedToFloat(srcTopRight.y) / h); // info->texH[0]); |
1163 | 1163 | ||
1164 | /* flushing is pipelined, free/finish is not */ |
1164 | /* flushing is pipelined, free/finish is not */ |
1165 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D); |
1165 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D); |
1166 | 1166 | ||
1167 | // OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); |
1167 | // OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); |
1168 | 1168 | ||
1169 | COMMIT_RING(); |
1169 | COMMIT_RING(); |
1170 | 1170 | ||
1171 | // LEAVE_DRAW(0); |
1171 | // LEAVE_DRAW(0); |
1172 | } |
1172 | } |
1173 | #undef VTX_OUT |
1173 | #undef VTX_OUT |
1174 | #undef VTX_OUT_MASK |
1174 | #undef VTX_OUT_MASK |
1175 | 1175 | ||
1176 | 1176 | ||
1177 | int RadeonComposite( blit_t *blit) |
1177 | int RadeonComposite( blit_t *blit) |
1178 | { |
1178 | { |
1179 | int tileSrcY, tileMaskY, tileDstY; |
1179 | int tileSrcY, tileMaskY, tileDstY; |
1180 | int remainingHeight; |
1180 | int remainingHeight; |
1181 | 1181 | ||
1182 | R300PrepareComposite(3, blit->src_x, blit->src_y, |
1182 | R300PrepareComposite(3, blit->src_x, blit->src_y, |
1183 | blit->dst_x, blit->dst_y, |
1183 | blit->dst_x, blit->dst_y, |
1184 | blit->w, blit->h); |
1184 | blit->w, blit->h); |
1185 | 1185 | ||
1186 | // if (!need_src_tile_x && !need_src_tile_y) { |
1186 | // if (!need_src_tile_x && !need_src_tile_y) { |
1187 | RadeonCompositeTile( blit->src_x, blit->src_y, |
1187 | RadeonCompositeTile( blit->src_x, blit->src_y, |
1188 | blit->dst_x, blit->dst_y, |
1188 | blit->dst_x, blit->dst_y, |
1189 | blit->w, blit->h); |
1189 | blit->w, blit->h); |
1190 | return 0; |
1190 | return 0; |
1191 | // } |
1191 | // } |
1192 | 1192 | ||
1193 | /* Tiling logic borrowed from exaFillRegionTiled */ |
1193 | /* Tiling logic borrowed from exaFillRegionTiled */ |
1194 | 1194 | ||
1195 | #if 0 |
1195 | #if 0 |
1196 | modulus(srcY, src_tile_height, tileSrcY); |
1196 | modulus(srcY, src_tile_height, tileSrcY); |
1197 | tileMaskY = maskY; |
1197 | tileMaskY = maskY; |
1198 | tileDstY = dstY; |
1198 | tileDstY = dstY; |
1199 | 1199 | ||
1200 | remainingHeight = height; |
1200 | remainingHeight = height; |
1201 | while (remainingHeight > 0) { |
1201 | while (remainingHeight > 0) { |
1202 | int remainingWidth = width; |
1202 | int remainingWidth = width; |
1203 | int tileSrcX, tileMaskX, tileDstX; |
1203 | int tileSrcX, tileMaskX, tileDstX; |
1204 | int h = src_tile_height - tileSrcY; |
1204 | int h = src_tile_height - tileSrcY; |
1205 | 1205 | ||
1206 | if (h > remainingHeight) |
1206 | if (h > remainingHeight) |
1207 | h = remainingHeight; |
1207 | h = remainingHeight; |
1208 | remainingHeight -= h; |
1208 | remainingHeight -= h; |
1209 | 1209 | ||
1210 | modulus(srcX, src_tile_width, tileSrcX); |
1210 | modulus(srcX, src_tile_width, tileSrcX); |
1211 | tileMaskX = maskX; |
1211 | tileMaskX = maskX; |
1212 | tileDstX = dstX; |
1212 | tileDstX = dstX; |
1213 | 1213 | ||
1214 | while (remainingWidth > 0) { |
1214 | while (remainingWidth > 0) { |
1215 | int w = src_tile_width - tileSrcX; |
1215 | int w = src_tile_width - tileSrcX; |
1216 | if (w > remainingWidth) |
1216 | if (w > remainingWidth) |
1217 | w = remainingWidth; |
1217 | w = remainingWidth; |
1218 | remainingWidth -= w; |
1218 | remainingWidth -= w; |
1219 | 1219 | ||
1220 | FUNC_NAME(RadeonCompositeTile)(pDst, |
1220 | FUNC_NAME(RadeonCompositeTile)(pDst, |
1221 | tileSrcX, tileSrcY, |
1221 | tileSrcX, tileSrcY, |
1222 | tileMaskX, tileMaskY, |
1222 | tileMaskX, tileMaskY, |
1223 | tileDstX, tileDstY, |
1223 | tileDstX, tileDstY, |
1224 | w, h); |
1224 | w, h); |
1225 | 1225 | ||
1226 | tileSrcX = 0; |
1226 | tileSrcX = 0; |
1227 | tileMaskX += w; |
1227 | tileMaskX += w; |
1228 | tileDstX += w; |
1228 | tileDstX += w; |
1229 | } |
1229 | } |
1230 | tileSrcY = 0; |
1230 | tileSrcY = 0; |
1231 | tileMaskY += h; |
1231 | tileMaskY += h; |
1232 | tileDstY += h; |
1232 | tileDstY += h; |
1233 | } |
1233 | } |
1234 | #endif |
1234 | #endif |
1235 | }><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |
1235 | }><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |