WebSVN – Kolibri OS – Diff – /programs/system/drivers/agp/agp.c

 #include "types.h"
+#include "link.h"
 #include
 #include
 #include "syscall.h"
 //    return retval;
 };
 #include "pci.inc"
 static void intel_8xx_tlbflush(void *mem)
 {
     u32_t temp;
-    temp = pciReadLong(agp_dev.PciTag, INTEL_AGPCTRL);
+    temp = pciReadLong(bridge->PciTag, INTEL_AGPCTRL);
-    pciWriteLong(agp_dev.PciTag, INTEL_AGPCTRL, temp & ~(1 << 7));
+    pciWriteLong(bridge->PciTag, INTEL_AGPCTRL, temp & ~(1 << 7));
-    temp = pciReadLong(agp_dev.PciTag, INTEL_AGPCTRL);
+    temp = pciReadLong(bridge->PciTag, INTEL_AGPCTRL);
-    pciWriteLong(agp_dev.PciTag, INTEL_AGPCTRL, temp | (1 << 7));
+    pciWriteLong(bridge->PciTag, INTEL_AGPCTRL, temp | (1 << 7));
     {   8,  2048,  2, 62 },
     {   4,  1024,  1, 63 }
 };
-#if 0
-static int agp_backend_initialize(struct agp_bridge_data *bridge)
-{
-	int size_value, rc, got_gatt=0, got_keylist=0;
-	bridge->max_memory_agp = agp_find_max();
-	bridge->version = &agp_current_version;
-	if (bridge->driver->needs_scratch_page) {
-		void *addr = bridge->driver->agp_alloc_page(bridge);
-		if (!addr) {
-			printk(KERN_ERR PFX "unable to get memory for scratch page.\n");
-			return -ENOMEM;
-		}
-		flush_agp_mappings();
-		bridge->scratch_page_real = virt_to_gart(addr);
-		bridge->scratch_page =
-		    bridge->driver->mask_memory(bridge, bridge->scratch_page_real, 0);
-	}
-	size_value = bridge->driver->fetch_size();
-	if (size_value == 0) {
-		printk(KERN_ERR PFX "unable to determine aperture size.\n");
-		rc = -EINVAL;
-		goto err_out;
-	}
-	if (bridge->driver->create_gatt_table(bridge)) {
-		printk(KERN_ERR PFX
-		    "unable to get memory for graphics translation table.\n");
-		rc = -ENOMEM;
-		goto err_out;
-	}
-	got_gatt = 1;
-	bridge->key_list = vmalloc(PAGE_SIZE * 4);
-	if (bridge->key_list == NULL) {
-		printk(KERN_ERR PFX "error allocating memory for key lists.\n");
-		rc = -ENOMEM;
-		goto err_out;
-	}
-	got_keylist = 1;
-	/* FIXME vmalloc'd memory not guaranteed contiguous */
-	memset(bridge->key_list, 0, PAGE_SIZE * 4);
-	if (bridge->driver->configure()) {
-		printk(KERN_ERR PFX "error configuring host chipset.\n");
-		rc = -EINVAL;
-		goto err_out;
-	}
-	return 0;
-err_out:
-	if (bridge->driver->needs_scratch_page) {
-		bridge->driver->agp_destroy_page(
-				gart_to_virt(bridge->scratch_page_real));
-		flush_agp_mappings();
-	}
-	if (got_gatt)
-		bridge->driver->free_gatt_table(bridge);
-	if (got_keylist) {
-		vfree(bridge->key_list);
-		bridge->key_list = NULL;
-	}
-	return rc;
-}
-#endif
-static int intel_845_configure(void *bridge)
+static int intel_845_configure()
+{
     u32_t temp;
-    u8_t  temp2;
-    aper_size_t *current_size;
+    u8_t  temp2;
-    agp_t *agp = (agp_t*)bridge;
+    aper_size_t *current_size;
-    current_size = agp->current_size;
+    current_size = bridge->current_size;
 	/* aperture size */
-    pciWriteByte(agp->PciTag, INTEL_APSIZE, current_size->size_value);
+    pciWriteByte(bridge->PciTag, INTEL_APSIZE, current_size->size_value);
     dbgprintf("INTEL_APSIZE %d\n", current_size->size_value );
-    if (agp->apbase_config != 0)
+    if (bridge->apbase_config != 0)
     {
-        pciWriteLong(agp->PciTag, AGP_APBASE, agp->apbase_config);
+        pciWriteLong(bridge->PciTag, AGP_APBASE, bridge->apbase_config);
     }
     else
+    {
 		/* address to map to */
-        temp = pciReadLong(agp->PciTag, AGP_APBASE);
+        temp = pciReadLong(bridge->PciTag, AGP_APBASE);
-        agp->gart_addr = (temp & PCI_MAP_MEMORY_ADDRESS_MASK);
+        bridge->gart_addr = (temp & PCI_MAP_MEMORY_ADDRESS_MASK);
-        agp->apbase_config = temp;
+        bridge->apbase_config = temp;
+	}
     dbgprintf("AGP_APBASE %x\n", temp );
 	/* attbase - aperture base */
-    pciWriteLong(agp->PciTag, INTEL_ATTBASE, agp->gatt_dma);
+    pciWriteLong(bridge->PciTag, INTEL_ATTBASE, bridge->gatt_dma);
 	/* agpctrl */
-    pciWriteLong(agp->PciTag, INTEL_AGPCTRL, 0x0000);
+    pciWriteLong(bridge->PciTag, INTEL_AGPCTRL, 0x0000);
 	/* agpm */
-    temp2 = pciReadByte(agp->PciTag, INTEL_I845_AGPM);
+    temp2 = pciReadByte(bridge->PciTag, INTEL_I845_AGPM);
-    pciWriteByte(agp->PciTag, INTEL_I845_AGPM, temp2 | (1 << 1));
+    pciWriteByte(bridge->PciTag, INTEL_I845_AGPM, temp2 | (1 << 1));
+	/* clear any possible error conditions */
-	/* clear any possible error conditions */
+    pciWriteWord(bridge->PciTag, INTEL_I845_ERRSTS, 0x001c);
-    pciWriteWord(agp->PciTag, INTEL_I845_ERRSTS, 0x001c);
+	return 0;
-	return 0;
+}
-int agp_generic_create_gatt_table(agp_t *bridge)
-{
-    count_t pages;
+int agp_generic_create_gatt_table()
-    pages = bridge->current_size->pages_count;
-    bridge->gatt_dma = AllocPages(pages);
+{
+    count_t pages;
+    pages = bridge->current_size->pages_count;
+    if( bridge->gatt_dma = AllocPages(pages))
+    {
+        if(bridge->gatt_table =
+           (u32_t*)MapIoMem((void*)bridge->gatt_dma,
+                            pages<<12, PG_SW+PG_NOCACHE))
+        {
+            dbgprintf("gatt map %x at %x %d pages\n",bridge->gatt_dma ,
+                       bridge->gatt_table, pages);
+	/* AK: bogus, should encode addresses > 4GB */
-    bridge->gatt_table = (u32_t*)MapIoMem((void*)bridge->gatt_dma,
+            u32_t volatile *table = bridge->gatt_table;
-                                     pages<<12, PG_SW+PG_NOCACHE);
-    dbgprintf("gatt map %x at %x %d pages\n",bridge->gatt_dma ,
+            count_t count = bridge->current_size->num_entries;
                bridge->gatt_table, pages);
             while(count--) {            /* FIXME memset */
-    if (bridge->gatt_table == NULL)
+                addr_t tmp;
         return -30;//ENOMEM;
                 *table = 0;
-	/* AK: bogus, should encode addresses > 4GB */
+                table++;
 //    for (i = 0; i < num_entries; i++) {
-//        writel(bridge->scratch_page, bridge->gatt_table+i);
+            return 1;
-//        readl(bridge->gatt_table+i);    /* PCI Posting. */
+        };
-//    }
+    };
+    dbgprintf("unable to get memory for "
-	return 0;
+              "graphics translation table.\n");
 	return 0;
+}
 static int __intel_8xx_fetch_size(u8_t temp)
+{
 	int i;
     aper_size_t *values;
-   // values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
+    values = bridge->aperture_sizes;
 //        curr->is_flushed = TRUE;
 //    }
 //    ret_val = curr->bridge->driver->insert_memory(curr, pg_start, curr->type);
-    u32_t volatile *table = &agp_dev.gatt_table[agp_addr>>12];
+    u32_t volatile *table = &bridge->gatt_table[agp_addr>>12];
     count = size >> 12;
     dma_addr |= 0x00000017;
-    while(count--)
-        addr_t tmp;
     while(count--)
         *table = dma_addr;
-        tmp = *table;                    /* PCI Posting. */
+        *table = dma_addr;
         table++;
         dma_addr+=4096;
+    }
-    agp_dev.tlb_flush(NULL);
+    bridge->tlb_flush(NULL);
 //    if (ret_val != 0)
+//        return ret_val;
+//    curr->is_bound = TRUE;
+//    curr->pg_start = pg_start;
+	return 0;
+}
+void get_agp_version(agp_t *bridge)
+{
+    u32_t ncapid;
+	/* Exit early if already set by errata workarounds. */
+	if (bridge->major_version != 0)
+		return;
+    ncapid = pciReadLong(bridge->PciTag, bridge->capndx);
+	bridge->major_version = (ncapid >> AGP_MAJOR_VERSION_SHIFT) & 0xf;
+	bridge->minor_version = (ncapid >> AGP_MINOR_VERSION_SHIFT) & 0xf;
+}
+static void agp_v2_parse_one(u32_t *requested_mode, u32_t *bridge_agpstat, u32_t *vga_agpstat)
+{
+    u32_t tmp;
+	if (*requested_mode & AGP2_RESERVED_MASK) {
+        dbgprintf("reserved bits set (%x) in mode 0x%x. Fixed.\n",
+			*requested_mode & AGP2_RESERVED_MASK, *requested_mode);
+		*requested_mode &= ~AGP2_RESERVED_MASK;
+	}
+	/* Check the speed bits make sense. Only one should be set. */
+	tmp = *requested_mode & 7;
+	switch (tmp) {
+		case 0:
+            dbgprintf("Setting to x1 mode.\n");
+			*requested_mode |= AGPSTAT2_1X;
+			break;
+		case 1:
+		case 2:
+			break;
+		case 3:
+			*requested_mode &= ~(AGPSTAT2_1X);	/* rate=2 */
+			break;
+		case 4:
+			break;
+		case 5:
+		case 6:
+		case 7:
+			*requested_mode &= ~(AGPSTAT2_1X|AGPSTAT2_2X); /* rate=4*/
+			break;
+	}
+	/* disable SBA if it's not supported */
+	if (!((*bridge_agpstat & AGPSTAT_SBA) && (*vga_agpstat & AGPSTAT_SBA) && (*requested_mode & AGPSTAT_SBA)))
+		*bridge_agpstat &= ~AGPSTAT_SBA;
+	/* Set rate */
+	if (!((*bridge_agpstat & AGPSTAT2_4X) && (*vga_agpstat & AGPSTAT2_4X) && (*requested_mode & AGPSTAT2_4X)))
+		*bridge_agpstat &= ~AGPSTAT2_4X;
+	if (!((*bridge_agpstat & AGPSTAT2_2X) && (*vga_agpstat & AGPSTAT2_2X) && (*requested_mode & AGPSTAT2_2X)))
+		*bridge_agpstat &= ~AGPSTAT2_2X;
+	if (!((*bridge_agpstat & AGPSTAT2_1X) && (*vga_agpstat & AGPSTAT2_1X) && (*requested_mode & AGPSTAT2_1X)))
+		*bridge_agpstat &= ~AGPSTAT2_1X;
+	/* Now we know what mode it should be, clear out the unwanted bits. */
+	if (*bridge_agpstat & AGPSTAT2_4X)
+		*bridge_agpstat &= ~(AGPSTAT2_1X | AGPSTAT2_2X);	/* 4X */
+	if (*bridge_agpstat & AGPSTAT2_2X)
+		*bridge_agpstat &= ~(AGPSTAT2_1X | AGPSTAT2_4X);	/* 2X */
+	if (*bridge_agpstat & AGPSTAT2_1X)
+		*bridge_agpstat &= ~(AGPSTAT2_2X | AGPSTAT2_4X);	/* 1X */
+	/* Apply any errata. */
+    if (bridge->flags & AGP_ERRATA_FASTWRITES)
+		*bridge_agpstat &= ~AGPSTAT_FW;
+    if (bridge->flags & AGP_ERRATA_SBA)
+		*bridge_agpstat &= ~AGPSTAT_SBA;
+    if (bridge->flags & AGP_ERRATA_1X) {
+		*bridge_agpstat &= ~(AGPSTAT2_2X | AGPSTAT2_4X);
+		*bridge_agpstat |= AGPSTAT2_1X;
+	}
+	/* If we've dropped down to 1X, disable fast writes. */
+	if (*bridge_agpstat & AGPSTAT2_1X)
+		*bridge_agpstat &= ~AGPSTAT_FW;
+}
+static void agp_v3_parse_one(u32_t *requested_mode,
+                             u32_t *bridge_agpstat,
+                             u32_t *vga_agpstat)
+{
+    u32_t origbridge = *bridge_agpstat, origvga = *vga_agpstat;
+    u32_t tmp;
+    if (*requested_mode & AGP3_RESERVED_MASK)
+    {
+        dbgprintf("reserved bits set (%x) in mode 0x%x. Fixed.\n",
+			*requested_mode & AGP3_RESERVED_MASK, *requested_mode);
+		*requested_mode &= ~AGP3_RESERVED_MASK;
+	}
+	/* Check the speed bits make sense. */
+	tmp = *requested_mode & 7;
+	if (tmp == 0) {
+        dbgprintf("Setting to AGP3 x4 mode.\n");
+		*requested_mode |= AGPSTAT3_4X;
+	}
+	if (tmp >= 3) {
+        dbgprintf("Setting to AGP3 x8 mode.\n");
+		*requested_mode = (*requested_mode & ~7) | AGPSTAT3_8X;
+	}
+	/* ARQSZ - Set the value to the maximum one.
+	 * Don't allow the mode register to override values. */
+	*bridge_agpstat = ((*bridge_agpstat & ~AGPSTAT_ARQSZ) |
+        max_t(u32_t,(*bridge_agpstat & AGPSTAT_ARQSZ),(*vga_agpstat & AGPSTAT_ARQSZ)));
+	/* Calibration cycle.
+	 * Don't allow the mode register to override values. */
+	*bridge_agpstat = ((*bridge_agpstat & ~AGPSTAT_CAL_MASK) |
+        min_t(u32_t,(*bridge_agpstat & AGPSTAT_CAL_MASK),(*vga_agpstat & AGPSTAT_CAL_MASK)));
+	/* SBA *must* be supported for AGP v3 */
+	*bridge_agpstat |= AGPSTAT_SBA;
+	/*
+	 * Set speed.
+	 * Check for invalid speeds. This can happen when applications
+	 * written before the AGP 3.0 standard pass AGP2.x modes to AGP3 hardware
+	 */
+	if (*requested_mode & AGPSTAT_MODE_3_0) {
+		/*
+		 * Caller hasn't a clue what it is doing. Bridge is in 3.0 mode,
+		 * have been passed a 3.0 mode, but with 2.x speed bits set.
+		 * AGP2.x 4x -> AGP3.0 4x.
+		 */
+		if (*requested_mode & AGPSTAT2_4X) {
+            dbgprintf("broken AGP3 flags (%x). Fixed.\n", *requested_mode);
+			*requested_mode &= ~AGPSTAT2_4X;
+			*requested_mode |= AGPSTAT3_4X;
+		}
+	} else {
+		/*
+		 * The caller doesn't know what they are doing. We are in 3.0 mode,
+		 * but have been passed an AGP 2.x mode.
+		 * Convert AGP 1x,2x,4x -> AGP 3.0 4x.
+		 */
+        dbgprintf("broken AGP2 flags (%x) in AGP3 mode. Fixed.\n",*requested_mode);
+		*requested_mode &= ~(AGPSTAT2_4X | AGPSTAT2_2X | AGPSTAT2_1X);
+		*requested_mode |= AGPSTAT3_4X;
+	}
+	if (*requested_mode & AGPSTAT3_8X) {
+		if (!(*bridge_agpstat & AGPSTAT3_8X)) {
+			*bridge_agpstat &= ~(AGPSTAT3_8X | AGPSTAT3_RSVD);
+			*bridge_agpstat |= AGPSTAT3_4X;
+            dbgprintf("requested AGPx8 but bridge not capable.\n");
+			return;
+		}
+		if (!(*vga_agpstat & AGPSTAT3_8X)) {
+			*bridge_agpstat &= ~(AGPSTAT3_8X | AGPSTAT3_RSVD);
+			*bridge_agpstat |= AGPSTAT3_4X;
+            dbgprintf("requested AGPx8 but graphic card not capable.\n");
+			return;
+		}
+		/* All set, bridge & device can do AGP x8*/
+		*bridge_agpstat &= ~(AGPSTAT3_4X | AGPSTAT3_RSVD);
+		goto done;
+	} else {
+		/*
+		 * If we didn't specify AGPx8, we can only do x4.
+		 * If the hardware can't do x4, we're up shit creek, and never
+		 *  should have got this far.
+		 */
+		*bridge_agpstat &= ~(AGPSTAT3_8X | AGPSTAT3_RSVD);
+		if ((*bridge_agpstat & AGPSTAT3_4X) && (*vga_agpstat & AGPSTAT3_4X))
+			*bridge_agpstat |= AGPSTAT3_4X;
+		else {
+            dbgprintf("Badness. Don't know which AGP mode to set. "
+							"[bridge_agpstat:%x vga_agpstat:%x fell back to:- bridge_agpstat:%x vga_agpstat:%x]\n",
+							origbridge, origvga, *bridge_agpstat, *vga_agpstat);
+			if (!(*bridge_agpstat & AGPSTAT3_4X))
+                dbgprintf("Bridge couldn't do AGP x4.\n");
+			if (!(*vga_agpstat & AGPSTAT3_4X))
+                dbgprintf("Graphic card couldn't do AGP x4.\n");
+			return;
+		}
+	}
+done:
+	/* Apply any errata. */
+    if (bridge->flags & AGP_ERRATA_FASTWRITES)
+		*bridge_agpstat &= ~AGPSTAT_FW;
+    if (bridge->flags & AGP_ERRATA_SBA)
+		*bridge_agpstat &= ~AGPSTAT_SBA;
+    if (bridge->flags & AGP_ERRATA_1X) {
+		*bridge_agpstat &= ~(AGPSTAT2_2X | AGPSTAT2_4X);
+		*bridge_agpstat |= AGPSTAT2_1X;
+	}
+}
+u32_t agp_collect_device_status(agp_t *bridge, u32_t requested_mode,
+                                u32_t bridge_agpstat)
+{
+    PCITAG  vgaTag;
+    u32_t   vga_agpstat;
+    int     cap_ptr;
+    for (;;)
+    {
+        vgaTag = pci_find_class(PCI_CLASS_DISPLAY_VGA);
+        if (vgaTag == -1)
+        {
+            dbgprintf("Couldn't find an AGP VGA controller.\n");
+			return 0;
+		}
+        cap_ptr = pci_find_capability(vgaTag, PCI_CAP_ID_AGP);
+		if (cap_ptr)
+			break;
+	}
+	/*
+	 * Ok, here we have a AGP device. Disable impossible
+	 * settings, and adjust the readqueue to the minimum.
+	 */
+    vga_agpstat = pciReadLong(vgaTag, cap_ptr+PCI_AGP_STATUS);
+	/* adjust RQ depth */
+	bridge_agpstat = ((bridge_agpstat & ~AGPSTAT_RQ_DEPTH) |
+         min_t(u32_t, (requested_mode & AGPSTAT_RQ_DEPTH),
+         min_t(u32_t, (bridge_agpstat & AGPSTAT_RQ_DEPTH), (vga_agpstat & AGPSTAT_RQ_DEPTH))));
+	/* disable FW if it's not supported */
+	if (!((bridge_agpstat & AGPSTAT_FW) &&
+          (vga_agpstat & AGPSTAT_FW) &&
+          (requested_mode & AGPSTAT_FW)))
+		bridge_agpstat &= ~AGPSTAT_FW;
+	/* Check to see if we are operating in 3.0 mode */
+    if (bridge->mode & AGPSTAT_MODE_3_0)
+		agp_v3_parse_one(&requested_mode, &bridge_agpstat, &vga_agpstat);
+	else
+		agp_v2_parse_one(&requested_mode, &bridge_agpstat, &vga_agpstat);
+	return bridge_agpstat;
+}
+void agp_device_command(u32_t bridge_agpstat, int agp_v3)
+{
+    PCITAG device = 0;
+	int mode;
+	mode = bridge_agpstat & 0x7;
+	if (agp_v3)
+		mode *= 4;
+    for_each_pci_dev(device)
+    {
+        int agp = pci_find_capability(device, PCI_CAP_ID_AGP);
+		if (!agp)
+			continue;
+        dbgprintf("Putting AGP V%d device at into %dx mode\n",
+                agp_v3 ? 3 : 2, mode);
+        pciWriteLong(device, agp + PCI_AGP_COMMAND, bridge_agpstat);
+	}
+}
+struct agp_3_5_dev
+{
+    link_t link;
+    int    capndx;
+    u32_t  maxbw;
+    PCITAG tag;
+};
+/*
+ * Fully configure and enable an AGP 3.0 host bridge and all the devices
+ * lying behind it.
+ */
+int agp_3_5_enable(agp_t *bridge)
+{
+    u8_t   mcapndx;
+    u32_t  isoch, arqsz;
+    u32_t  tstatus, mstatus, ncapid;
+    u32_t  mmajor;
+    u16_t  mpstat;
+    link_t dev_list;
+    struct agp_3_5_dev *cur, *pos;
+	unsigned int ndevs = 0;
+    PCITAG dev = 0;
+	int ret = 0;
+	/* Extract some power-on defaults from the target */
+    tstatus = pciReadLong(bridge->PciTag, bridge->capndx+AGPSTAT);
+	isoch     = (tstatus >> 17) & 0x1;
+	if (isoch == 0)	/* isoch xfers not available, bail out. */
+        return -1;
+	arqsz     = (tstatus >> 13) & 0x7;
+    list_initialize(&dev_list);
+	/* Find all AGP devices, and add them to dev_list. */
+    for_each_pci_dev(dev)
+    {
+        u16_t devclass;
+		mcapndx = pci_find_capability(dev, PCI_CAP_ID_AGP);
+		if (mcapndx == 0)
+			continue;
+        devclass = pciReadWord(dev, 0x0A);
+        switch (devclass & 0xff00)
+        {
+			case 0x0600:    /* Bridge */
+				/* Skip bridges. We should call this function for each one. */
+				continue;
+			case 0x0001:    /* Unclassified device */
+				/* Don't know what this is, but log it for investigation. */
+				if (mcapndx != 0) {
+                    dbgprintf("Wacky, found unclassified AGP device.\n");
+				}
+				continue;
+			case 0x0300:    /* Display controller */
+			case 0x0400:    /* Multimedia controller */
+                if((cur = malloc(sizeof(*cur))) == NULL)
+                {
+                    ret = -1;
+					goto free_and_exit;
+				}
+                cur->tag = dev;
+                list_prepend(&cur->link, &dev_list);
+				ndevs++;
+				continue;
+			default:
+				continue;
+		}
+	}
+	/*
+	 * Take an initial pass through the devices lying behind our host
+	 * bridge.  Make sure each one is actually an AGP 3.0 device, otherwise
+	 * exit with an error message.  Along the way store the AGP 3.0
+	 * cap_ptr for each device
+	 */
+    cur = (struct agp_3_5_dev*)dev_list.next;
+    while(&cur->link != &dev_list)
+    {
+        dev = cur->tag;
+        mpstat = pciReadWord(dev, PCI_STATUS);
+		if ((mpstat & PCI_STATUS_CAP_LIST) == 0)
+			continue;
+        mcapndx = pciReadByte(dev, PCI_CAPABILITY_LIST);
+		if (mcapndx != 0) {
+			do {
+                ncapid = pciReadLong(dev, mcapndx);
+				if ((ncapid & 0xff) != 2)
+					mcapndx = (ncapid >> 8) & 0xff;
+			}
+			while (((ncapid & 0xff) != 2) && (mcapndx != 0));
+		}
+		if (mcapndx == 0) {
+            dbgprintf("woah!  Non-AGP device "
+				"found on the secondary bus of an AGP 3.5 bridge!\n");
+            ret = -1;
+			goto free_and_exit;
+		}
+		mmajor = (ncapid >> AGP_MAJOR_VERSION_SHIFT) & 0xf;
+		if (mmajor < 3) {
+            dbgprintf("woah!  AGP 2.0 device "
+				"found on the secondary bus of an AGP 3.5 "
+				"bridge operating with AGP 3.0 electricals!\n");
+            ret = -1;
+			goto free_and_exit;
+		}
+		cur->capndx = mcapndx;
+        mstatus = pciReadLong(dev, cur->capndx+AGPSTAT);
+		if (((mstatus >> 3) & 0x1) == 0) {
+            dbgprintf("woah!  AGP 3.x device "
+				"not operating in AGP 3.x mode found on the "
+				"secondary bus of an AGP 3.5 bridge operating "
+				"with AGP 3.0 electricals!\n");
+            ret = -1;
+			goto free_and_exit;
+		}
+        cur = (struct agp_3_5_dev*)cur->link.next;
+	}
+	/*
+	 * Call functions to divide target resources amongst the AGP 3.0
+	 * masters.  This process is dramatically different depending on
+	 * whether isochronous transfers are supported.
+	 */
+	if (isoch) {
+        ret = agp_3_5_isochronous_node_enable(bridge, &dev_list, ndevs);
+		if (ret) {
+            dbgprintf("Something bad happened setting "
+                      "up isochronous xfers.  Falling back to "
+                      "non-isochronous xfer mode.\n");
+		} else {
+			goto free_and_exit;
+		}
+	}
+	agp_3_5_nonisochronous_node_enable(bridge, dev_list, ndevs);
+free_and_exit:
+	/* Be sure to free the dev_list */
+    for (pos = (struct agp_3_5_dev*)dev_list.next; &pos->link != &dev_list; )
+    {
+        cur = pos;
+        pos = (struct agp_3_5_dev*)pos->link.next;
+        free(cur);
+	}
+get_out:
+	return ret;
+}
+void agp_generic_enable(u32_t requested_mode)
+{
+    u32_t bridge_agpstat, temp;
+    get_agp_version(bridge);
+    dbgprintf("Found an AGP %d.%d compliant device.\n",
+           bridge->major_version, bridge->minor_version);
+    bridge_agpstat = pciReadLong(bridge->PciTag,
+                     bridge->capndx + PCI_AGP_STATUS);
+    bridge_agpstat = agp_collect_device_status(bridge, requested_mode, bridge_agpstat);
+	if (bridge_agpstat == 0)
+		/* Something bad happened. FIXME: Return error code? */
+		return;
+	bridge_agpstat |= AGPSTAT_AGP_ENABLE;
+	/* Do AGP version specific frobbing. */
+    if (bridge->major_version >= 3)
+    {
+        if (bridge->mode & AGPSTAT_MODE_3_0)
+        {
+			/* If we have 3.5, we can do the isoch stuff. */
+            if (bridge->minor_version >= 5)
+                agp_3_5_enable(bridge);
+            agp_device_command(bridge_agpstat, TRUE);
+			return;
+        }
+        else
+        {
+		    /* Disable calibration cycle in RX91<1> when not in AGP3.0 mode of operation.*/
+		    bridge_agpstat &= ~(7<<10) ;
+            temp = pciReadLong(bridge->PciTag, bridge->capndx+AGPCTRL);
+		    temp |= (1<<9);
+            pciWriteLong(bridge->PciTag, bridge->capndx+AGPCTRL, temp);
+            dbgprintf("Device is in legacy mode,"
+                      " falling back to 2.x\n");
 //        return ret_val;
+	}
-//    curr->is_bound = TRUE;
-//    curr->pg_start = pg_start;
+	/* AGP v<3 */
-	return 0;
+    agp_device_command(bridge_agpstat, FALSE);
+}
 static agp_t intel_845_driver =
+{
-//    .aperture_sizes     = intel_8xx_sizes,
+    .aperture_sizes     = intel_8xx_sizes,
 //    .size_type          = U8_APER_SIZE,
 //    .num_aperture_sizes = 7,
     .configure          = intel_845_configure,
     .fetch_size         = intel_8xx_fetch_size,
 //    .cleanup            = intel_8xx_cleanup,
     .tlb_flush          = intel_8xx_tlbflush,
 //    .mask_memory        = agp_generic_mask_memory,
 //    .masks              = intel_generic_masks,
 //    .agp_enable         = agp_generic_enable,
 //    .cache_flush        = global_cache_flush,
-//    .create_gatt_table  = agp_generic_create_gatt_table,
+    .create_gatt_table  = agp_generic_create_gatt_table,
+//    .free_gatt_table    = agp_generic_free_gatt_table,
+//    .insert_memory      = agp_generic_insert_memory,
+//    .remove_memory      = agp_generic_remove_memory,
+//    .alloc_by_type      = agp_generic_alloc_by_type,
+//    .free_by_type       = agp_generic_free_by_type,
+//    .agp_alloc_page     = agp_generic_alloc_page,
+//    .agp_destroy_page   = agp_generic_destroy_page,
+};
+int init_bridge(PCITAG pciTag)
+{
+    size_t size_value;
+    bridge = &intel_845_driver;
+    bridge->PciTag = pciTag;
+    bridge->capndx = pci_find_capability(pciTag, PCI_CAP_ID_AGP);
+    size_value = bridge->fetch_size();
+    if (size_value == 0) {
+        dbgprintf("unable to determine aperture size.\n");
+        return 0;
+    };
+    dbgprintf("fetch size = %x\n", size_value);
 //    .free_gatt_table    = agp_generic_free_gatt_table,

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(root)/programs/system/drivers/agp/agp.c – Rev 948 → 951