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// version 0.02
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// version 0.03
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// Author: Pavel Iakovlev
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// Author: Pavel Iakovlev
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// http://shell-storm.org/online/Online-Assembler-and-Disassembler/?inst=&arch=arm#assembly - online compiler (Little endian:)
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// http://shell-storm.org/online/Online-Assembler-and-Disassembler/?inst=&arch=arm#assembly - online compiler (Little endian:)
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char param[4096] ={0};
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char param[4096] ={0};
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char program_path[4096] = {0};
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char program_path[4096] = {0};
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// test opcode arm, compiler (http://shell-storm.org/online/Online-Assembler-and-Disassembler/?inst=mov+r0%2C1%0D%0Amov+r5%2C2%0D%0Amov+r2%2C+r0%2C+lsl+r5&arch=arm#assembly) (Little endian:)
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// test opcode arm, compiler (http://shell-storm.org/online/Online-Assembler-and-Disassembler/?inst=mov+r0%2C1%0D%0Amov+r5%2C2%0D%0Amov+r2%2C+r0%2C+lsl+r5&arch=arm#assembly) (Little endian:)
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dword test_bytecode = "\x01\x00\xa0\xe3\x02\x50\xa0\xe3\x10\x25\xa0\xe1";
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dword test_bytecode = "\x04\x10\x5f\xe5\x7b\x00\x00\x00";
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_mask mask = {0,0}; // processor mask
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_mask mask = {0,0}; // processor mask
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void main()
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void main()
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{
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{
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	callOpcode(#test_bytecode,3);
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	callOpcode(#test_bytecode,1);
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		command = DSDWORD[binary + PC]; // generation PC instruction
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		command = DSDWORD[binary + PC]; // generation PC instruction
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		//EAX = DSDWORD[command >> 28 << 2 + #opcodeExec]; // get opcodeExecition call instruction
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		//EAX = DSDWORD[command >> 28 << 2 + #opcodeExec]; // get opcodeExecition call instruction
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		//EAX(command); // call opcodeExecition
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		//EAX(command); // call opcodeExecition
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		//IF (command & 0xC000000 == 0) opcodeExec0(command);
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		//IF (command & 0xC000000 == 0) opcodeExec0(command);
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		IF (command & 0x0FFFFFF0 == 0x12FFF10) BranchExchange(command);
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		if (command & 0x0FFFFFF0 == 0x12FFF10) BranchExchange(command);
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		ELSE IF (command & 0x0FF00FF0 == 0x1000090) SingleDataSwap(command);
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		else if (command & 0x0FF00FF0 == 0x1000090) SingleDataSwap(command);
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		ELSE IF (command & 0x0FC000F0 == 0x0000090) Multiply(command);
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		else if (command & 0x0FC000F0 == 0x0000090) Multiply(command);
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		ELSE IF (command & 0x0FC000F0 == 0x0800090) MultiplyLong(command);
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		else if (command & 0x0FC000F0 == 0x0800090) MultiplyLong(command);
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		else if (command & 0x0C000000 == 0x0000000) DataProcessing(command);
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		else if (command & 0xE000010 == 0x6000010) ;// undefined
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		ELSE IF (command & 0x0C000000 == 0x0000000) DataProcessing(command);
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		else if (command & 0xC000000 == 0x4000000) SingleDataTransfer(command, binary);
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		PC += 4; // addition 4 for reg15 or PC instruction
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		PC += 4; // addition 4 for reg15 or PC instruction
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		pMask = 0;
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		pMask = 0;
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		IF (mask.IRQ)  pMask |= 0x2;
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		IF (mask.IRQ)  pMask |= 0x2;
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		IF (mask.FIRQ) pMask |= 0x1;
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		IF (mask.FIRQ) pMask |= 0x1;
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		IF (mode.User)               pMode = 0;
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		if (mode.User)               pMode = 0;
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		ELSE IF (mode.FastInterrupt) pMode = 1;
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		else IF (mode.FastInterrupt) pMode = 1;
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		ELSE IF (mode.Interrupt)     pMode = 2;
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		else IF (mode.Interrupt)     pMode = 2;
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		ELSE IF (mode.Supervisor)    pMode = 3;
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		else IF (mode.Supervisor)    pMode = 3;
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		//reg.r15 = flag << 28 | PC | pMode;
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		//reg.r15 = flag << 28 | PC | pMode;
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dword BranchExchange(dword command)
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dword BranchExchange(dword command)
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{
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{
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}
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dword SingleDataTransfer(dword command, binary)
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{
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	dword Rd = #reg;
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	dword Rn = #reg;
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	dword offset = 0;
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	Rd += command >> 12 & 0xF << 2;
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	Rn += command >> 16 & 0xF << 2;
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	offset = command & 0xFFF;
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	IF (command >> 16 & 0xF != 15) IF (command & 0x800000 == 0) $neg offset;
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	IF (command & 0x400000) // byte
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	{
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		IF (command >> 16 & 0xF == 15)
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		{
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			IF (command & 0x100000) DSDWORD[Rd] = DSBYTE[binary + offset];
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			ELSE DSBYTE[binary + offset] = DSDWORD[Rd];
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		}
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		ELSE
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		{
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			Rn = DSDWORD[Rn];
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			IF (command & 0x2000000 == 0) Rn += offset;
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			IF (command & 0x100000) DSDWORD[Rd] = DSDWORD[binary + Rn];
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			ELSE DSDWORD[binary + Rn] = DSDWORD[Rd];
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		}
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	}
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	ELSE // dword
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	{
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		Rn = DSDWORD[Rn];
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		IF (command & 0x2000000 == 0) Rn += offset;
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		IF (command & 0x100000) DSDWORD[Rd] = DSDWORD[binary + Rn];
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		ELSE DSDWORD[binary + Rn] = DSDWORD[Rd];
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	}
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}
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}
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dword DataProcessing(dword command) // Data Processing / PSR Transfer
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dword DataProcessing(dword command) // Data Processing / PSR Transfer
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{
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{
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	dword opcode = 0;
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	dword opcode = 0;
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	switch (typeSdvig) // type sdvig
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	switch (typeSdvig) // type sdvig
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	{
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	{
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		case 0: // logic left
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		case 0: // logic left
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			operand <<= sdvig;
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			if(sdvig == 2) while(1);
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			operand <<= sdvig;
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		break;
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		break;
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		case 1: // logic right
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		case 1: // logic right
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			operand >>= sdvig;
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			operand >>= sdvig;
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		break;
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		break;
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		break;
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		break;
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		case 15: // mvn
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		case 15: // mvn
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			DSDWORD[Rd] = DSDWORD[Rn] + operand;
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			DSDWORD[Rd] = DSDWORD[Rn] + operand;
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		break;
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		break;
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	}
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	}
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	IF(reg.r2 == 4) while(1);
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}
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}
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