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| 1 | // version 0.01 |
1 | // version 0.02 |
| 2 | // Author: Pavel Iakovlev |
2 | // Author: Pavel Iakovlev |
| - | 3 | // http://shell-storm.org/online/Online-Assembler-and-Disassembler/?inst=&arch=arm#assembly - online compiler (Little endian:) |
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| Line 3... | Line 4... | ||
| 3 | 4 | ||
| 4 | 5 | ||
| 5 | #pragma option OST |
6 | #pragma option OST |
| Line 22... | Line 23... | ||
| 22 | dword I_Param = #param; |
23 | dword I_Param = #param; |
| 23 | dword I_Path = #program_path; |
24 | dword I_Path = #program_path; |
| 24 | char param[4096] ={0}; |
25 | char param[4096] ={0}; |
| 25 | char program_path[4096] = {0}; |
26 | char program_path[4096] = {0}; |
| Line -... | Line 27... | ||
| - | 27 | ||
| - | 28 | // test opcode arm, compiler (http://shell-storm.org/online/Online-Assembler-and-Disassembler/?inst=mov+r0%2C1%0D%0Amov+r5%2C2%0D%0Amov+r2%2C+r0%2C+lsl+r5&arch=arm#assembly) (Little endian:) |
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| 26 | 29 | ||
| - | 30 | dword test_bytecode = "\x01\x00\xa0\xe3\x02\x50\xa0\xe3\x10\x25\xa0\xe1"; |
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| - | 31 | ||
| Line 27... | Line 32... | ||
| 27 | dword test_bytecode = "\x05\x10\x82\xe2\x07\x30\x82\xe2\x03\x20\x81\xe0"; // test opcode arm |
32 | // -------------------- |
| 28 | 33 | ||
| 29 | struct _reg // registers arm |
34 | struct _reg // registers arm |
| 30 | { |
35 | { |
| Line 93... | Line 98... | ||
| 93 | byte flag = 0; |
98 | byte flag = 0; |
| 94 | byte pMask = 0; |
99 | byte pMask = 0; |
| 95 | byte pMode = 0; |
100 | byte pMode = 0; |
| 96 | while(lengthInstruction) |
101 | while(lengthInstruction) |
| 97 | { |
102 | { |
| 98 | PC = reg.r15 >> 2 & 0xFFFFFF; |
103 | //PC = reg.r15 >> 2 & 0xFFFFFF; |
| 99 | flag = reg.r15 >> 28; |
104 | flag = reg.r15 >> 28; |
| 100 | pMask = reg.r15 >> 26; |
105 | pMask = reg.r15 >> 26; |
| Line 101... | Line 106... | ||
| 101 | 106 | ||
| 102 | flags.negative = flag & 0x8; |
107 | flags.negative = flag & 0x8; |
| Line 132... | Line 137... | ||
| 132 | ELSE IF (command & 0x0FC000F0 == 0x0000090) Multiply(command); |
137 | ELSE IF (command & 0x0FC000F0 == 0x0000090) Multiply(command); |
| 133 | ELSE IF (command & 0x0FC000F0 == 0x0800090) MultiplyLong(command); |
138 | ELSE IF (command & 0x0FC000F0 == 0x0800090) MultiplyLong(command); |
| 134 | ELSE IF (command & 0x0C000000 == 0x0000000) DataProcessing(command); |
139 | ELSE IF (command & 0x0C000000 == 0x0000000) DataProcessing(command); |
| Line 135... | Line 140... | ||
| 135 | 140 | ||
| 136 | PC += 4; // addition 4 for reg15 or PC instruction |
141 | PC += 4; // addition 4 for reg15 or PC instruction |
| Line 137... | Line 142... | ||
| 137 | PC <<= 2; |
142 | //PC <<= 2; |
| 138 | 143 | ||
| 139 | flag = 0; |
144 | flag = 0; |
| 140 | IF (flags.negative) flag |= 0x8; |
145 | IF (flags.negative) flag |= 0x8; |
| Line 149... | Line 154... | ||
| 149 | IF (mode.User) pMode = 0; |
154 | IF (mode.User) pMode = 0; |
| 150 | ELSE IF (mode.FastInterrupt) pMode = 1; |
155 | ELSE IF (mode.FastInterrupt) pMode = 1; |
| 151 | ELSE IF (mode.Interrupt) pMode = 2; |
156 | ELSE IF (mode.Interrupt) pMode = 2; |
| 152 | ELSE IF (mode.Supervisor) pMode = 3; |
157 | ELSE IF (mode.Supervisor) pMode = 3; |
| Line 153... | Line 158... | ||
| 153 | 158 | ||
| 154 | reg.r15 = flag << 28 | PC | pMode; |
159 | //reg.r15 = flag << 28 | PC | pMode; |
| 155 | lengthInstruction--; |
160 | lengthInstruction--; |
| 156 | } |
161 | } |
| Line 157... | Line 162... | ||
| 157 | } |
162 | } |
| Line 180... | Line 185... | ||
| 180 | { |
185 | { |
| 181 | dword opcode = 0; |
186 | dword opcode = 0; |
| 182 | dword Rd = #reg; |
187 | dword Rd = #reg; |
| 183 | dword Rn = #reg; |
188 | dword Rn = #reg; |
| 184 | dword operand = 0; |
189 | dword operand = 0; |
| - | 190 | word sdvig = 0; |
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| - | 191 | word context = 0; |
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| - | 192 | byte typeSdvig = 0; |
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| 185 | opcode = command >> 21 & 0xF; |
193 | opcode = command >> 21 & 0xF; |
| 186 | Rd += command >> 12 & 0xF << 2; |
194 | Rd += command >> 12 & 0xF << 2; |
| 187 | Rn += command >> 16 & 0xF << 2; |
195 | Rn += command >> 16 & 0xF << 2; |
| 188 | operand = command & 0xFFF; |
196 | context = command & 0xFFF; |
| - | 197 | ||
| - | 198 | IF (command & 0x2000000) operand = context; |
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| - | 199 | ELSE operand = DSDWORD[context & 1111b << 2 + #reg]; |
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| - | 200 | ||
| - | 201 | typeSdvig = context >> 5 & 11b; |
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| - | 202 | IF (context & 10000b) sdvig = DSBYTE[context >> 8 & 1111b << 2 + #reg]; |
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| - | 203 | ELSE sdvig = context >> 7 & 11111b; |
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| Line 189... | Line 204... | ||
| 189 | 204 | ||
| 190 | IF (command & 0x2000000 == 0) |
205 | switch (typeSdvig) // type sdvig |
| - | 206 | { |
|
| 191 | { |
207 | case 0: // logic left |
| - | 208 | operand <<= sdvig; |
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| - | 209 | if(sdvig == 2) while(1); |
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| - | 210 | break; |
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| - | 211 | case 1: // logic right |
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| - | 212 | operand >>= sdvig; |
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| - | 213 | break; |
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| - | 214 | case 2: // arifmetic left |
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| - | 215 | ||
| - | 216 | break; |
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| - | 217 | case 3: // arifmetic right |
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| - | 218 | ||
| 192 | operand = DSDWORD[operand << 2 + #reg]; |
219 | break; |
| Line 193... | Line 220... | ||
| 193 | } |
220 | } |
| 194 | 221 | ||
| 195 | switch (opcode) |
222 | switch (opcode) |
| Line 207... | Line 234... | ||
| 207 | DSDWORD[Rd] = operand - DSDWORD[Rn]; |
234 | DSDWORD[Rd] = operand - DSDWORD[Rn]; |
| 208 | break; |
235 | break; |
| 209 | case 4: // add |
236 | case 4: // add |
| 210 | DSDWORD[Rd] = DSDWORD[Rn] + operand; |
237 | DSDWORD[Rd] = DSDWORD[Rn] + operand; |
| 211 | break; |
238 | break; |
| - | 239 | case 5: // adc |
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| - | 240 | DSDWORD[Rd] = DSDWORD[Rn] + operand; |
|
| - | 241 | break; |
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| - | 242 | case 6: // sbc |
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| - | 243 | ||
| - | 244 | break; |
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| - | 245 | case 7: // rsc |
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| - | 246 | ||
| - | 247 | break; |
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| - | 248 | case 8: // tst |
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| - | 249 | ||
| - | 250 | break; |
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| - | 251 | case 9: // teq |
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| - | 252 | ||
| - | 253 | break; |
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| - | 254 | case 10: // cmp |
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| - | 255 | ||
| - | 256 | break; |
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| - | 257 | case 11: // cmn |
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| - | 258 | ||
| - | 259 | break; |
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| - | 260 | case 12: // orr |
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| - | 261 | DSDWORD[Rd] = DSDWORD[Rn] | operand; |
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| - | 262 | break; |
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| - | 263 | case 13: // mov |
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| - | 264 | DSDWORD[Rd] = operand; |
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| - | 265 | break; |
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| - | 266 | case 14: // bic |
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| - | 267 | $not operand; |
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| - | 268 | DSDWORD[Rd] = DSDWORD[Rn] & operand; |
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| - | 269 | break; |
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| - | 270 | case 15: // mvn |
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| - | 271 | DSDWORD[Rd] = DSDWORD[Rn] + operand; |
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| - | 272 | break; |
|
| 212 | } |
273 | } |
| 213 | IF(reg.r2 == 12) while(1); |
274 | IF(reg.r2 == 4) while(1); |
| 214 | } |
275 | } |
| Line 215... | Line 276... | ||
| 215 | 276 | ||
| 216 | 277 | ||