WebSVN – Kolibri OS – Diff – /kernel/trunk/detect/init_ata.inc


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                              ;;
;; Copyright (C) KolibriOS team 2014-2015. All rights reserved. ;;
;; Distributed under terms of the GNU General Public License    ;;
;;                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
$Revision: 6015 $
 
 
;-----------------------------------------------------------------------------
; find the IDE controller in the device list
;-----------------------------------------------------------------------------
        mov     ecx, IDE_controller_1
        mov     esi, pcidev_list
;--------------------------------------
align 4
.loop:
        mov     esi, [esi+PCIDEV.fd]
        cmp     esi, pcidev_list
        jz      find_IDE_controller_done
 
        mov     eax, [esi+PCIDEV.class]
;        shr     eax, 4
;        cmp     eax, 0x01018
        shr     eax, 7
        cmp     eax, 0x010180 shr 7
        jnz     .loop
;--------------------------------------
.found:
        mov     eax, [esi+PCIDEV.class]
        DEBUGF  1, 'K : IDE controller programming interface %x\n', eax
        mov     [ecx+IDE_DATA.ProgrammingInterface], eax
 
        mov     ah, [esi+PCIDEV.bus]
        mov     al, 2
        mov     bh, [esi+PCIDEV.devfn]
;--------------------------------------
        mov     dx, 0x1F0
        test    byte [esi+PCIDEV.class], 1
        jz      @f
        mov     bl, 0x10
        push    eax
        call    pci_read_reg
        and     eax, 0xFFFC
        mov     edx, eax
        pop     eax
@@:
        DEBUGF  1, 'K : BAR0 IDE base addr %x\n', dx
        mov     [StandardATABases], dx
        mov     [ecx+IDE_DATA.BAR0_val], dx
;--------------------------------------
        mov     dx, 0x3F4
        test    byte [esi+PCIDEV.class], 1
        jz      @f
        mov     bl, 0x14
        push    eax
        call    pci_read_reg
        and     eax, 0xFFFC
        mov     edx, eax
        pop     eax
@@:
        DEBUGF  1, 'K : BAR1 IDE base addr %x\n', dx
        mov     [ecx+IDE_DATA.BAR1_val], dx
;--------------------------------------
        mov     dx, 0x170
        test    byte [esi+PCIDEV.class], 4
        jz      @f
        mov     bl, 0x18
        push    eax
        call    pci_read_reg
        and     eax, 0xFFFC
        mov     edx, eax
        pop     eax
@@:
        DEBUGF  1, 'K : BAR2 IDE base addr %x\n', dx
        mov     [StandardATABases+2], dx
        mov     [ecx+IDE_DATA.BAR2_val], dx
;--------------------------------------
        mov     dx, 0x374
        test    byte [esi+PCIDEV.class], 4
        jz      @f
        mov     bl, 0x1C
        push    eax
        call    pci_read_reg
        and     eax, 0xFFFC
        mov     edx, eax
        pop     eax
@@:
        DEBUGF  1, 'K : BAR3 IDE base addr %x\n', dx
        mov     [ecx+IDE_DATA.BAR3_val], dx
;--------------------------------------
        mov     bl, 0x20
        push    eax
        call    pci_read_reg
        and     eax, 0xFFFC
        DEBUGF  1, 'K : BAR4 IDE controller register base addr %x\n', ax
        mov     [ecx+IDE_DATA.RegsBaseAddres], ax
        pop     eax
;--------------------------------------
        mov     bl, 0x3C
        push    eax
        call    pci_read_reg
        and     eax, 0xFF
        DEBUGF  1, 'K : IDE Interrupt %x\n', al
        mov     [ecx+IDE_DATA.Interrupt], ax
        pop     eax
 
        add     ecx, sizeof.IDE_DATA
;--------------------------------------
        jmp     .loop
;-----------------------------------------------------------------------------
uglobal
align 4
;--------------------------------------
IDE_controller_pointer dd ?
;--------------------------------------
IDE_controller_1 IDE_DATA
IDE_controller_2 IDE_DATA
IDE_controller_3 IDE_DATA
;--------------------------------------
cache_ide0  IDE_CACHE
cache_ide1  IDE_CACHE
cache_ide2  IDE_CACHE
cache_ide3  IDE_CACHE
cache_ide4  IDE_CACHE
cache_ide5  IDE_CACHE
cache_ide6  IDE_CACHE
cache_ide7  IDE_CACHE
cache_ide8  IDE_CACHE
cache_ide9  IDE_CACHE
cache_ide10 IDE_CACHE
cache_ide11 IDE_CACHE
;--------------------------------------
IDE_device_1 rd 2
IDE_device_2 rd 2
IDE_device_3 rd 2
;--------------------------------------
endg
;-----------------------------------------------------------------------------
; START of initialisation IDE ATA code
;-----------------------------------------------------------------------------
Init_IDE_ATA_controller:
        cmp     [ecx+IDE_DATA.ProgrammingInterface], 0
        jne     @f
 
        ret
;--------------------------------------
@@:
        mov     esi, boot_disabling_ide
        call    boot_log
;--------------------------------------
; Disable IDE interrupts, because the search
; for IDE partitions is in the PIO mode.
;--------------------------------------
.disable_IDE_interrupt:
; Disable interrupts in IDE controller for PIO
        mov     al, 2
        mov     dx, [ecx+IDE_DATA.BAR1_val] ;0x3F4
        add     dx, 2 ;0x3F6
        out     dx, al
        mov     dx, [ecx+IDE_DATA.BAR3_val] ;0x374
        add     dx, 2 ;0x376
        out     dx, al
;-----------------------------------------------------------------------------
; set current ata bases
@@:
        mov     ax, [ecx+IDE_DATA.BAR0_val]
        mov     [StandardATABases], ax
        mov     ax, [ecx+IDE_DATA.BAR2_val]
        mov     [StandardATABases+2], ax
 
        mov     esi, boot_detecthdcd
        call    boot_log
;--------------------------------------
include 'dev_hdcd.inc'
;--------------------------------------
        ret
;-----------------------------------------------------------------------------
Init_IDE_ATA_controller_2:
        cmp     [ecx+IDE_DATA.ProgrammingInterface], 0
        jne     @f
 
        ret
;--------------------------------------
@@:
        mov     dx, [ecx+IDE_DATA.RegsBaseAddres]
; test whether it is our interrupt?
        add     dx, 2
        in      al, dx
        test    al, 100b
        jz      @f
; clear Bus Master IDE Status register
; clear Interrupt bit
        out     dx, al
;--------------------------------------
@@:
        add     dx, 8
; test whether it is our interrupt?
        in      al, dx
        test    al, 100b
        jz      @f
; clear Bus Master IDE Status register
; clear Interrupt bit
        out     dx, al
;--------------------------------------
@@:
; read status register and remove the interrupt request
        mov     dx, [ecx+IDE_DATA.BAR0_val] ;0x1F0
        add     dx, 0x7 ;0x1F7
        in      al, dx
        mov     dx, [ecx+IDE_DATA.BAR2_val] ;0x170
        add     dx, 0x7 ;0x177
        in      al, dx
;-----------------------------------------------------------------------------
;        push    eax edx
;        mov     dx, [ecx+IDE_DATA.RegsBaseAddres]
;        xor     eax, eax
;        add     dx, 2
;        in      al, dx
;        DEBUGF  1, "K : Primary Bus Master IDE Status Register %x\n", eax
 
;        add     dx, 8
;        in      al, dx
;        DEBUGF  1, "K : Secondary Bus Master IDE Status Register %x\n", eax
;        pop     edx eax
 
;        cmp     [ecx+IDE_DATA.RegsBaseAddres], 0
;        setnz   [ecx+IDE_DATA.dma_hdd]
;-----------------------------------------------------------------------------
; set interrupts for IDE Controller
;-----------------------------------------------------------------------------
        pushfd
        cli
.enable_IDE_interrupt:
        mov     esi, boot_enabling_ide
        call    boot_log
; Enable interrupts in IDE controller for DMA
        xor     ebx, ebx
        cmp     ecx, IDE_controller_2
        jne     @f
 
        add     ebx, 5
        jmp     .check_DRIVE_DATA
;--------------------------------------
@@:
        cmp     ecx, IDE_controller_3
        jne     .check_DRIVE_DATA
 
        add     ebx, 10
;--------------------------------------
.check_DRIVE_DATA:
        mov     al, 0
        mov     ah, [ebx+DRIVE_DATA+1]
        test    ah, 10100000b ; check for ATAPI devices
        jz      @f
;--------------------------------------
.ch1_pio_set_ATAPI:
        DEBUGF  1, "K : IDE CH1 PIO, because ATAPI drive present\n"
        jmp     .ch1_pio_set_for_all
;--------------------------------------
.ch1_pio_set_no_devices:
        DEBUGF  1, "K : IDE CH1 PIO because no devices\n"
        jmp     .ch1_pio_set_for_all
;-------------------------------------
.ch1_pio_set:
        DEBUGF  1, "K : IDE CH1 PIO because device not support UDMA\n"
;-------------------------------------
.ch1_pio_set_for_all:
        mov     [ecx+IDE_DATA.dma_hdd_channel_1], al
        jmp     .ch2_check
;--------------------------------------
@@:
        xor     ebx, ebx
        call    calculate_IDE_device_values_storage
 
        test    ah, 1010000b
        jz      .ch1_pio_set_no_devices
 
        test    ah, 1000000b
        jz      @f
 
        cmp     [ebx+IDE_DEVICE.UDMA_possible_modes], al
        je      .ch1_pio_set
 
        cmp     [ebx+IDE_DEVICE.UDMA_set_mode], al
        je      .ch1_pio_set
;--------------------------------------
@@:
        test    ah, 10000b
        jz      @f
 
        add     ebx, 2
 
        cmp     [ebx+IDE_DEVICE.UDMA_possible_modes], al
        je      .ch1_pio_set
 
        cmp     [ebx+IDE_DEVICE.UDMA_set_mode], al
        je      .ch1_pio_set
;--------------------------------------
@@:
        mov     dx, [ecx+IDE_DATA.BAR1_val] ;0x3F4
        add     dx, 2 ;0x3F6
        out     dx, al
        DEBUGF  1, "K : IDE CH1 DMA enabled\n"
        mov     [ecx+IDE_DATA.dma_hdd_channel_1], byte 1
;--------------------------------------
.ch2_check:
        test    ah, 1010b ; check for ATAPI devices
        jz      @f
;--------------------------------------
.ch2_pio_set_ATAPI:
        DEBUGF  1, "K : IDE CH2 PIO, because ATAPI drive present\n"
        jmp     .ch2_pio_set_for_all
;--------------------------------------
.ch2_pio_set_no_devices:
        DEBUGF  1, "K : IDE CH2 PIO because no devices\n"
        jmp     .ch2_pio_set_for_all
;--------------------------------------
.ch2_pio_set:
        DEBUGF  1, "K : IDE CH2 PIO because device not support UDMA\n"
;--------------------------------------
.ch2_pio_set_for_all:
        mov     [ecx+IDE_DATA.dma_hdd_channel_2], al
        jmp     .set_interrupts_for_IDE_controllers
;--------------------------------------
@@:
        mov     ebx, 4
        call    calculate_IDE_device_values_storage
 
        test    ah, 101b
        jz      .ch2_pio_set_no_devices
 
        test    ah, 100b
        jz      @f
 
        cmp     [ebx+IDE_DEVICE.UDMA_possible_modes], al
        je      .ch2_pio_set
 
        cmp     [ebx+IDE_DEVICE.UDMA_set_mode], al
        je      .ch2_pio_set
;--------------------------------------
@@:
        test    ah, 1b
        jz      @f
 
        add     ebx, 2
 
        cmp     [ebx+IDE_DEVICE.UDMA_possible_modes], al
        je      .ch2_pio_set
 
        cmp     [ebx+IDE_DEVICE.UDMA_set_mode], al
        je      .ch2_pio_set
;--------------------------------------
@@:
        mov     dx, [ecx+IDE_DATA.BAR3_val] ;0x374
        add     dx, 2 ;0x376
        out     dx, al
        DEBUGF  1, "K : IDE CH2 DMA enabled\n"
        mov     [ecx+IDE_DATA.dma_hdd_channel_2], byte 1
;--------------------------------------
.set_interrupts_for_IDE_controllers:
        mov     esi, boot_set_int_IDE
        call    boot_log
;--------------------------------------
        mov     eax, [ecx+IDE_DATA.ProgrammingInterface]
;        cmp     ax, 0x0180
;        je      .pata_ide
 
;        cmp     ax, 0x018a
;        jne     .sata_ide
 
        test    al, 1 ; 0 - legacy PCI mode, 1 - native PCI mode
        jnz     .sata_ide
;--------------------------------------
.pata_ide:
        cmp     [ecx+IDE_DATA.RegsBaseAddres], 0
        je      .end_set_interrupts
 
        push    ecx
        stdcall attach_int_handler, 14, IDE_irq_14_handler, ecx
        pop     ecx
        DEBUGF  1, "K : Set IDE IRQ14 return code %x\n", eax
        push    ecx
        stdcall attach_int_handler, 15, IDE_irq_15_handler, ecx
        DEBUGF  1, "K : Set IDE IRQ15 return code %x\n", eax
        pop     ecx
 
        jmp     .end_set_interrupts
;--------------------------------------
.sata_ide:
;        cmp     ax, 0x0185
;        je      .sata_ide_1
 
;        cmp     ax, 0x018f
;        jne     .end_set_interrupts
;--------------------------------------
;.sata_ide_1:
; Some weird controllers generate an interrupt even if IDE interrupts
; are disabled and no IDE devices. For example, notebook ASUS K72F -
; IDE controller 010185 generates false interrupt when we work with
; the IDE controller 01018f. For this reason, the interrupt handler
; does not need to be installed if both channel IDE controller
; running in PIO mode.
 
; ...unfortunately, PCI interrupt can be shared with other devices
; which could enable it without consulting IDE code.
; So install the handler anyways and try to process
; even those interrupts which we are not expecting.
        cmp     [ecx+IDE_DATA.RegsBaseAddres], 0
        je      .end_set_interrupts
 
 
 
 
 
 
 
 
        mov     ax, [ecx+IDE_DATA.Interrupt]
        movzx   eax, al
        push    ecx
        stdcall attach_int_handler, eax, IDE_common_irq_handler, ecx
        pop     ecx
        DEBUGF  1, "K : Set IDE IRQ%d return code %x\n", [ecx+IDE_DATA.Interrupt]:1, eax
;--------------------------------------
.end_set_interrupts:
        popfd
        ret
;-----------------------------------------------------------------------------
; END of initialisation IDE ATA code
;-----------------------------------------------------------------------------
find_IDE_controller_done:
        mov     ecx, IDE_controller_1
        mov     [IDE_controller_pointer], ecx
        call    Init_IDE_ATA_controller
        mov     ecx, IDE_controller_2
        mov     [IDE_controller_pointer], ecx
        call    Init_IDE_ATA_controller
        mov     ecx, IDE_controller_3
        mov     [IDE_controller_pointer], ecx
        call    Init_IDE_ATA_controller
;-----------------------------------------------------------------------------
        mov     esi, boot_getcache
        call    boot_log
include 'getcache.inc'
;-----------------------------------------------------------------------------
        mov     esi, boot_detectpart
        call    boot_log
include 'sear_par.inc'
;-----------------------------------------------------------------------------
        mov     esi, boot_init_sys
        call    boot_log
        call    Parser_params
 
if ~ defined extended_primary_loader
; ramdisk image should be loaded by extended primary loader if it exists
; READ RAMDISK IMAGE FROM HD
include '../boot/rdload.inc'
end if
;-----------------------------------------------------------------------------
        mov     ecx, IDE_controller_1
        mov     [IDE_controller_pointer], ecx
        call    Init_IDE_ATA_controller_2
        mov     ecx, IDE_controller_2
        mov     [IDE_controller_pointer], ecx
        call    Init_IDE_ATA_controller_2
        mov     ecx, IDE_controller_3
        mov     [IDE_controller_pointer], ecx
        call    Init_IDE_ATA_controller_2
;-----------------------------------------------------------------------------

Rev 5363	Rev 6015
1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2	;; ;;	2	;; ;;
3	;; Copyright (C) KolibriOS team 2014-2015. All rights reserved. ;;	3	;; Copyright (C) KolibriOS team 2014-2015. All rights reserved. ;;
4	;; Distributed under terms of the GNU General Public License ;;	4	;; Distributed under terms of the GNU General Public License ;;
5	;; ;;	5	;; ;;
6	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	6	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7		7
8	$Revision: 5363 $	8	$Revision: 6015 $
9		9
10		10
11	;-----------------------------------------------------------------------------	11	;-----------------------------------------------------------------------------
12	; find the IDE controller in the device list	12	; find the IDE controller in the device list
13	;-----------------------------------------------------------------------------	13	;-----------------------------------------------------------------------------
14	mov ecx, IDE_controller_1	14	mov ecx, IDE_controller_1
15	mov esi, pcidev_list	15	mov esi, pcidev_list
16	;--------------------------------------	16	;--------------------------------------
17	align 4	17	align 4
18	.loop:	18	.loop:
19	mov esi, [esi+PCIDEV.fd]	19	mov esi, [esi+PCIDEV.fd]
20	cmp esi, pcidev_list	20	cmp esi, pcidev_list
21	jz find_IDE_controller_done	21	jz find_IDE_controller_done
22		22
23	mov eax, [esi+PCIDEV.class]	23	mov eax, [esi+PCIDEV.class]
24	; shr eax, 4	24	; shr eax, 4
25	; cmp eax, 0x01018	25	; cmp eax, 0x01018
26	shr eax, 7	26	shr eax, 7
27	cmp eax, 0x010180 shr 7	27	cmp eax, 0x010180 shr 7
28	jnz .loop	28	jnz .loop
29	;--------------------------------------	29	;--------------------------------------
30	.found:	30	.found:
31	mov eax, [esi+PCIDEV.class]	31	mov eax, [esi+PCIDEV.class]
32	DEBUGF 1, 'K : IDE controller programming interface %x\n', eax	32	DEBUGF 1, 'K : IDE controller programming interface %x\n', eax
33	mov [ecx+IDE_DATA.ProgrammingInterface], eax	33	mov [ecx+IDE_DATA.ProgrammingInterface], eax
34		34
35	mov ah, [esi+PCIDEV.bus]	35	mov ah, [esi+PCIDEV.bus]
36	mov al, 2	36	mov al, 2
37	mov bh, [esi+PCIDEV.devfn]	37	mov bh, [esi+PCIDEV.devfn]
38	;--------------------------------------	38	;--------------------------------------
39	mov dx, 0x1F0	39	mov dx, 0x1F0
40	test byte [esi+PCIDEV.class], 1	40	test byte [esi+PCIDEV.class], 1
41	jz @f	41	jz @f
42	mov bl, 0x10	42	mov bl, 0x10
43	push eax	43	push eax
44	call pci_read_reg	44	call pci_read_reg
45	and eax, 0xFFFC	45	and eax, 0xFFFC
46	mov edx, eax	46	mov edx, eax
47	pop eax	47	pop eax
48	@@:	48	@@:
49	DEBUGF 1, 'K : BAR0 IDE base addr %x\n', dx	49	DEBUGF 1, 'K : BAR0 IDE base addr %x\n', dx
50	mov [StandardATABases], dx	50	mov [StandardATABases], dx
51	mov [ecx+IDE_DATA.BAR0_val], dx	51	mov [ecx+IDE_DATA.BAR0_val], dx
52	;--------------------------------------	52	;--------------------------------------
53	mov dx, 0x3F4	53	mov dx, 0x3F4
54	test byte [esi+PCIDEV.class], 1	54	test byte [esi+PCIDEV.class], 1
55	jz @f	55	jz @f
56	mov bl, 0x14	56	mov bl, 0x14
57	push eax	57	push eax
58	call pci_read_reg	58	call pci_read_reg
59	and eax, 0xFFFC	59	and eax, 0xFFFC
60	mov edx, eax	60	mov edx, eax
61	pop eax	61	pop eax
62	@@:	62	@@:
63	DEBUGF 1, 'K : BAR1 IDE base addr %x\n', dx	63	DEBUGF 1, 'K : BAR1 IDE base addr %x\n', dx
64	mov [ecx+IDE_DATA.BAR1_val], dx	64	mov [ecx+IDE_DATA.BAR1_val], dx
65	;--------------------------------------	65	;--------------------------------------
66	mov dx, 0x170	66	mov dx, 0x170
67	test byte [esi+PCIDEV.class], 4	67	test byte [esi+PCIDEV.class], 4
68	jz @f	68	jz @f
69	mov bl, 0x18	69	mov bl, 0x18
70	push eax	70	push eax
71	call pci_read_reg	71	call pci_read_reg
72	and eax, 0xFFFC	72	and eax, 0xFFFC
73	mov edx, eax	73	mov edx, eax
74	pop eax	74	pop eax
75	@@:	75	@@:
76	DEBUGF 1, 'K : BAR2 IDE base addr %x\n', dx	76	DEBUGF 1, 'K : BAR2 IDE base addr %x\n', dx
77	mov [StandardATABases+2], dx	77	mov [StandardATABases+2], dx
78	mov [ecx+IDE_DATA.BAR2_val], dx	78	mov [ecx+IDE_DATA.BAR2_val], dx
79	;--------------------------------------	79	;--------------------------------------
80	mov dx, 0x374	80	mov dx, 0x374
81	test byte [esi+PCIDEV.class], 4	81	test byte [esi+PCIDEV.class], 4
82	jz @f	82	jz @f
83	mov bl, 0x1C	83	mov bl, 0x1C
84	push eax	84	push eax
85	call pci_read_reg	85	call pci_read_reg
86	and eax, 0xFFFC	86	and eax, 0xFFFC
87	mov edx, eax	87	mov edx, eax
88	pop eax	88	pop eax
89	@@:	89	@@:
90	DEBUGF 1, 'K : BAR3 IDE base addr %x\n', dx	90	DEBUGF 1, 'K : BAR3 IDE base addr %x\n', dx
91	mov [ecx+IDE_DATA.BAR3_val], dx	91	mov [ecx+IDE_DATA.BAR3_val], dx
92	;--------------------------------------	92	;--------------------------------------
93	mov bl, 0x20	93	mov bl, 0x20
94	push eax	94	push eax
95	call pci_read_reg	95	call pci_read_reg
96	and eax, 0xFFFC	96	and eax, 0xFFFC
97	DEBUGF 1, 'K : BAR4 IDE controller register base addr %x\n', ax	97	DEBUGF 1, 'K : BAR4 IDE controller register base addr %x\n', ax
98	mov [ecx+IDE_DATA.RegsBaseAddres], ax	98	mov [ecx+IDE_DATA.RegsBaseAddres], ax
99	pop eax	99	pop eax
100	;--------------------------------------	100	;--------------------------------------
101	mov bl, 0x3C	101	mov bl, 0x3C
102	push eax	102	push eax
103	call pci_read_reg	103	call pci_read_reg
104	and eax, 0xFF	104	and eax, 0xFF
105	DEBUGF 1, 'K : IDE Interrupt %x\n', al	105	DEBUGF 1, 'K : IDE Interrupt %x\n', al
106	mov [ecx+IDE_DATA.Interrupt], ax	106	mov [ecx+IDE_DATA.Interrupt], ax
107	pop eax	107	pop eax
108		108
109	add ecx, sizeof.IDE_DATA	109	add ecx, sizeof.IDE_DATA
110	;--------------------------------------	110	;--------------------------------------
111	jmp .loop	111	jmp .loop
112	;-----------------------------------------------------------------------------	112	;-----------------------------------------------------------------------------
113	uglobal	113	uglobal
114	align 4	114	align 4
115	;--------------------------------------	115	;--------------------------------------
116	IDE_controller_pointer dd ?	116	IDE_controller_pointer dd ?
117	;--------------------------------------	117	;--------------------------------------
118	IDE_controller_1 IDE_DATA	118	IDE_controller_1 IDE_DATA
119	IDE_controller_2 IDE_DATA	119	IDE_controller_2 IDE_DATA
120	IDE_controller_3 IDE_DATA	120	IDE_controller_3 IDE_DATA
121	;--------------------------------------	121	;--------------------------------------
122	cache_ide0 IDE_CACHE	122	cache_ide0 IDE_CACHE
123	cache_ide1 IDE_CACHE	123	cache_ide1 IDE_CACHE
124	cache_ide2 IDE_CACHE	124	cache_ide2 IDE_CACHE
125	cache_ide3 IDE_CACHE	125	cache_ide3 IDE_CACHE
126	cache_ide4 IDE_CACHE	126	cache_ide4 IDE_CACHE
127	cache_ide5 IDE_CACHE	127	cache_ide5 IDE_CACHE
128	cache_ide6 IDE_CACHE	128	cache_ide6 IDE_CACHE
129	cache_ide7 IDE_CACHE	129	cache_ide7 IDE_CACHE
130	cache_ide8 IDE_CACHE	130	cache_ide8 IDE_CACHE
131	cache_ide9 IDE_CACHE	131	cache_ide9 IDE_CACHE
132	cache_ide10 IDE_CACHE	132	cache_ide10 IDE_CACHE
133	cache_ide11 IDE_CACHE	133	cache_ide11 IDE_CACHE
134	;--------------------------------------	134	;--------------------------------------
135	IDE_device_1 rd 2	135	IDE_device_1 rd 2
136	IDE_device_2 rd 2	136	IDE_device_2 rd 2
137	IDE_device_3 rd 2	137	IDE_device_3 rd 2
138	;--------------------------------------	138	;--------------------------------------
139	endg	139	endg
140	;-----------------------------------------------------------------------------	140	;-----------------------------------------------------------------------------
141	; START of initialisation IDE ATA code	141	; START of initialisation IDE ATA code
142	;-----------------------------------------------------------------------------	142	;-----------------------------------------------------------------------------
143	Init_IDE_ATA_controller:	143	Init_IDE_ATA_controller:
144	cmp [ecx+IDE_DATA.ProgrammingInterface], 0	144	cmp [ecx+IDE_DATA.ProgrammingInterface], 0
145	jne @f	145	jne @f
146		146
147	ret	147	ret
148	;--------------------------------------	148	;--------------------------------------
149	@@:	149	@@:
150	mov esi, boot_disabling_ide	150	mov esi, boot_disabling_ide
151	call boot_log	151	call boot_log
152	;--------------------------------------	152	;--------------------------------------
153	; Disable IDE interrupts, because the search	153	; Disable IDE interrupts, because the search
154	; for IDE partitions is in the PIO mode.	154	; for IDE partitions is in the PIO mode.
155	;--------------------------------------	155	;--------------------------------------
156	.disable_IDE_interrupt:	156	.disable_IDE_interrupt:
157	; Disable interrupts in IDE controller for PIO	157	; Disable interrupts in IDE controller for PIO
158	mov al, 2	158	mov al, 2
159	mov dx, [ecx+IDE_DATA.BAR1_val] ;0x3F4	159	mov dx, [ecx+IDE_DATA.BAR1_val] ;0x3F4
160	add dx, 2 ;0x3F6	160	add dx, 2 ;0x3F6
161	out dx, al	161	out dx, al
162	mov dx, [ecx+IDE_DATA.BAR3_val] ;0x374	162	mov dx, [ecx+IDE_DATA.BAR3_val] ;0x374
163	add dx, 2 ;0x376	163	add dx, 2 ;0x376
164	out dx, al	164	out dx, al
165	;-----------------------------------------------------------------------------	165	;-----------------------------------------------------------------------------
166	; set current ata bases	166	; set current ata bases
167	@@:	167	@@:
168	mov ax, [ecx+IDE_DATA.BAR0_val]	168	mov ax, [ecx+IDE_DATA.BAR0_val]
169	mov [StandardATABases], ax	169	mov [StandardATABases], ax
170	mov ax, [ecx+IDE_DATA.BAR2_val]	170	mov ax, [ecx+IDE_DATA.BAR2_val]
171	mov [StandardATABases+2], ax	171	mov [StandardATABases+2], ax
172		172
173	mov esi, boot_detecthdcd	173	mov esi, boot_detecthdcd
174	call boot_log	174	call boot_log
175	;--------------------------------------	175	;--------------------------------------
176	include 'dev_hdcd.inc'	176	include 'dev_hdcd.inc'
177	;--------------------------------------	177	;--------------------------------------
178	ret	178	ret
179	;-----------------------------------------------------------------------------	179	;-----------------------------------------------------------------------------
180	Init_IDE_ATA_controller_2:	180	Init_IDE_ATA_controller_2:
181	cmp [ecx+IDE_DATA.ProgrammingInterface], 0	181	cmp [ecx+IDE_DATA.ProgrammingInterface], 0
182	jne @f	182	jne @f
183		183
184	ret	184	ret
185	;--------------------------------------	185	;--------------------------------------
186	@@:	186	@@:
187	mov dx, [ecx+IDE_DATA.RegsBaseAddres]	187	mov dx, [ecx+IDE_DATA.RegsBaseAddres]
188	; test whether it is our interrupt?	188	; test whether it is our interrupt?
189	add dx, 2	189	add dx, 2
190	in al, dx	190	in al, dx
191	test al, 100b	191	test al, 100b
192	jz @f	192	jz @f
193	; clear Bus Master IDE Status register	193	; clear Bus Master IDE Status register
194	; clear Interrupt bit	194	; clear Interrupt bit
195	out dx, al	195	out dx, al
196	;--------------------------------------	196	;--------------------------------------
197	@@:	197	@@:
198	add dx, 8	198	add dx, 8
199	; test whether it is our interrupt?	199	; test whether it is our interrupt?
200	in al, dx	200	in al, dx
201	test al, 100b	201	test al, 100b
202	jz @f	202	jz @f
203	; clear Bus Master IDE Status register	203	; clear Bus Master IDE Status register
204	; clear Interrupt bit	204	; clear Interrupt bit
205	out dx, al	205	out dx, al
206	;--------------------------------------	206	;--------------------------------------
207	@@:	207	@@:
208	; read status register and remove the interrupt request	208	; read status register and remove the interrupt request
209	mov dx, [ecx+IDE_DATA.BAR0_val] ;0x1F0	209	mov dx, [ecx+IDE_DATA.BAR0_val] ;0x1F0
210	add dx, 0x7 ;0x1F7	210	add dx, 0x7 ;0x1F7
211	in al, dx	211	in al, dx
212	mov dx, [ecx+IDE_DATA.BAR2_val] ;0x170	212	mov dx, [ecx+IDE_DATA.BAR2_val] ;0x170
213	add dx, 0x7 ;0x177	213	add dx, 0x7 ;0x177
214	in al, dx	214	in al, dx
215	;-----------------------------------------------------------------------------	215	;-----------------------------------------------------------------------------
216	; push eax edx	216	; push eax edx
217	; mov dx, [ecx+IDE_DATA.RegsBaseAddres]	217	; mov dx, [ecx+IDE_DATA.RegsBaseAddres]
218	; xor eax, eax	218	; xor eax, eax
219	; add dx, 2	219	; add dx, 2
220	; in al, dx	220	; in al, dx
221	; DEBUGF 1, "K : Primary Bus Master IDE Status Register %x\n", eax	221	; DEBUGF 1, "K : Primary Bus Master IDE Status Register %x\n", eax
222		222
223	; add dx, 8	223	; add dx, 8
224	; in al, dx	224	; in al, dx
225	; DEBUGF 1, "K : Secondary Bus Master IDE Status Register %x\n", eax	225	; DEBUGF 1, "K : Secondary Bus Master IDE Status Register %x\n", eax
226	; pop edx eax	226	; pop edx eax
227		227
228	; cmp [ecx+IDE_DATA.RegsBaseAddres], 0	228	; cmp [ecx+IDE_DATA.RegsBaseAddres], 0
229	; setnz [ecx+IDE_DATA.dma_hdd]	229	; setnz [ecx+IDE_DATA.dma_hdd]
230	;-----------------------------------------------------------------------------	230	;-----------------------------------------------------------------------------
231	; set interrupts for IDE Controller	231	; set interrupts for IDE Controller
232	;-----------------------------------------------------------------------------	232	;-----------------------------------------------------------------------------
233	pushfd	233	pushfd
234	cli	234	cli
235	.enable_IDE_interrupt:	235	.enable_IDE_interrupt:
236	mov esi, boot_enabling_ide	236	mov esi, boot_enabling_ide
237	call boot_log	237	call boot_log
238	; Enable interrupts in IDE controller for DMA	238	; Enable interrupts in IDE controller for DMA
239	xor ebx, ebx	239	xor ebx, ebx
240	cmp ecx, IDE_controller_2	240	cmp ecx, IDE_controller_2
241	jne @f	241	jne @f
242		242
243	add ebx, 5	243	add ebx, 5
244	jmp .check_DRIVE_DATA	244	jmp .check_DRIVE_DATA
245	;--------------------------------------	245	;--------------------------------------
246	@@:	246	@@:
247	cmp ecx, IDE_controller_3	247	cmp ecx, IDE_controller_3
248	jne .check_DRIVE_DATA	248	jne .check_DRIVE_DATA
249		249
250	add ebx, 10	250	add ebx, 10
251	;--------------------------------------	251	;--------------------------------------
252	.check_DRIVE_DATA:	252	.check_DRIVE_DATA:
253	mov al, 0	253	mov al, 0
254	mov ah, [ebx+DRIVE_DATA+1]	254	mov ah, [ebx+DRIVE_DATA+1]
255	test ah, 10100000b ; check for ATAPI devices	255	test ah, 10100000b ; check for ATAPI devices
256	jz @f	256	jz @f
257	;--------------------------------------	257	;--------------------------------------
258	.ch1_pio_set_ATAPI:	258	.ch1_pio_set_ATAPI:
259	DEBUGF 1, "K : IDE CH1 PIO, because ATAPI drive present\n"	259	DEBUGF 1, "K : IDE CH1 PIO, because ATAPI drive present\n"
260	jmp .ch1_pio_set_for_all	260	jmp .ch1_pio_set_for_all
261	;--------------------------------------	261	;--------------------------------------
262	.ch1_pio_set_no_devices:	262	.ch1_pio_set_no_devices:
263	DEBUGF 1, "K : IDE CH1 PIO because no devices\n"	263	DEBUGF 1, "K : IDE CH1 PIO because no devices\n"
264	jmp .ch1_pio_set_for_all	264	jmp .ch1_pio_set_for_all
265	;-------------------------------------	265	;-------------------------------------
266	.ch1_pio_set:	266	.ch1_pio_set:
267	DEBUGF 1, "K : IDE CH1 PIO because device not support UDMA\n"	267	DEBUGF 1, "K : IDE CH1 PIO because device not support UDMA\n"
268	;-------------------------------------	268	;-------------------------------------
269	.ch1_pio_set_for_all:	269	.ch1_pio_set_for_all:
270	mov [ecx+IDE_DATA.dma_hdd_channel_1], al	270	mov [ecx+IDE_DATA.dma_hdd_channel_1], al
271	jmp .ch2_check	271	jmp .ch2_check
272	;--------------------------------------	272	;--------------------------------------
273	@@:	273	@@:
274	xor ebx, ebx	274	xor ebx, ebx
275	call calculate_IDE_device_values_storage	275	call calculate_IDE_device_values_storage
276		276
277	test ah, 1010000b	277	test ah, 1010000b
278	jz .ch1_pio_set_no_devices	278	jz .ch1_pio_set_no_devices
279		279
280	test ah, 1000000b	280	test ah, 1000000b
281	jz @f	281	jz @f
282		282
283	cmp [ebx+IDE_DEVICE.UDMA_possible_modes], al	283	cmp [ebx+IDE_DEVICE.UDMA_possible_modes], al
284	je .ch1_pio_set	284	je .ch1_pio_set
285		285
286	cmp [ebx+IDE_DEVICE.UDMA_set_mode], al	286	cmp [ebx+IDE_DEVICE.UDMA_set_mode], al
287	je .ch1_pio_set	287	je .ch1_pio_set
288	;--------------------------------------	288	;--------------------------------------
289	@@:	289	@@:
290	test ah, 10000b	290	test ah, 10000b
291	jz @f	291	jz @f
292		292
293	add ebx, 2	293	add ebx, 2
294		294
295	cmp [ebx+IDE_DEVICE.UDMA_possible_modes], al	295	cmp [ebx+IDE_DEVICE.UDMA_possible_modes], al
296	je .ch1_pio_set	296	je .ch1_pio_set
297		297
298	cmp [ebx+IDE_DEVICE.UDMA_set_mode], al	298	cmp [ebx+IDE_DEVICE.UDMA_set_mode], al
299	je .ch1_pio_set	299	je .ch1_pio_set
300	;--------------------------------------	300	;--------------------------------------
301	@@:	301	@@:
302	mov dx, [ecx+IDE_DATA.BAR1_val] ;0x3F4	302	mov dx, [ecx+IDE_DATA.BAR1_val] ;0x3F4
303	add dx, 2 ;0x3F6	303	add dx, 2 ;0x3F6
304	out dx, al	304	out dx, al
305	DEBUGF 1, "K : IDE CH1 DMA enabled\n"	305	DEBUGF 1, "K : IDE CH1 DMA enabled\n"
306	mov [ecx+IDE_DATA.dma_hdd_channel_1], byte 1	306	mov [ecx+IDE_DATA.dma_hdd_channel_1], byte 1
307	;--------------------------------------	307	;--------------------------------------
308	.ch2_check:	308	.ch2_check:
309	test ah, 1010b ; check for ATAPI devices	309	test ah, 1010b ; check for ATAPI devices
310	jz @f	310	jz @f
311	;--------------------------------------	311	;--------------------------------------
312	.ch2_pio_set_ATAPI:	312	.ch2_pio_set_ATAPI:
313	DEBUGF 1, "K : IDE CH2 PIO, because ATAPI drive present\n"	313	DEBUGF 1, "K : IDE CH2 PIO, because ATAPI drive present\n"
314	jmp .ch2_pio_set_for_all	314	jmp .ch2_pio_set_for_all
315	;--------------------------------------	315	;--------------------------------------
316	.ch2_pio_set_no_devices:	316	.ch2_pio_set_no_devices:
317	DEBUGF 1, "K : IDE CH2 PIO because no devices\n"	317	DEBUGF 1, "K : IDE CH2 PIO because no devices\n"
318	jmp .ch2_pio_set_for_all	318	jmp .ch2_pio_set_for_all
319	;--------------------------------------	319	;--------------------------------------
320	.ch2_pio_set:	320	.ch2_pio_set:
321	DEBUGF 1, "K : IDE CH2 PIO because device not support UDMA\n"	321	DEBUGF 1, "K : IDE CH2 PIO because device not support UDMA\n"
322	;--------------------------------------	322	;--------------------------------------
323	.ch2_pio_set_for_all:	323	.ch2_pio_set_for_all:
324	mov [ecx+IDE_DATA.dma_hdd_channel_2], al	324	mov [ecx+IDE_DATA.dma_hdd_channel_2], al
325	jmp .set_interrupts_for_IDE_controllers	325	jmp .set_interrupts_for_IDE_controllers
326	;--------------------------------------	326	;--------------------------------------
327	@@:	327	@@:
328	mov ebx, 4	328	mov ebx, 4
329	call calculate_IDE_device_values_storage	329	call calculate_IDE_device_values_storage
330		330
331	test ah, 101b	331	test ah, 101b
332	jz .ch2_pio_set_no_devices	332	jz .ch2_pio_set_no_devices
333		333
334	test ah, 100b	334	test ah, 100b
335	jz @f	335	jz @f
336		336
337	cmp [ebx+IDE_DEVICE.UDMA_possible_modes], al	337	cmp [ebx+IDE_DEVICE.UDMA_possible_modes], al
338	je .ch2_pio_set	338	je .ch2_pio_set
339		339
340	cmp [ebx+IDE_DEVICE.UDMA_set_mode], al	340	cmp [ebx+IDE_DEVICE.UDMA_set_mode], al
341	je .ch2_pio_set	341	je .ch2_pio_set
342	;--------------------------------------	342	;--------------------------------------
343	@@:	343	@@:
344	test ah, 1b	344	test ah, 1b
345	jz @f	345	jz @f
346		346
347	add ebx, 2	347	add ebx, 2
348		348
349	cmp [ebx+IDE_DEVICE.UDMA_possible_modes], al	349	cmp [ebx+IDE_DEVICE.UDMA_possible_modes], al
350	je .ch2_pio_set	350	je .ch2_pio_set
351		351
352	cmp [ebx+IDE_DEVICE.UDMA_set_mode], al	352	cmp [ebx+IDE_DEVICE.UDMA_set_mode], al
353	je .ch2_pio_set	353	je .ch2_pio_set
354	;--------------------------------------	354	;--------------------------------------
355	@@:	355	@@:
356	mov dx, [ecx+IDE_DATA.BAR3_val] ;0x374	356	mov dx, [ecx+IDE_DATA.BAR3_val] ;0x374
357	add dx, 2 ;0x376	357	add dx, 2 ;0x376
358	out dx, al	358	out dx, al
359	DEBUGF 1, "K : IDE CH2 DMA enabled\n"	359	DEBUGF 1, "K : IDE CH2 DMA enabled\n"
360	mov [ecx+IDE_DATA.dma_hdd_channel_2], byte 1	360	mov [ecx+IDE_DATA.dma_hdd_channel_2], byte 1
361	;--------------------------------------	361	;--------------------------------------
362	.set_interrupts_for_IDE_controllers:	362	.set_interrupts_for_IDE_controllers:
363	mov esi, boot_set_int_IDE	363	mov esi, boot_set_int_IDE
364	call boot_log	364	call boot_log
365	;--------------------------------------	365	;--------------------------------------
366	mov eax, [ecx+IDE_DATA.ProgrammingInterface]	366	mov eax, [ecx+IDE_DATA.ProgrammingInterface]
367	; cmp ax, 0x0180	367	; cmp ax, 0x0180
368	; je .pata_ide	368	; je .pata_ide
369		369
370	; cmp ax, 0x018a	370	; cmp ax, 0x018a
371	; jne .sata_ide	371	; jne .sata_ide
372		372
373	test al, 1 ; 0 - legacy PCI mode, 1 - native PCI mode	373	test al, 1 ; 0 - legacy PCI mode, 1 - native PCI mode
374	jnz .sata_ide	374	jnz .sata_ide
375	;--------------------------------------	375	;--------------------------------------
376	.pata_ide:	376	.pata_ide:
377	cmp [ecx+IDE_DATA.RegsBaseAddres], 0	377	cmp [ecx+IDE_DATA.RegsBaseAddres], 0
378	je .end_set_interrupts	378	je .end_set_interrupts
379		379
380	push ecx	380	push ecx
381	stdcall attach_int_handler, 14, IDE_irq_14_handler, 0	381	stdcall attach_int_handler, 14, IDE_irq_14_handler, ecx
-		382	pop ecx
382	DEBUGF 1, "K : Set IDE IRQ14 return code %x\n", eax	383	DEBUGF 1, "K : Set IDE IRQ14 return code %x\n", eax
-		384	push ecx
383	stdcall attach_int_handler, 15, IDE_irq_15_handler, 0	385	stdcall attach_int_handler, 15, IDE_irq_15_handler, ecx
384	DEBUGF 1, "K : Set IDE IRQ15 return code %x\n", eax	386	DEBUGF 1, "K : Set IDE IRQ15 return code %x\n", eax
385	pop ecx	387	pop ecx
386		388
387	jmp .end_set_interrupts	389	jmp .end_set_interrupts
388	;--------------------------------------	390	;--------------------------------------
389	.sata_ide:	391	.sata_ide:
390	; cmp ax, 0x0185	392	; cmp ax, 0x0185
391	; je .sata_ide_1	393	; je .sata_ide_1
392		394
393	; cmp ax, 0x018f	395	; cmp ax, 0x018f
394	; jne .end_set_interrupts	396	; jne .end_set_interrupts
395	;--------------------------------------	397	;--------------------------------------
396	;.sata_ide_1:	398	;.sata_ide_1:
397	; Some weird controllers generate an interrupt even if IDE interrupts	399	; Some weird controllers generate an interrupt even if IDE interrupts
398	; are disabled and no IDE devices. For example, notebook ASUS K72F -	400	; are disabled and no IDE devices. For example, notebook ASUS K72F -
399	; IDE controller 010185 generates false interrupt when we work with	401	; IDE controller 010185 generates false interrupt when we work with
400	; the IDE controller 01018f. For this reason, the interrupt handler	402	; the IDE controller 01018f. For this reason, the interrupt handler
401	; does not need to be installed if both channel IDE controller	403	; does not need to be installed if both channel IDE controller
402	; running in PIO mode.	404	; running in PIO mode.
-		405
-		406	; ...unfortunately, PCI interrupt can be shared with other devices
-		407	; which could enable it without consulting IDE code.
-		408	; So install the handler anyways and try to process
-		409	; even those interrupts which we are not expecting.
403	cmp [ecx+IDE_DATA.RegsBaseAddres], 0	410	cmp [ecx+IDE_DATA.RegsBaseAddres], 0
404	je .end_set_interrupts	411	je .end_set_interrupts
405		-
406	cmp [ecx+IDE_DATA.dma_hdd_channel_1], 0	-
407	jne @f	-
408		-
409	cmp [ecx+IDE_DATA.dma_hdd_channel_2], 0	-
410	je .end_set_interrupts	-
411	;--------------------------------------	-
412	@@:	412
413	mov ax, [ecx+IDE_DATA.Interrupt]	413	mov ax, [ecx+IDE_DATA.Interrupt]
414	movzx eax, al	414	movzx eax, al
415	push ecx	415	push ecx
416	stdcall attach_int_handler, eax, IDE_common_irq_handler, 0	416	stdcall attach_int_handler, eax, IDE_common_irq_handler, ecx
417	pop ecx	417	pop ecx
418	DEBUGF 1, "K : Set IDE IRQ%d return code %x\n", [ecx+IDE_DATA.Interrupt]:1, eax	418	DEBUGF 1, "K : Set IDE IRQ%d return code %x\n", [ecx+IDE_DATA.Interrupt]:1, eax
419	;--------------------------------------	419	;--------------------------------------
420	.end_set_interrupts:	420	.end_set_interrupts:
421	popfd	421	popfd
422	ret	422	ret
423	;-----------------------------------------------------------------------------	423	;-----------------------------------------------------------------------------
424	; END of initialisation IDE ATA code	424	; END of initialisation IDE ATA code
425	;-----------------------------------------------------------------------------	425	;-----------------------------------------------------------------------------
426	find_IDE_controller_done:	426	find_IDE_controller_done:
427	mov ecx, IDE_controller_1	427	mov ecx, IDE_controller_1
428	mov [IDE_controller_pointer], ecx	428	mov [IDE_controller_pointer], ecx
429	call Init_IDE_ATA_controller	429	call Init_IDE_ATA_controller
430	mov ecx, IDE_controller_2	430	mov ecx, IDE_controller_2
431	mov [IDE_controller_pointer], ecx	431	mov [IDE_controller_pointer], ecx
432	call Init_IDE_ATA_controller	432	call Init_IDE_ATA_controller
433	mov ecx, IDE_controller_3	433	mov ecx, IDE_controller_3
434	mov [IDE_controller_pointer], ecx	434	mov [IDE_controller_pointer], ecx
435	call Init_IDE_ATA_controller	435	call Init_IDE_ATA_controller
436	;-----------------------------------------------------------------------------	436	;-----------------------------------------------------------------------------
437	mov esi, boot_getcache	437	mov esi, boot_getcache
438	call boot_log	438	call boot_log
439	include 'getcache.inc'	439	include 'getcache.inc'
440	;-----------------------------------------------------------------------------	440	;-----------------------------------------------------------------------------
441	mov esi, boot_detectpart	441	mov esi, boot_detectpart
442	call boot_log	442	call boot_log
443	include 'sear_par.inc'	443	include 'sear_par.inc'
444	;-----------------------------------------------------------------------------	444	;-----------------------------------------------------------------------------
445	mov esi, boot_init_sys	445	mov esi, boot_init_sys
446	call boot_log	446	call boot_log
447	call Parser_params	447	call Parser_params
448		448
449	if ~ defined extended_primary_loader	449	if ~ defined extended_primary_loader
450	; ramdisk image should be loaded by extended primary loader if it exists	450	; ramdisk image should be loaded by extended primary loader if it exists
451	; READ RAMDISK IMAGE FROM HD	451	; READ RAMDISK IMAGE FROM HD
452	include '../boot/rdload.inc'	452	include '../boot/rdload.inc'
453	end if	453	end if
454	;-----------------------------------------------------------------------------	454	;-----------------------------------------------------------------------------
455	mov ecx, IDE_controller_1	455	mov ecx, IDE_controller_1
456	mov [IDE_controller_pointer], ecx	456	mov [IDE_controller_pointer], ecx
457	call Init_IDE_ATA_controller_2	457	call Init_IDE_ATA_controller_2
458	mov ecx, IDE_controller_2	458	mov ecx, IDE_controller_2
459	mov [IDE_controller_pointer], ecx	459	mov [IDE_controller_pointer], ecx
460	call Init_IDE_ATA_controller_2	460	call Init_IDE_ATA_controller_2
461	mov ecx, IDE_controller_3	461	mov ecx, IDE_controller_3
462	mov [IDE_controller_pointer], ecx	462	mov [IDE_controller_pointer], ecx
463	call Init_IDE_ATA_controller_2	463	call Init_IDE_ATA_controller_2
464	;-----------------------------------------------------------------------------	464	;-----------------------------------------------------------------------------

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(root)/kernel/trunk/detect/init_ata.inc – Rev 5363 → 6015