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1 | ; Simple test for ring-3 debugging of mtrr.inc. |
1 | ; Simple test for ring-3 debugging of mtrr.inc. |
2 | ; Contains some inputs taken from real-life MTRRs and expected outputs. |
2 | ; Contains some inputs taken from real-life MTRRs and expected outputs. |
3 | format PE console |
3 | format PE console |
4 | ;include 'win32a.inc' |
4 | ;include 'win32a.inc' |
5 | macro $Revision [args] |
5 | macro $Revision [args] |
6 | { |
6 | { |
7 | } |
7 | } |
8 | macro ignore_empty_revision_keyword { |
8 | macro ignore_empty_revision_keyword { |
9 | macro $Revi#sion$ \{\} |
9 | macro $Revi#sion$ \{\} |
10 | } |
10 | } |
11 | ignore_empty_revision_keyword |
11 | ignore_empty_revision_keyword |
12 | include '../proc32.inc' |
12 | include '../proc32.inc' |
13 | include '../struct.inc' |
13 | include '../struct.inc' |
14 | entry start |
14 | entry start |
15 | 15 | ||
16 | ; one test has 8, another test has 10 |
16 | ; one test has 8, another test has 10 |
17 | ; this is the maximal value for storing/copying, real value is in MTRRCAP |
17 | ; this is the maximal value for storing/copying, real value is in MTRRCAP |
18 | MAX_VARIABLE_MTRR = 10 |
18 | MAX_VARIABLE_MTRR = 10 |
19 | 19 | ||
20 | start: |
20 | start: |
21 | ; Copy test inputs, run init_mtrr, compare with test outputs. Repeat. |
21 | ; Copy test inputs, run init_mtrr, compare with test outputs. Repeat. |
22 | mov esi, test1_in_data |
22 | mov esi, test1_in_data |
23 | mov edi, mtrrdata |
23 | mov edi, mtrrdata |
24 | mov ecx, mtrrdata_size / 4 |
24 | mov ecx, mtrrdata_size / 4 |
25 | rep movsd |
25 | rep movsd |
26 | call init_mtrr |
26 | call init_mtrr |
27 | mov esi, test1_out_data |
27 | mov esi, test1_out_data |
28 | mov edi, mtrrdata |
28 | mov edi, mtrrdata |
29 | mov ecx, mtrrdata_size / 4 |
29 | mov ecx, mtrrdata_size / 4 |
30 | repz cmpsd |
30 | repz cmpsd |
31 | jnz .fail |
31 | jnz .fail |
32 | mov esi, test2_in_data |
32 | mov esi, test2_in_data |
33 | mov edi, mtrrdata |
33 | mov edi, mtrrdata |
34 | mov ecx, mtrrdata_size / 4 |
34 | mov ecx, mtrrdata_size / 4 |
35 | rep movsd |
35 | rep movsd |
36 | call init_mtrr |
36 | call init_mtrr |
37 | mov esi, test2_out_data |
37 | mov esi, test2_out_data |
38 | mov edi, mtrrdata |
38 | mov edi, mtrrdata |
39 | mov ecx, mtrrdata_size / 4 |
39 | mov ecx, mtrrdata_size / 4 |
40 | repz cmpsd |
40 | repz cmpsd |
41 | jnz .fail |
41 | jnz .fail |
42 | ret |
42 | ret |
43 | 43 | ||
44 | .fail: |
44 | .fail: |
45 | int3 |
45 | int3 |
46 | jmp $ |
46 | jmp $ |
47 | 47 | ||
48 | ; Helper procedure for _rdmsr/_wrmsr, replacements of rdmsr/wrmsr. |
48 | ; Helper procedure for _rdmsr/_wrmsr, replacements of rdmsr/wrmsr. |
49 | ; Returns pointer to memory containing the given MSR. |
49 | ; Returns pointer to memory containing the given MSR. |
50 | ; in: ecx = MSR |
50 | ; in: ecx = MSR |
51 | ; out: esi -> MSR data |
51 | ; out: esi -> MSR data |
52 | proc get_msr_ptr |
52 | proc get_msr_ptr |
53 | mov esi, mtrrcap |
53 | mov esi, mtrrcap |
54 | cmp ecx, 0xFE |
54 | cmp ecx, 0xFE |
55 | jz .ok |
55 | jz .ok |
56 | mov esi, mtrr_def_type |
56 | mov esi, mtrr_def_type |
57 | cmp ecx, 0x2FF |
57 | cmp ecx, 0x2FF |
58 | jz .ok |
58 | jz .ok |
59 | lea esi, [ecx-0x200] |
59 | lea esi, [ecx-0x200] |
60 | cmp esi, MAX_VARIABLE_MTRR*2 |
60 | cmp esi, MAX_VARIABLE_MTRR*2 |
61 | jae .fail |
61 | jae .fail |
62 | lea esi, [mtrr+esi*8] |
62 | lea esi, [mtrr+esi*8] |
63 | .ok: |
63 | .ok: |
64 | ret |
64 | ret |
65 | .fail: |
65 | .fail: |
66 | int3 |
66 | int3 |
67 | ret |
67 | ret |
68 | endp |
68 | endp |
69 | 69 | ||
70 | ; Emulates rdmsr. |
70 | ; Emulates rdmsr. |
71 | proc _rdmsr |
71 | proc _rdmsr |
72 | push esi |
72 | push esi |
73 | call get_msr_ptr |
73 | call get_msr_ptr |
74 | mov eax, [esi] |
74 | mov eax, [esi] |
75 | mov edx, [esi+4] |
75 | mov edx, [esi+4] |
76 | pop esi |
76 | pop esi |
77 | ret |
77 | ret |
78 | endp |
78 | endp |
79 | 79 | ||
80 | ; Emulates wrmsr. |
80 | ; Emulates wrmsr. |
81 | proc _wrmsr |
81 | proc _wrmsr |
82 | push esi |
82 | push esi |
83 | call get_msr_ptr |
83 | call get_msr_ptr |
84 | mov [esi], eax |
84 | mov [esi], eax |
85 | mov [esi+4], edx |
85 | mov [esi+4], edx |
86 | pop esi |
86 | pop esi |
87 | ret |
87 | ret |
88 | endp |
88 | endp |
89 | 89 | ||
90 | ; Macro to substitute rdmsr/wrmsr with emulating code. |
90 | ; Macro to substitute rdmsr/wrmsr with emulating code. |
91 | macro rdmsr |
91 | macro rdmsr |
92 | { |
92 | { |
93 | call _rdmsr |
93 | call _rdmsr |
94 | } |
94 | } |
95 | macro wrmsr |
95 | macro wrmsr |
96 | { |
96 | { |
97 | call _wrmsr |
97 | call _wrmsr |
98 | } |
98 | } |
99 | ; Our emulation of rdmsr/wrmsr has nothing to do with real cache |
99 | ; Our emulation of rdmsr/wrmsr has nothing to do with real cache |
100 | ; and system-wide settings, |
100 | ; and system-wide settings, |
101 | ; remove all attempts to wbinvd and disable/enable cache in cr0. |
101 | ; remove all attempts to wbinvd and disable/enable cache in cr0. |
102 | macro wbinvd |
102 | macro wbinvd |
103 | { |
103 | { |
104 | } |
104 | } |
105 | macro mov a,b |
105 | macro mov a,b |
106 | { |
106 | { |
107 | if ~(a eq cr0) & ~(b eq cr0) |
107 | if ~(a eq cr0) & ~(b eq cr0) |
108 | mov a, b |
108 | mov a, b |
109 | end if |
109 | end if |
110 | } |
110 | } |
111 | macro movi r,i |
111 | macro movi r,i |
112 | { |
112 | { |
113 | push i |
113 | push i |
114 | pop r |
114 | pop r |
115 | } |
115 | } |
116 | 116 | ||
117 | include '../kglobals.inc' |
117 | include '../kglobals.inc' |
118 | CAPS_MTRR equ 12 |
118 | CAPS_MTRR = 12 |
119 | MSR_MTRR_DEF_TYPE equ 0x2FF |
119 | MSR_MTRR_DEF_TYPE = 0x2FF |
120 | CAPS_PGE equ 13 |
120 | CAPS_PGE = 13 |
121 | CAPS_PAT equ 16 |
121 | CAPS_PAT = 16 |
122 | MSR_CR_PAT equ 0x277 |
122 | MSR_CR_PAT = 0x277 |
123 | PAT_VALUE equ 0x00070106 ; (UC<<24)|(UCM<<16)|(WC<<8)|WB |
123 | PAT_VALUE = 0x00070106 ; (UC<<24)|(UCM<<16)|(WC<<8)|WB |
124 | MEM_WB equ 6 ;write-back memory |
124 | MEM_WB = 6 ;write-back memory |
125 | MEM_WC equ 1 ;write combined memory |
125 | MEM_WC = 1 ;write combined memory |
126 | MEM_UC equ 0 ;uncached memory |
126 | MEM_UC = 0 ;uncached memory |
127 | include 'mtrr.inc' |
127 | include 'mtrr.inc' |
128 | 128 | ||
129 | BOOT_VARS = 0 |
129 | BOOT_VARS = 0 |
130 | BOOT.mtrr db 1 |
130 | BOOT.mtrr db 1 |
131 | align 4 |
131 | align 4 |
132 | cpu_caps dd 1 shl CAPS_MTRR |
132 | cpu_caps dd 1 shl CAPS_MTRR |
133 | LFBAddress dd 0xE0000000 |
133 | LFBAddress dd 0xE0000000 |
134 | LFBSize dd 0x10000000 |
134 | LFBSize dd 0x10000000 |
135 | MEM_AMOUNT dd 0 ; not used, needed for compilation |
135 | MEM_AMOUNT dd 0 ; not used, needed for compilation |
136 | 136 | ||
137 | align 4 |
137 | align 4 |
138 | ; Test 1: input |
138 | ; Test 1: input |
139 | test1_in_data: |
139 | test1_in_data: |
140 | test1_phys_addr_width db 36 |
140 | test1_phys_addr_width db 36 |
141 | rb 3 |
141 | rb 3 |
142 | test1_in_mtrrcap dq 0xD08 |
142 | test1_in_mtrrcap dq 0xD08 |
143 | test1_in_mtrr_def_type dq 0xC00 |
143 | test1_in_mtrr_def_type dq 0xC00 |
144 | test1_in_mtrrs: |
144 | test1_in_mtrrs: |
145 | dq 0x000000006, 0xF00000800 |
145 | dq 0x000000006, 0xF00000800 |
146 | dq 0x100000006, 0xFC0000800 |
146 | dq 0x100000006, 0xFC0000800 |
147 | dq 0x0BC000000, 0xFFC000800 |
147 | dq 0x0BC000000, 0xFFC000800 |
148 | dq 0x0C0000000, 0xFC0000800 |
148 | dq 0x0C0000000, 0xFC0000800 |
149 | dq 0x138000000, 0xFF8000800 |
149 | dq 0x138000000, 0xFF8000800 |
150 | dq 0, 0 |
150 | dq 0, 0 |
151 | dq 0, 0 |
151 | dq 0, 0 |
152 | dq 0, 0 |
152 | dq 0, 0 |
153 | dq -1, -1 ; not used |
153 | dq -1, -1 ; not used |
154 | dq -1, -1 ; not used |
154 | dq -1, -1 ; not used |
155 | ; Test 1: output |
155 | ; Test 1: output |
156 | test1_out_data: |
156 | test1_out_data: |
157 | dd 36 ; phys_addr_width, readonly |
157 | dd 36 ; phys_addr_width, readonly |
158 | dq 0xD08 ; MTRRCAP, readonly |
158 | dq 0xD08 ; MTRRCAP, readonly |
159 | dq 0xC00 ; MTRR_DEF_TYPE, should be the same |
159 | dq 0xC00 ; MTRR_DEF_TYPE, should be the same |
160 | dq 0x000000006, 0xF80000800 |
160 | dq 0x000000006, 0xF80000800 |
161 | dq 0x080000006, 0xFC0000800 |
161 | dq 0x080000006, 0xFC0000800 |
162 | dq 0x0BC000000, 0xFFC000800 |
162 | dq 0x0BC000000, 0xFFC000800 |
163 | dq 0x100000006, 0xFC0000800 |
163 | dq 0x100000006, 0xFC0000800 |
164 | dq 0x138000000, 0xFF8000800 |
164 | dq 0x138000000, 0xFF8000800 |
165 | dq 0x0E0000001, 0xFFF000800 ; added for [LFBAddress] |
165 | dq 0x0E0000001, 0xFFF000800 ; added for [LFBAddress] |
166 | dq 0, 0 |
166 | dq 0, 0 |
167 | dq 0, 0 |
167 | dq 0, 0 |
168 | dq -1, -1 ; not used |
168 | dq -1, -1 ; not used |
169 | dq -1, -1 ; not used |
169 | dq -1, -1 ; not used |
170 | 170 | ||
171 | ; Test 2: input |
171 | ; Test 2: input |
172 | test2_in_data: |
172 | test2_in_data: |
173 | test2_phys_addr_width db 39 |
173 | test2_phys_addr_width db 39 |
174 | rb 3 |
174 | rb 3 |
175 | test2_in_mtrrcap dq 0xD0A |
175 | test2_in_mtrrcap dq 0xD0A |
176 | test2_in_mtrr_def_type dq 0xC00 |
176 | test2_in_mtrr_def_type dq 0xC00 |
177 | test2_in_mtrrs: |
177 | test2_in_mtrrs: |
178 | dq 0x0000000006, 0x7F00000800 |
178 | dq 0x0000000006, 0x7F00000800 |
179 | dq 0x0100000006, 0x7FE0000800 |
179 | dq 0x0100000006, 0x7FE0000800 |
180 | dq 0x00E0000000, 0x7FE0000800 |
180 | dq 0x00E0000000, 0x7FE0000800 |
181 | dq 0x00DC000000, 0x7FFC000800 |
181 | dq 0x00DC000000, 0x7FFC000800 |
182 | dq 0x00DBC00000, 0x7FFFC00800 |
182 | dq 0x00DBC00000, 0x7FFFC00800 |
183 | dq 0x011F800000, 0x7FFF800800 |
183 | dq 0x011F800000, 0x7FFF800800 |
184 | dq 0x011F400000, 0x7FFFC00800 |
184 | dq 0x011F400000, 0x7FFFC00800 |
185 | dq 0x011F200000, 0x7FFFE00800 |
185 | dq 0x011F200000, 0x7FFFE00800 |
186 | dq 0, 0 |
186 | dq 0, 0 |
187 | dq 0, 0 |
187 | dq 0, 0 |
188 | 188 | ||
189 | ; Test 2: output |
189 | ; Test 2: output |
190 | test2_out_data: |
190 | test2_out_data: |
191 | dd 39 ; phys_addr_width, readonly |
191 | dd 39 ; phys_addr_width, readonly |
192 | dq 0xD0A ; MTRRCAP, readonly |
192 | dq 0xD0A ; MTRRCAP, readonly |
193 | dq 0xC00 ; MTRR_DEF_TYPE, should be the same |
193 | dq 0xC00 ; MTRR_DEF_TYPE, should be the same |
194 | dq 0x0000000006, 0x7F80000800 |
194 | dq 0x0000000006, 0x7F80000800 |
195 | dq 0x0080000006, 0x7FC0000800 |
195 | dq 0x0080000006, 0x7FC0000800 |
196 | dq 0x00C0000006, 0x7FE0000800 |
196 | dq 0x00C0000006, 0x7FE0000800 |
197 | dq 0x00DC000000, 0x7FFC000800 |
197 | dq 0x00DC000000, 0x7FFC000800 |
198 | dq 0x00DBC00000, 0x7FFFC00800 |
198 | dq 0x00DBC00000, 0x7FFFC00800 |
199 | dq 0x0100000006, 0x7FE0000800 |
199 | dq 0x0100000006, 0x7FE0000800 |
200 | dq 0x011F800000, 0x7FFF800800 |
200 | dq 0x011F800000, 0x7FFF800800 |
201 | dq 0x011F400000, 0x7FFFC00800 |
201 | dq 0x011F400000, 0x7FFFC00800 |
202 | dq 0x011F200000, 0x7FFFE00800 |
202 | dq 0x011F200000, 0x7FFFE00800 |
203 | dq 0x00E0000001, 0x7FFF000800 ; added for [LFBAddress] |
203 | dq 0x00E0000001, 0x7FFF000800 ; added for [LFBAddress] |
204 | IncludeIGlobals |
204 | IncludeIGlobals |
205 | align 4 |
205 | align 4 |
206 | mtrrdata: |
206 | mtrrdata: |
207 | cpu_phys_addr_width db ? |
207 | cpu_phys_addr_width db ? |
208 | rb 3 |
208 | rb 3 |
209 | mtrrcap dq ? |
209 | mtrrcap dq ? |
210 | mtrr_def_type dq ? |
210 | mtrr_def_type dq ? |
211 | mtrr rq MAX_VARIABLE_MTRR*2 |
211 | mtrr rq MAX_VARIABLE_MTRR*2 |
212 | mtrrdata_size = $ - mtrrdata |
212 | mtrrdata_size = $ - mtrrdata |
213 | IncludeUGlobals8)|WB |
213 | IncludeUGlobals8)|WB |
214 | MEM_WB><8)|WB |
214 | MEM_WB><8)|WB |
215 | MEM_WB>16)|(WC<<8)|WB |
215 | MEM_WB>16)|(WC<<8)|WB |
216 | MEM_WB><16)|(WC<<8)|WB |
216 | MEM_WB><16)|(WC<<8)|WB |
217 | MEM_WB>24)|(UCM<<16)|(WC<<8)|WB |
217 | MEM_WB>24)|(UCM<<16)|(WC<<8)|WB |
218 | MEM_WB><24)|(UCM<<16)|(WC<<8)|WB |
218 | MEM_WB><24)|(UCM<<16)|(WC<<8)|WB |
219 | MEM_WB> |
219 | MEM_WB> |