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| Rev 7132 | Rev 7136 | ||
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| 3 | ;; Copyright (C) KolibriOS team 2004-2017. All rights reserved. ;; |
3 | ;; Copyright (C) KolibriOS team 2004-2017. All rights reserved. ;; |
| 4 | ;; Distributed under terms of the GNU General Public License ;; |
4 | ;; Distributed under terms of the GNU General Public License ;; |
| 5 | ;; ;; |
5 | ;; ;; |
| 6 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
6 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| Line 7... | Line 7... | ||
| 7 | 7 | ||
| Line 8... | Line 8... | ||
| 8 | $Revision: 7132 $ |
8 | $Revision: 7136 $ |
| 9 | 9 | ||
| 10 | 10 | ||
| 11 | dpl0 equ 10010000b ; data read dpl0 |
11 | dpl0 = 10010000b ; data read dpl0 |
| 12 | drw0 equ 10010010b ; data read/write dpl0 |
12 | drw0 = 10010010b ; data read/write dpl0 |
| Line 13... | Line 13... | ||
| 13 | drw3 equ 11110010b ; data read/write dpl3 |
13 | drw3 = 11110010b ; data read/write dpl3 |
| 14 | cpl0 equ 10011010b ; code read dpl0 |
14 | cpl0 = 10011010b ; code read dpl0 |
| Line 15... | Line 15... | ||
| 15 | cpl3 equ 11111010b ; code read dpl3 |
15 | cpl3 = 11111010b ; code read dpl3 |
| Line 16... | Line 16... | ||
| 16 | 16 | ||
| 17 | D32 equ 01000000b ; 32bit segment |
17 | D32 = 01000000b ; 32bit segment |
| 18 | G32 equ 10000000b ; page gran |
18 | G32 = 10000000b ; page gran |
| 19 | 19 | ||
| 20 | 20 | ||
| 21 | ;;;;;;;;;;;;cpu_caps flags;;;;;;;;;;;;;;;; |
21 | ;;;;;;;;;;;;cpu_caps flags;;;;;;;;;;;;;;;; |
| 22 | 22 | ||
| 23 | CPU_386 equ 3 |
23 | CPU_386 = 3 |
| 24 | CPU_486 equ 4 |
24 | CPU_486 = 4 |
| 25 | CPU_PENTIUM equ 5 |
25 | CPU_PENTIUM = 5 |
| 26 | CPU_P6 equ 6 |
26 | CPU_P6 = 6 |
| 27 | CPU_PENTIUM4 equ 0x0F |
27 | CPU_PENTIUM4 = 0x0F |
| 28 | 28 | ||
| 29 | CAPS_FPU equ 00 ;on-chip x87 floating point unit |
29 | CAPS_FPU = 00 ;on-chip x87 floating point unit |
| 30 | CAPS_VME equ 01 ;virtual-mode enhancements |
30 | CAPS_VME = 01 ;virtual-mode enhancements |
| 31 | CAPS_DE equ 02 ;debugging extensions |
31 | CAPS_DE = 02 ;debugging extensions |
| 32 | CAPS_PSE equ 03 ;page-size extensions |
32 | CAPS_PSE = 03 ;page-size extensions |
| 33 | CAPS_TSC equ 04 ;time stamp counter |
33 | CAPS_TSC = 04 ;time stamp counter |
| 34 | CAPS_MSR equ 05 ;model-specific registers |
34 | CAPS_MSR = 05 ;model-specific registers |
| 35 | CAPS_PAE equ 06 ;physical-address extensions |
35 | CAPS_PAE = 06 ;physical-address extensions |
| 36 | CAPS_MCE equ 07 ;machine check exception |
36 | CAPS_MCE = 07 ;machine check exception |
| 37 | CAPS_CX8 equ 08 ;CMPXCHG8B instruction |
37 | CAPS_CX8 = 08 ;CMPXCHG8B instruction |
| 38 | CAPS_APIC equ 09 ;on-chip advanced programmable |
38 | CAPS_APIC = 09 ;on-chip advanced programmable |
| 39 | ; interrupt controller |
39 | ;interrupt controller |
| 40 | ; 10 ;unused |
40 | ; 10 ;unused |
| 41 | CAPS_SEP equ 11 ;SYSENTER and SYSEXIT instructions |
41 | CAPS_SEP = 11 ;SYSENTER and SYSEXIT instructions |
| 42 | CAPS_MTRR equ 12 ;memory-type range registers |
42 | CAPS_MTRR = 12 ;memory-type range registers |
| 43 | CAPS_PGE equ 13 ;page global extension |
43 | CAPS_PGE = 13 ;page global extension |
| Line 44... | Line 44... | ||
| 44 | CAPS_MCA equ 14 ;machine check architecture |
44 | CAPS_MCA = 14 ;machine check architecture |
| 45 | CAPS_CMOV equ 15 ;conditional move instructions |
45 | CAPS_CMOV = 15 ;conditional move instructions |
| 46 | CAPS_PAT equ 16 ;page attribute table |
46 | CAPS_PAT = 16 ;page attribute table |
| 47 | 47 | ||
| 48 | CAPS_PSE36 equ 17 ;page-size extensions |
48 | CAPS_PSE36 = 17 ;page-size extensions |
| 49 | CAPS_PSN equ 18 ;processor serial number |
49 | CAPS_PSN = 18 ;processor serial number |
| 50 | CAPS_CLFLUSH equ 19 ;CLFUSH instruction |
50 | CAPS_CLFLUSH = 19 ;CLFUSH instruction |
| 51 | 51 | ||
| 52 | CAPS_DS equ 21 ;debug store |
52 | CAPS_DS = 21 ;debug store |
| 53 | CAPS_ACPI equ 22 ;thermal monitor and software |
53 | CAPS_ACPI = 22 ;thermal monitor and software |
| 54 | ;controlled clock supported |
54 | ;controlled clock supported |
| 55 | CAPS_MMX equ 23 ;MMX instructions |
55 | CAPS_MMX = 23 ;MMX instructions |
| Line 56... | Line 56... | ||
| 56 | CAPS_FXSR equ 24 ;FXSAVE and FXRSTOR instructions |
56 | CAPS_FXSR = 24 ;FXSAVE and FXRSTOR instructions |
| 57 | CAPS_SSE equ 25 ;SSE instructions |
57 | CAPS_SSE = 25 ;SSE instructions |
| 58 | CAPS_SSE2 equ 26 ;SSE2 instructions |
58 | CAPS_SSE2 = 26 ;SSE2 instructions |
| 59 | CAPS_SS equ 27 ;self-snoop |
59 | CAPS_SS = 27 ;self-snoop |
| 60 | CAPS_HTT equ 28 ;hyper-threading technology |
60 | CAPS_HTT = 28 ;hyper-threading technology |
| 61 | CAPS_TM equ 29 ;thermal monitor supported |
61 | CAPS_TM = 29 ;thermal monitor supported |
| 62 | CAPS_IA64 equ 30 ;IA64 capabilities |
62 | CAPS_IA64 = 30 ;IA64 capabilities |
| 63 | CAPS_PBE equ 31 ;pending break enable |
63 | CAPS_PBE = 31 ;pending break enable |
| 64 | 64 | ||
| 65 | ;ecx |
65 | ;ecx |
| 66 | CAPS_SSE3 equ 32 ;SSE3 instructions |
66 | CAPS_SSE3 = 32 ;SSE3 instructions |
| 67 | ; 33 |
67 | ; 33 |
| 68 | ; 34 |
68 | ; 34 |
| 69 | CAPS_MONITOR equ 35 ;MONITOR/MWAIT instructions |
69 | CAPS_MONITOR = 35 ;MONITOR/MWAIT instructions |
| 70 | CAPS_DS_CPL equ 36 ; |
70 | CAPS_DS_CPL = 36 ; |
| 71 | CAPS_VMX equ 37 ;virtual mode extensions |
71 | CAPS_VMX = 37 ;virtual mode extensions |
| 72 | ; 38 ; |
72 | ; 38 ; |
| 73 | CAPS_EST equ 39 ;enhansed speed step |
73 | CAPS_EST = 39 ;enhansed speed step |
| 74 | CAPS_TM2 equ 40 ;thermal monitor2 supported |
74 | CAPS_TM2 = 40 ;thermal monitor2 supported |
| 75 | ; 41 |
75 | ; 41 |
| 76 | CAPS_CID equ 42 ; |
76 | CAPS_CID = 42 ; |
| 77 | ; 43 |
77 | ; 43 |
| 78 | ; 44 |
78 | ; 44 |
| 79 | CAPS_CX16 equ 45 ;CMPXCHG16B instruction |
79 | CAPS_CX16 = 45 ;CMPXCHG16B instruction |
| 80 | CAPS_xTPR equ 46 ; |
80 | CAPS_xTPR = 46 ; |
| 81 | CAPS_XSAVE equ (32 + 26) ; XSAVE and XRSTOR instructions |
81 | CAPS_XSAVE = 32 + 26 ; XSAVE and XRSTOR instructions |
| 82 | CAPS_OSXSAVE equ (32 + 27) |
82 | CAPS_OSXSAVE = 32 + 27 |
| 83 | ; A value of 1 indicates that the OS has set CR4.OSXSAVE[bit 18] to enable |
83 | ; A value of 1 indicates that the OS has set CR4.OSXSAVE[bit 18] to enable |
| 84 | ; XSETBV/XGETBV instructions to access XCR0 and to support processor extended |
84 | ; XSETBV/XGETBV instructions to access XCR0 and to support processor extended |
| 85 | ; state management using XSAVE/XRSTOR. |
85 | ; state management using XSAVE/XRSTOR. |
| 86 | CAPS_AVX equ (32 + 28) ; not AVX2 |
86 | CAPS_AVX = 32 + 28 ; not AVX2 |
| 87 | ; |
87 | ; |
| 88 | ;reserved |
88 | ;reserved |
| 89 | ; |
89 | ; |
| 90 | ;ext edx /ecx |
90 | ;ext edx /ecx |
| 91 | CAPS_SYSCAL equ 64 ; |
91 | CAPS_SYSCAL = 64 ; |
| 92 | CAPS_XD equ 65 ;execution disable |
92 | CAPS_XD = 65 ;execution disable |
| Line 93... | Line 93... | ||
| 93 | CAPS_FFXSR equ 66 ; |
93 | CAPS_FFXSR = 66 ; |
| 94 | CAPS_RDTSCP equ 67 ; |
94 | CAPS_RDTSCP = 67 ; |
| 95 | CAPS_X64 equ 68 ; |
95 | CAPS_X64 = 68 ; |
| 96 | CAPS_3DNOW equ 69 ; |
96 | CAPS_3DNOW = 69 ; |
| 97 | CAPS_3DNOWEXT equ 70 ; |
97 | CAPS_3DNOWEXT = 70 ; |
| 98 | CAPS_LAHF equ 71 ; |
98 | CAPS_LAHF = 71 ; |
| 99 | CAPS_CMP_LEG equ 72 ; |
99 | CAPS_CMP_LEG = 72 ; |
| 100 | CAPS_SVM equ 73 ;secure virual machine |
100 | CAPS_SVM = 73 ;secure virual machine |
| 101 | CAPS_ALTMOVCR8 equ 74 ; |
101 | CAPS_ALTMOVCR8 = 74 ; |
| 102 | 102 | ||
| 103 | ; CPU MSR names |
103 | ; CPU MSR names |
| 104 | MSR_SYSENTER_CS equ 0x174 |
104 | MSR_SYSENTER_CS = 0x174 |
| 105 | MSR_SYSENTER_ESP equ 0x175 |
105 | MSR_SYSENTER_ESP = 0x175 |
| 106 | MSR_SYSENTER_EIP equ 0x176 |
106 | MSR_SYSENTER_EIP = 0x176 |
| 107 | MSR_CR_PAT equ 0x277 |
107 | MSR_CR_PAT = 0x277 |
| 108 | MSR_MTRR_DEF_TYPE equ 0x2FF |
108 | MSR_MTRR_DEF_TYPE = 0x2FF |
| 109 | 109 | ||
| 110 | MSR_AMD_EFER equ 0xC0000080 ; Extended Feature Enable Register |
110 | MSR_AMD_EFER = 0xC0000080 ; Extended Feature Enable Register |
| 111 | MSR_AMD_STAR equ 0xC0000081 ; SYSCALL/SYSRET Target Address Register |
111 | MSR_AMD_STAR = 0xC0000081 ; SYSCALL/SYSRET Target Address Register |
| 112 | 112 | ||
| 113 | CR0_PE equ 0x00000001 ;protected mode |
113 | CR0_PE = 0x00000001 ;protected mode |
| 114 | CR0_MP equ 0x00000002 ;monitor fpu |
114 | CR0_MP = 0x00000002 ;monitor fpu |
| 115 | CR0_EM equ 0x00000004 ;fpu emulation |
115 | CR0_EM = 0x00000004 ;fpu emulation |
| 116 | CR0_TS equ 0x00000008 ;task switch |
116 | CR0_TS = 0x00000008 ;task switch |
| 117 | CR0_ET equ 0x00000010 ;extension type hardcoded to 1 |
117 | CR0_ET = 0x00000010 ;extension type hardcoded to 1 |
| 118 | CR0_NE equ 0x00000020 ;numeric error |
118 | CR0_NE = 0x00000020 ;numeric error |
| 119 | CR0_WP equ 0x00010000 ;write protect |
119 | CR0_WP = 0x00010000 ;write protect |
| 120 | CR0_AM equ 0x00040000 ;alignment check |
120 | CR0_AM = 0x00040000 ;alignment check |
| 121 | CR0_NW equ 0x20000000 ;not write-through |
121 | CR0_NW = 0x20000000 ;not write-through |
| 122 | CR0_CD equ 0x40000000 ;cache disable |
122 | CR0_CD = 0x40000000 ;cache disable |
| 123 | CR0_PG equ 0x80000000 ;paging |
123 | CR0_PG = 0x80000000 ;paging |
| 124 | 124 | ||
| 125 | 125 | ||
| 126 | CR4_VME equ 0x000001 |
126 | CR4_VME = 0x000001 |
| 127 | CR4_PVI equ 0x000002 |
127 | CR4_PVI = 0x000002 |
| 128 | CR4_TSD equ 0x000004 |
128 | CR4_TSD = 0x000004 |
| 129 | CR4_DE equ 0x000008 |
129 | CR4_DE = 0x000008 |
| 130 | CR4_PSE equ 0x000010 |
130 | CR4_PSE = 0x000010 |
| 131 | CR4_PAE equ 0x000020 |
131 | CR4_PAE = 0x000020 |
| 132 | CR4_MCE equ 0x000040 |
132 | CR4_MCE = 0x000040 |
| 133 | CR4_PGE equ 0x000080 |
133 | CR4_PGE = 0x000080 |
| 134 | CR4_PCE equ 0x000100 |
134 | CR4_PCE = 0x000100 |
| 135 | CR4_OSFXSR equ 0x000200 |
135 | CR4_OSFXSR = 0x000200 |
| 136 | CR4_OSXMMEXPT equ 0x000400 |
136 | CR4_OSXMMEXPT = 0x000400 |
| 137 | CR4_OSXSAVE equ 0x040000 |
137 | CR4_OSXSAVE = 0x040000 |
| 138 | 138 | ||
| 139 | XCR0_FPU_MMX equ 0x0001 |
139 | XCR0_FPU_MMX = 0x0001 |
| 140 | XCR0_SSE equ 0x0002 |
140 | XCR0_SSE = 0x0002 |
| 141 | XCR0_AVX equ 0x0004 |
141 | XCR0_AVX = 0x0004 |
| 142 | XCR0_MPX equ 0x0018 |
142 | XCR0_MPX = 0x0018 |
| 143 | XCR0_AVX512 equ 0x00e0 |
143 | XCR0_AVX512 = 0x00e0 |
| 144 | 144 | ||
| 145 | MXCSR_IE equ 0x0001 |
145 | MXCSR_IE = 0x0001 |
| 146 | MXCSR_DE equ 0x0002 |
146 | MXCSR_DE = 0x0002 |
| 147 | MXCSR_ZE equ 0x0004 |
147 | MXCSR_ZE = 0x0004 |
| 148 | MXCSR_OE equ 0x0008 |
148 | MXCSR_OE = 0x0008 |
| 149 | MXCSR_UE equ 0x0010 |
149 | MXCSR_UE = 0x0010 |
| 150 | MXCSR_PE equ 0x0020 |
150 | MXCSR_PE = 0x0020 |
| 151 | MXCSR_DAZ equ 0x0040 |
151 | MXCSR_DAZ = 0x0040 |
| 152 | MXCSR_IM equ 0x0080 |
152 | MXCSR_IM = 0x0080 |
| 153 | MXCSR_DM equ 0x0100 |
153 | MXCSR_DM = 0x0100 |
| 154 | MXCSR_ZM equ 0x0200 |
154 | MXCSR_ZM = 0x0200 |
| 155 | MXCSR_OM equ 0x0400 |
155 | MXCSR_OM = 0x0400 |
| 156 | MXCSR_UM equ 0x0800 |
156 | MXCSR_UM = 0x0800 |
| 157 | MXCSR_PM equ 0x1000 |
157 | MXCSR_PM = 0x1000 |
| 158 | MXCSR_FZ equ 0x8000 |
158 | MXCSR_FZ = 0x8000 |
| 159 | 159 | ||
| 160 | MXCSR_INIT equ (MXCSR_IM+MXCSR_DM+MXCSR_ZM+MXCSR_OM+MXCSR_UM+MXCSR_PM) |
160 | MXCSR_INIT = MXCSR_IM + MXCSR_DM + MXCSR_ZM + MXCSR_OM + MXCSR_UM + MXCSR_PM |
| 161 | 161 | ||
| 162 | EFLAGS_CF equ 0x000001 ; carry flag |
162 | EFLAGS_CF = 0x000001 ; carry flag |
| 163 | EFLAGS_PF equ 0x000004 ; parity flag |
163 | EFLAGS_PF = 0x000004 ; parity flag |
| 164 | EFLAGS_AF equ 0x000010 ; auxiliary flag |
164 | EFLAGS_AF = 0x000010 ; auxiliary flag |
| 165 | EFLAGS_ZF equ 0x000040 ; zero flag |
165 | EFLAGS_ZF = 0x000040 ; zero flag |
| 166 | EFLAGS_SF equ 0x000080 ; sign flag |
166 | EFLAGS_SF = 0x000080 ; sign flag |
| 167 | EFLAGS_TF equ 0x000100 ; trap flag |
167 | EFLAGS_TF = 0x000100 ; trap flag |
| 168 | EFLAGS_IF equ 0x000200 ; interrupt flag |
168 | EFLAGS_IF = 0x000200 ; interrupt flag |
| Line 169... | Line 169... | ||
| 169 | EFLAGS_DF equ 0x000400 ; direction flag |
169 | EFLAGS_DF = 0x000400 ; direction flag |
| 170 | EFLAGS_OF equ 0x000800 ; overflow flag |
170 | EFLAGS_OF = 0x000800 ; overflow flag |
| Line 171... | Line 171... | ||
| 171 | EFLAGS_IOPL equ 0x003000 ; i/o priviledge level |
171 | EFLAGS_IOPL = 0x003000 ; i/o priviledge level |
| 172 | EFLAGS_NT equ 0x004000 ; nested task flag |
172 | EFLAGS_NT = 0x004000 ; nested task flag |
| 173 | EFLAGS_RF equ 0x010000 ; resume flag |
173 | EFLAGS_RF = 0x010000 ; resume flag |
| 174 | EFLAGS_VM equ 0x020000 ; virtual 8086 mode flag |
174 | EFLAGS_VM = 0x020000 ; virtual 8086 mode flag |
| Line 211... | Line 211... | ||
| 211 | rb 24 |
211 | rb 24 |
| 212 | _io_map_0 rb 4096 |
212 | _io_map_0 rb 4096 |
| 213 | _io_map_1 rb 4096 |
213 | _io_map_1 rb 4096 |
| 214 | ends |
214 | ends |
| Line 215... | Line 215... | ||
| 215 | 215 | ||
| Line 216... | Line 216... | ||
| 216 | DRIVE_DATA_SIZE equ 16 |
216 | DRIVE_DATA_SIZE = 16 |
| Line 217... | Line 217... | ||
| 217 | 217 | ||
| Line 218... | Line 218... | ||
| 218 | OS_BASE equ 0x80000000 |
218 | OS_BASE = 0x80000000 |
| 219 | 219 | ||
| 220 | window_data equ (OS_BASE+0x0001000) |
220 | window_data = OS_BASE + 0x0001000 |
| 221 | 221 | ||
| 222 | CURRENT_TASK equ (OS_BASE+0x0003000) |
222 | CURRENT_TASK = OS_BASE + 0x0003000 |
| Line 223... | Line 223... | ||
| 223 | TASK_COUNT equ (OS_BASE+0x0003004) |
223 | TASK_COUNT = OS_BASE + 0x0003004 |
| Line 224... | Line 224... | ||
| 224 | TASK_BASE equ (OS_BASE+0x0003010) |
224 | TASK_BASE = OS_BASE + 0x0003010 |
| Line 225... | Line 225... | ||
| 225 | TASK_DATA equ (OS_BASE+0x0003020) |
225 | TASK_DATA = OS_BASE + 0x0003020 |
| Line 226... | Line 226... | ||
| 226 | TASK_EVENT equ (OS_BASE+0x0003020) |
226 | TASK_EVENT = OS_BASE + 0x0003020 |
| 227 | 227 | ||
| 228 | CDDataBuf equ (OS_BASE+0x0005000) |
228 | CDDataBuf = OS_BASE + 0x0005000 |
| 229 | 229 | ||
| Line 230... | Line 230... | ||
| 230 | ;unused 0x6000 - 0x8fff |
230 | ;unused 0x6000 - 0x8fff |
| 231 | 231 | ||
| 232 | BOOT_VARS equ 0x9000 |
232 | BOOT_VARS = 0x9000 |
| Line 233... | Line 233... | ||
| 233 | 233 | ||
| 234 | idts equ (OS_BASE+0x000B100) |
234 | idts = OS_BASE + 0x000B100 |
| Line 235... | Line 235... | ||
| 235 | WIN_STACK equ (OS_BASE+0x000C000) |
235 | WIN_STACK = OS_BASE + 0x000C000 |
| 236 | WIN_POS equ (OS_BASE+0x000C400) |
236 | WIN_POS = OS_BASE + 0x000C400 |
| Line 237... | Line 237... | ||
| 237 | FDD_BUFF equ (OS_BASE+0x000D000) ;512 |
237 | FDD_BUFF = OS_BASE + 0x000D000 ;512 |
| 238 | 238 | ||
| Line 239... | Line 239... | ||
| 239 | WIN_TEMP_XY equ (OS_BASE+0x000F300) |
239 | WIN_TEMP_XY = OS_BASE + 0x000F300 |
| Line 240... | Line 240... | ||
| 240 | KEY_COUNT equ (OS_BASE+0x000F400) |
240 | KEY_COUNT = OS_BASE + 0x000F400 |
| Line 241... | Line 241... | ||
| 241 | KEY_BUFF equ (OS_BASE+0x000F401) ; 120*2 + 2*2 = 244 bytes, actually 255 bytes |
241 | KEY_BUFF = OS_BASE + 0x000F401 ; 120*2 + 2*2 = 244 bytes, actually 255 bytes |
| Line 242... | Line 242... | ||
| 242 | 242 | ||
| Line 243... | Line 243... | ||
| 243 | BTN_COUNT equ (OS_BASE+0x000F500) |
243 | BTN_COUNT = OS_BASE + 0x000F500 |
| Line 244... | Line -... | ||
| 244 | BTN_BUFF equ (OS_BASE+0x000F501) |
- | |
| 245 | - | ||
| 246 | 244 | BTN_BUFF = OS_BASE + 0x000F501 |
|
| 247 | BTN_ADDR equ (OS_BASE+0x000FE88) |
245 | |
| 248 | MEM_AMOUNT equ (OS_BASE+0x000FE8C) |
246 | |
| Line 249... | Line 247... | ||
| 249 | 247 | BTN_ADDR = OS_BASE + 0x000FE88 |
|
| 250 | SYS_SHUTDOWN equ (OS_BASE+0x000FF00) |
248 | MEM_AMOUNT = OS_BASE + 0x000FE8C |
| Line 251... | Line 249... | ||
| 251 | TASK_ACTIVATE equ (OS_BASE+0x000FF01) |
249 | |
| 252 | 250 | SYS_SHUTDOWN = OS_BASE + 0x000FF00 |
|
| 253 | 251 | TASK_ACTIVATE = OS_BASE + 0x000FF01 |
|
| 254 | TMP_STACK_TOP equ 0x006CC00 |
252 | |
| 255 | 253 | ||
| 256 | sys_proc equ (OS_BASE+0x006F000) |
254 | TMP_STACK_TOP = 0x006CC00 |
| 257 | 255 | ||
| 258 | SLOT_BASE equ (OS_BASE+0x0080000) |
256 | sys_proc = OS_BASE + 0x006F000 |
| 259 | 257 | ||
| 260 | VGABasePtr equ (OS_BASE+0x00A0000) |
258 | SLOT_BASE = OS_BASE + 0x0080000 |
| 261 | 259 | ||
| 262 | CLEAN_ZONE equ (_CLEAN_ZONE-OS_BASE) |
260 | VGABasePtr = OS_BASE + 0x00A0000 |
| 263 | 261 | ||
| 264 | UPPER_KERNEL_PAGES equ (OS_BASE+0x0400000) |
262 | UPPER_KERNEL_PAGES = OS_BASE + 0x0400000 |
| 265 | 263 | ||
| 266 | virtual at (OS_BASE+0x05FFF80) |
264 | virtual at OS_BASE + 0x05FFF80 |
| 267 | tss TSS |
265 | tss TSS |
| 268 | end virtual |
266 | end virtual |
| 269 | 267 | ||
| 270 | HEAP_BASE equ (OS_BASE+0x0800000) |
268 | HEAP_BASE = OS_BASE + 0x0800000 |
| 271 | HEAP_MIN_SIZE equ 0x01000000 |
269 | HEAP_MIN_SIZE = 0x01000000 |
| 272 | 270 | ||
| 273 | page_tabs equ 0xFDC00000 |
271 | page_tabs = 0xFDC00000 |
| 274 | app_page_tabs equ 0xFDC00000 |
272 | app_page_tabs = 0xFDC00000 |
| 275 | kernel_tabs equ (page_tabs+ (OS_BASE shr 10)) ;0xFDE00000 |
273 | kernel_tabs = page_tabs + (OS_BASE shr 10) ;0xFDE00000 |
| 276 | master_tab equ (page_tabs+ (page_tabs shr 10)) ;0xFDFF70000 |
274 | master_tab = page_tabs + (page_tabs shr 10) ;0xFDFF70000 |
| 277 | 275 | ||
| 278 | LFB_BASE equ 0xFE000000 |
276 | LFB_BASE = 0xFE000000 |
| 279 | 277 | ||
| 280 | 278 | ||
| 281 | new_app_base equ 0; |
279 | new_app_base = 0; |
| 282 | 280 | ||
| 283 | twdw equ 0x2000 ;(CURRENT_TASK-window_data) |
281 | twdw = 0x2000 ; CURRENT_TASK - window_data |
| 284 | 282 | ||
| 285 | std_application_base_address equ new_app_base |
283 | std_application_base_address = new_app_base |
| 286 | RING0_STACK_SIZE equ 0x2000 |
284 | RING0_STACK_SIZE = 0x2000 |
| 287 | 285 | ||
| 288 | REG_SS equ (RING0_STACK_SIZE-4) |
286 | REG_SS = RING0_STACK_SIZE - 4 |
| 289 | REG_APP_ESP equ (RING0_STACK_SIZE-8) |
287 | REG_APP_ESP = RING0_STACK_SIZE - 8 |
| 290 | REG_EFLAGS equ (RING0_STACK_SIZE-12) |
288 | REG_EFLAGS = RING0_STACK_SIZE - 12 |
| 291 | REG_CS equ (RING0_STACK_SIZE-16) |
289 | REG_CS = RING0_STACK_SIZE - 16 |
| 292 | REG_EIP equ (RING0_STACK_SIZE-20) |
290 | REG_EIP = RING0_STACK_SIZE - 20 |
| 293 | REG_EAX equ (RING0_STACK_SIZE-24) |
291 | REG_EAX = RING0_STACK_SIZE - 24 |
| 294 | REG_ECX equ (RING0_STACK_SIZE-28) |
292 | REG_ECX = RING0_STACK_SIZE - 28 |
| 295 | REG_EDX equ (RING0_STACK_SIZE-32) |
293 | REG_EDX = RING0_STACK_SIZE - 32 |
| 296 | REG_EBX equ (RING0_STACK_SIZE-36) |
294 | REG_EBX = RING0_STACK_SIZE - 36 |
| 297 | REG_ESP equ (RING0_STACK_SIZE-40) ;RING0_STACK_SIZE-20 |
295 | REG_ESP = RING0_STACK_SIZE - 40 ;RING0_STACK_SIZE-20 |
| 298 | REG_EBP equ (RING0_STACK_SIZE-44) |
296 | REG_EBP = RING0_STACK_SIZE - 44 |
| 299 | REG_ESI equ (RING0_STACK_SIZE-48) |
297 | REG_ESI = RING0_STACK_SIZE - 48 |
| 300 | REG_EDI equ (RING0_STACK_SIZE-52) |
298 | REG_EDI = RING0_STACK_SIZE - 52 |
| 301 | REG_RET equ (RING0_STACK_SIZE-56) ;irq0.return |
299 | REG_RET = RING0_STACK_SIZE - 56 ;irq0.return |
| - | 300 | ||
| - | 301 | ||
| - | 302 | PAGE_SIZE = 4096 |
|
| - | 303 | ||
| 302 | 304 | PG_UNMAP = 0x000 |
|
| 303 | 305 | PG_READ = 0x001 |
|
| 304 | PAGE_SIZE equ 4096 |
306 | PG_WRITE = 0x002 |
| 305 | 307 | PG_USER = 0x004 |
|
| 306 | PG_UNMAP equ 0x000 |
308 | PG_PCD = 0x008 |
| 307 | PG_READ equ 0x001 |
309 | PG_PWT = 0x010 |
| 308 | PG_WRITE equ 0x002 |
310 | PG_ACCESSED = 0x020 |
| 309 | PG_USER equ 0x004 |
311 | PG_DIRTY = 0x040 |
| 310 | PG_PCD equ 0x008 |
312 | PG_PAT = 0x080 |
| 311 | PG_PWT equ 0x010 |
313 | PG_GLOBAL = 0x100 |
| 312 | PG_ACCESSED equ 0x020 |
314 | PG_SHARED = 0x200 |
| 313 | PG_DIRTY equ 0x040 |
315 | |
| 314 | PG_PAT equ 0x080 |
316 | PG_SWR = 0x003 ; PG_WRITE + PG_READ |
| 315 | PG_GLOBAL equ 0x100 |
317 | PG_UR = 0x005 ; PG_USER + PG_READ |
| 316 | PG_SHARED equ 0x200 |
318 | PG_UWR = 0x007 ; PG_USER + PG_WRITE + PG_READ |
| 317 | 319 | PG_NOCACHE = 0x018 ; PG_PCD + PG_PWT |
|
| 318 | PG_SWR equ 0x003 ; (PG_WRITE+PG_READ) |
320 | |
| 319 | PG_UR equ 0x005 ; (PG_USER+PG_READ) |
321 | PDE_LARGE = 0x080 |
| 320 | PG_UWR equ 0x007 ; (PG_USER+PG_WRITE+PG_READ) |
322 | |
| 321 | PG_NOCACHE equ 0x018 ; (PG_PCD+PG_PWT) |
323 | MEM_WB = 6 ; write-back memory |
| 322 | 324 | MEM_WC = 1 ; write combined memory |
|
| 323 | PDE_LARGE equ 0x080 |
325 | MEM_UC = 0 ; uncached memory |
| 324 | 326 | ||
| 325 | PAT_WB equ 0x000 |
327 | PAT_WB = 0x000 |
| 326 | PAT_WC equ 0x008 |
328 | PAT_WC = 0x008 |
| 327 | PAT_UCM equ 0x010 |
329 | PAT_UCM = 0x010 |
| 328 | PAT_UC equ 0x018 |
330 | PAT_UC = 0x018 |
| 329 | 331 | ||
| 330 | PAT_TYPE_UC equ 0 |
332 | PAT_TYPE_UC = 0 |
| 331 | PAT_TYPE_WC equ 1 |
333 | PAT_TYPE_WC = 1 |
| 332 | PAT_TYPE_WB equ 6 |
334 | PAT_TYPE_WB = 6 |
| 333 | PAT_TYPE_UCM equ 7 |
335 | PAT_TYPE_UCM = 7 |
| 334 | 336 | ||
| 335 | PAT_VALUE equ 0x00070106; (UC<<24)|(UCM<<16)|(WC<<8)|WB |
337 | PAT_VALUE = 0x00070106; (UC<<24)|(UCM<<16)|(WC<<8)|WB |
| 336 | 338 | ||
| 337 | MAX_MEMMAP_BLOCKS equ 32 |
339 | MAX_MEMMAP_BLOCKS = 32 |
| 338 | 340 | ||
| 339 | TMP_FILE_NAME equ 0 |
341 | TMP_FILE_NAME = 0 |
| 340 | TMP_CMD_LINE equ 1024 |
342 | TMP_CMD_LINE = 1024 |
| 341 | TMP_ICON_OFFS equ 1280 |
343 | TMP_ICON_OFFS = 1280 |
| Line 342... | Line 344... | ||
| 342 | 344 | ||
| Line 343... | Line 345... | ||
| 343 | 345 | ||
| 344 | EVENT_REDRAW equ 0x00000001 |
346 | EVENT_REDRAW = 0x00000001 |
| 345 | EVENT_KEY equ 0x00000002 |
347 | EVENT_KEY = 0x00000002 |
| 346 | EVENT_BUTTON equ 0x00000004 |
348 | EVENT_BUTTON = 0x00000004 |
| Line 406... | Line 408... | ||
| 406 | wait_list LHEAD |
408 | wait_list LHEAD |
| 407 | pointer dd ? |
409 | pointer dd ? |
| 408 | flags dd ? |
410 | flags dd ? |
| 409 | ends |
411 | ends |
| Line 410... | Line 412... | ||
| 410 | 412 | ||
| 411 | FUTEX_INIT equ 0 |
413 | FUTEX_INIT = 0 |
| 412 | FUTEX_DESTROY equ 1 |
414 | FUTEX_DESTROY = 1 |
| 413 | FUTEX_WAIT equ 2 |
415 | FUTEX_WAIT = 2 |
| Line 414... | Line 416... | ||
| 414 | FUTEX_WAKE equ 3 |
416 | FUTEX_WAKE = 3 |
| 415 | 417 | ||
| 416 | struct FILED |
418 | struct FILED |
| 417 | list LHEAD |
419 | list LHEAD |
| Line 534... | Line 536... | ||
| 534 | wnd_clientbox BOX ;+216 |
536 | wnd_clientbox BOX ;+216 |
| 535 | priority dd ? ;+232 |
537 | priority dd ? ;+232 |
| 536 | in_schedule LHEAD ;+236 |
538 | in_schedule LHEAD ;+236 |
| 537 | ends |
539 | ends |
| Line 538... | Line 540... | ||
| 538 | 540 | ||
| 539 | APP_OBJ_OFFSET equ 48 |
541 | APP_OBJ_OFFSET = 48 |
| Line 540... | Line 542... | ||
| 540 | APP_EV_OFFSET equ 40 |
542 | APP_EV_OFFSET = 40 |
| 541 | 543 | ||
| 542 | struct TASKDATA |
544 | struct TASKDATA |
| 543 | event_mask dd ? |
545 | event_mask dd ? |
| Line 884... | Line 886... | ||
| 884 | strucsize dd ? |
886 | strucsize dd ? |
| 885 | add_device dd ? |
887 | add_device dd ? |
| 886 | device_disconnect dd ? |
888 | device_disconnect dd ? |
| 887 | ends |
889 | ends |
| Line 888... | Line 890... | ||
| 888 | 890 | ||
| 889 | DRV_ENTRY equ 1 |
891 | DRV_ENTRY = 1 |
| Line 890... | Line 892... | ||
| 890 | DRV_EXIT equ -1 |
892 | DRV_EXIT = -1 |
| 891 | 893 | ||
| 892 | struct COFF_HEADER |
894 | struct COFF_HEADER |
| 893 | machine dw ? |
895 | machine dw ? |