WebSVN – Kolibri OS – Diff – /kernel/trunk/bus/pci/pci32.inc


$Revision: 465 $
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                           ;;
;; Copyright (C) KolibriOS team 2004-2007. All rights reserved. ;;
;; Distributed under terms of the GNU General Public License    ;;
;;                                                              ;;
;;                                                              ;;
;;  PCI32.INC                                                ;;
;;                                                           ;;
;;  32 bit PCI driver code                                   ;;
;;                                                           ;;
;;  Version 0.2  December 21st, 2002                         ;;
;;                                                           ;;
;;  Author: Victor Prodan, victorprodan@yahoo.com            ;;
;;    Credits:                                               ;;
;;          Ralf Brown                                       ;;
;;          Mike Hibbett, mikeh@oceanfree.net                ;;
;;                                                           ;;
;;  See file COPYING for details                             ;;
;;                                                           ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 
;***************************************************************************
;   Function
;      pci_api:
;
;   Description
;       entry point for system PCI calls
;***************************************************************************
 
align 4
 
pci_api:
 
        cmp  [pci_access_enabled],1
        jne  no_pci_access_for_applications
 
        or al,al
        jnz pci_fn_1
        ; PCI function 0: get pci version (AH.AL)
        movzx eax,word [BOOT_VAR+0x9022]
        ret
 
pci_fn_1:
        cmp al,1
        jnz pci_fn_2
 
        ; PCI function 1: get last bus in AL
        mov al,[BOOT_VAR+0x9021]
        ret
 
pci_fn_2:
        cmp al,2
        jne pci_fn_3
        ; PCI function 2: get pci access mechanism
        mov al,[BOOT_VAR+0x9020]
        ret
pci_fn_3:
 
        cmp al,4
        jz pci_read_reg   ;byte
        cmp al,5
        jz pci_read_reg   ;word
        cmp al,6
        jz pci_read_reg   ;dword
 
        cmp al,8
        jz pci_write_reg  ;byte
        cmp al,9
        jz pci_write_reg  ;word
        cmp al,10
        jz pci_write_reg  ;dword
 
      no_pci_access_for_applications:
 
        mov eax,-1
 
        ret
 
;***************************************************************************
;   Function
;      pci_make_config_cmd
;
;   Description
;       creates a command dword  for use with the PCI bus
;       bus # in ah
;       device+func in bh (dddddfff)
;       register in bl
;
;      command dword returned in eax ( 10000000 bbbbbbbb dddddfff rrrrrr00 )
;***************************************************************************
 
align 4
 
pci_make_config_cmd:
    shl     eax,8          ; move bus to bits 16-23
    mov     ax,bx          ; combine all
    and     eax,0xffffff
    or      eax,0x80000000
    ret
 
;***************************************************************************
;   Function
;      pci_read_reg:
;
;   Description
;       read a register from the PCI config space into EAX/AX/AL
;       IN: ah=bus,device+func=bh,register address=bl
;           number of bytes to read (1,2,4) coded into AL, bits 0-1
;***************************************************************************
 
align 4
 
pci_read_reg:
        cmp     byte [BOOT_VAR+0x9020],2 ;what mechanism will we use?
        je      pci_read_reg_2
 
                ; mechanism 1
        push    esi   ; save register size into ESI
        mov     esi,eax
        and     esi,3
 
        call    pci_make_config_cmd
        mov     ebx,eax
                ; get current state
        mov     dx,0xcf8
        in      eax, dx
        push    eax
                ; set up addressing to config data
        mov     eax,ebx
        and     al,0xfc ; make address dword-aligned
        out     dx,eax
                ; get requested DWORD of config data
        mov     dl,0xfc
        and     bl,3
        or      dl,bl    ; add to port address first 2 bits of register address
 
        or      esi,esi
        jz      pci_read_byte1
        cmp     esi,1
        jz      pci_read_word1
        cmp     esi,2
        jz      pci_read_dword1
        jmp     pci_fin_read1
 
pci_read_byte1:
        in      al,dx
        jmp pci_fin_read1
pci_read_word1:
        in      ax,dx
        jmp pci_fin_read1
pci_read_dword1:
        in      eax,dx
        jmp     pci_fin_read1
pci_fin_read1:
                ; restore configuration control
        xchg    eax,[esp]
        mov     dx,0xcf8
        out     dx,eax
 
        pop     eax
        pop     esi
        ret
pci_read_reg_2:
 
        test    bh,128  ;mech#2 only supports 16 devices per bus
        jnz     pci_read_reg_err
 
        push esi   ; save register size into ESI
        mov esi,eax
        and esi,3
 
        push    eax
                ;store current state of config space
        mov     dx,0xcf8
        in      al,dx
        mov     ah,al
        mov     dl,0xfa
        in      al,dx
 
        xchg    eax,[esp]
                ; out 0xcfa,bus
        mov     al,ah
        out     dx,al
                ; out 0xcf8,0x80
        mov     dl,0xf8
        mov     al,0x80
        out     dx,al
                ; compute addr
        shr     bh,3 ; func is ignored in mechanism 2
        or      bh,0xc0
        mov     dx,bx
 
        or      esi,esi
        jz      pci_read_byte2
        cmp     esi,1
        jz      pci_read_word2
        cmp     esi,2
        jz      pci_read_dword2
        jmp     pci_fin_read2
 
pci_read_byte2:
        in      al,dx
        jmp pci_fin_read2
pci_read_word2:
        in      ax,dx
        jmp pci_fin_read2
pci_read_dword2:
        in      eax,dx
;       jmp pci_fin_read2
pci_fin_read2:
 
                ; restore configuration space
        xchg    eax,[esp]
        mov     dx,0xcfa
        out     dx,al
        mov     dl,0xf8
        mov     al,ah
        out     dx,al
 
        pop     eax
        pop     esi
        ret
 
pci_read_reg_err:
        xor     eax,eax
        dec     eax
        ret
 
 
;***************************************************************************
;   Function
;      pci_write_reg:
;
;   Description
;       write a register from ECX/CX/CL into the PCI config space
;       IN: ah=bus,device+func=bh,register address (dword aligned)=bl,
;           value to write in ecx
;           number of bytes to write (1,2,4) coded into AL, bits 0-1
;***************************************************************************
 
align 4
 
pci_write_reg:
        cmp byte [BOOT_VAR+0x9020],2 ;what mechanism will we use?
        je pci_write_reg_2
 
                ; mechanism 1
        push    esi   ; save register size into ESI
        mov     esi,eax
        and     esi,3
 
        call    pci_make_config_cmd
        mov     ebx,eax
                ; get current state into ecx
        mov     dx,0xcf8
        in      eax, dx
        push    eax
                ; set up addressing to config data
        mov     eax,ebx
        and     al,0xfc ; make address dword-aligned
        out     dx,eax
                ; write DWORD of config data
        mov     dl,0xfc
        and     bl,3
        or      dl,bl
        mov     eax,ecx
 
        or      esi,esi
        jz      pci_write_byte1
        cmp     esi,1
        jz      pci_write_word1
        cmp     esi,2
        jz      pci_write_dword1
        jmp     pci_fin_write1
 
pci_write_byte1:
        out     dx,al
        jmp pci_fin_write1
pci_write_word1:
        out     dx,ax
        jmp pci_fin_write1
pci_write_dword1:
        out     dx,eax
        jmp     pci_fin_write1
pci_fin_write1:
 
                ; restore configuration control
        pop     eax
        mov     dl,0xf8
        out     dx,eax
 
        xor     eax,eax
        pop     esi
 
        ret
pci_write_reg_2:
 
        test    bh,128  ;mech#2 only supports 16 devices per bus
        jnz     pci_write_reg_err
 
 
        push esi   ; save register size into ESI
        mov esi,eax
        and esi,3
 
        push    eax
                ;store current state of config space
        mov     dx,0xcf8
        in      al,dx
        mov     ah,al
        mov     dl,0xfa
        in      al,dx
        xchg    eax,[esp]
                ; out 0xcfa,bus
        mov     al,ah
        out     dx,al
                ; out 0xcf8,0x80
        mov     dl,0xf8
        mov     al,0x80
        out     dx,al
                ; compute addr
        shr     bh,3 ; func is ignored in mechanism 2
        or      bh,0xc0
        mov     dx,bx
                ; write register
        mov     eax,ecx
 
        or      esi,esi
        jz      pci_write_byte2
        cmp     esi,1
        jz      pci_write_word2
        cmp     esi,2
        jz      pci_write_dword2
        jmp     pci_fin_write2
 
pci_write_byte2:
        out     dx,al
        jmp pci_fin_write2
pci_write_word2:
        out     dx,ax
        jmp pci_fin_write2
pci_write_dword2:
        out     dx,eax
        jmp     pci_fin_write2
pci_fin_write2:
                ; restore configuration space
        pop     eax
        mov     dx,0xcfa
        out     dx,al
        mov     dl,0xf8
        mov     al,ah
        out     dx,al
 
        xor     eax,eax
        pop     esi
        ret
 
pci_write_reg_err:
        xor     eax,eax
        dec     eax
        ret

Rev 431	Rev 465
1	$Revision: 431 $	1	$Revision: 465 $
2	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	2	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3	;; ;;	3	;; ;;
4	;; Copyright (C) KolibriOS team 2004-2007. All rights reserved. ;;	4	;; Copyright (C) KolibriOS team 2004-2007. All rights reserved. ;;
5	;; Distributed under terms of the GNU General Public License ;;	5	;; Distributed under terms of the GNU General Public License ;;
6	;; ;;	6	;; ;;
7	;; ;;	7	;; ;;
8	;; PCI32.INC ;;	8	;; PCI32.INC ;;
9	;; ;;	9	;; ;;
10	;; 32 bit PCI driver code ;;	10	;; 32 bit PCI driver code ;;
11	;; ;;	11	;; ;;
12	;; Version 0.2 December 21st, 2002 ;;	12	;; Version 0.2 December 21st, 2002 ;;
13	;; ;;	13	;; ;;
14	;; Author: Victor Prodan, victorprodan@yahoo.com ;;	14	;; Author: Victor Prodan, victorprodan@yahoo.com ;;
15	;; Credits: ;;	15	;; Credits: ;;
16	;; Ralf Brown ;;	16	;; Ralf Brown ;;
17	;; Mike Hibbett, mikeh@oceanfree.net ;;	17	;; Mike Hibbett, mikeh@oceanfree.net ;;
18	;; ;;	18	;; ;;
19	;; See file COPYING for details ;;	19	;; See file COPYING for details ;;
20	;; ;;	20	;; ;;
21	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;	21	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
22		22
23		23
24	;***************************************************************************	24	;***************************************************************************
25	; Function	25	; Function
26	; pci_api:	26	; pci_api:
27	;	27	;
28	; Description	28	; Description
29	; entry point for system PCI calls	29	; entry point for system PCI calls
30	;***************************************************************************	30	;***************************************************************************
31		31
32	align 4	32	align 4
33		33
34	pci_api:	34	pci_api:
35		35
36	cmp [pci_access_enabled],1	36	cmp [pci_access_enabled],1
37	jne no_pci_access_for_applications	37	jne no_pci_access_for_applications
38		38
39	or al,al	39	or al,al
40	jnz pci_fn_1	40	jnz pci_fn_1
41	; PCI function 0: get pci version (AH.AL)	41	; PCI function 0: get pci version (AH.AL)
42	movzx eax,word [0x2F0000+0x9022]	42	movzx eax,word [BOOT_VAR+0x9022]
43	ret	43	ret
44		44
45	pci_fn_1:	45	pci_fn_1:
46	cmp al,1	46	cmp al,1
47	jnz pci_fn_2	47	jnz pci_fn_2
48		48
49	; PCI function 1: get last bus in AL	49	; PCI function 1: get last bus in AL
50	mov al,[0x2F0000+0x9021]	50	mov al,[BOOT_VAR+0x9021]
51	ret	51	ret
52		52
53	pci_fn_2:	53	pci_fn_2:
54	cmp al,2	54	cmp al,2
55	jne pci_fn_3	55	jne pci_fn_3
56	; PCI function 2: get pci access mechanism	56	; PCI function 2: get pci access mechanism
57	mov al,[0x2F0000+0x9020]	57	mov al,[BOOT_VAR+0x9020]
58	ret	58	ret
59	pci_fn_3:	59	pci_fn_3:
60		60
61	cmp al,4	61	cmp al,4
62	jz pci_read_reg ;byte	62	jz pci_read_reg ;byte
63	cmp al,5	63	cmp al,5
64	jz pci_read_reg ;word	64	jz pci_read_reg ;word
65	cmp al,6	65	cmp al,6
66	jz pci_read_reg ;dword	66	jz pci_read_reg ;dword
67		67
68	cmp al,8	68	cmp al,8
69	jz pci_write_reg ;byte	69	jz pci_write_reg ;byte
70	cmp al,9	70	cmp al,9
71	jz pci_write_reg ;word	71	jz pci_write_reg ;word
72	cmp al,10	72	cmp al,10
73	jz pci_write_reg ;dword	73	jz pci_write_reg ;dword
74		74
75	no_pci_access_for_applications:	75	no_pci_access_for_applications:
76		76
77	mov eax,-1	77	mov eax,-1
78		78
79	ret	79	ret
80		80
81	;***************************************************************************	81	;***************************************************************************
82	; Function	82	; Function
83	; pci_make_config_cmd	83	; pci_make_config_cmd
84	;	84	;
85	; Description	85	; Description
86	; creates a command dword for use with the PCI bus	86	; creates a command dword for use with the PCI bus
87	; bus # in ah	87	; bus # in ah
88	; device+func in bh (dddddfff)	88	; device+func in bh (dddddfff)
89	; register in bl	89	; register in bl
90	;	90	;
91	; command dword returned in eax ( 10000000 bbbbbbbb dddddfff rrrrrr00 )	91	; command dword returned in eax ( 10000000 bbbbbbbb dddddfff rrrrrr00 )
92	;***************************************************************************	92	;***************************************************************************
93		93
94	align 4	94	align 4
95		95
96	pci_make_config_cmd:	96	pci_make_config_cmd:
97	shl eax,8 ; move bus to bits 16-23	97	shl eax,8 ; move bus to bits 16-23
98	mov ax,bx ; combine all	98	mov ax,bx ; combine all
99	and eax,0xffffff	99	and eax,0xffffff
100	or eax,0x80000000	100	or eax,0x80000000
101	ret	101	ret
102		102
103	;***************************************************************************	103	;***************************************************************************
104	; Function	104	; Function
105	; pci_read_reg:	105	; pci_read_reg:
106	;	106	;
107	; Description	107	; Description
108	; read a register from the PCI config space into EAX/AX/AL	108	; read a register from the PCI config space into EAX/AX/AL
109	; IN: ah=bus,device+func=bh,register address=bl	109	; IN: ah=bus,device+func=bh,register address=bl
110	; number of bytes to read (1,2,4) coded into AL, bits 0-1	110	; number of bytes to read (1,2,4) coded into AL, bits 0-1
111	;***************************************************************************	111	;***************************************************************************
112		112
113	align 4	113	align 4
114		114
115	pci_read_reg:	115	pci_read_reg:
116	cmp byte [0x2F0000+0x9020],2 ;what mechanism will we use?	116	cmp byte [BOOT_VAR+0x9020],2 ;what mechanism will we use?
117	je pci_read_reg_2	117	je pci_read_reg_2
118		118
119	; mechanism 1	119	; mechanism 1
120	push esi ; save register size into ESI	120	push esi ; save register size into ESI
121	mov esi,eax	121	mov esi,eax
122	and esi,3	122	and esi,3
123		123
124	call pci_make_config_cmd	124	call pci_make_config_cmd
125	mov ebx,eax	125	mov ebx,eax
126	; get current state	126	; get current state
127	mov dx,0xcf8	127	mov dx,0xcf8
128	in eax, dx	128	in eax, dx
129	push eax	129	push eax
130	; set up addressing to config data	130	; set up addressing to config data
131	mov eax,ebx	131	mov eax,ebx
132	and al,0xfc ; make address dword-aligned	132	and al,0xfc ; make address dword-aligned
133	out dx,eax	133	out dx,eax
134	; get requested DWORD of config data	134	; get requested DWORD of config data
135	mov dl,0xfc	135	mov dl,0xfc
136	and bl,3	136	and bl,3
137	or dl,bl ; add to port address first 2 bits of register address	137	or dl,bl ; add to port address first 2 bits of register address
138		138
139	or esi,esi	139	or esi,esi
140	jz pci_read_byte1	140	jz pci_read_byte1
141	cmp esi,1	141	cmp esi,1
142	jz pci_read_word1	142	jz pci_read_word1
143	cmp esi,2	143	cmp esi,2
144	jz pci_read_dword1	144	jz pci_read_dword1
145	jmp pci_fin_read1	145	jmp pci_fin_read1
146		146
147	pci_read_byte1:	147	pci_read_byte1:
148	in al,dx	148	in al,dx
149	jmp pci_fin_read1	149	jmp pci_fin_read1
150	pci_read_word1:	150	pci_read_word1:
151	in ax,dx	151	in ax,dx
152	jmp pci_fin_read1	152	jmp pci_fin_read1
153	pci_read_dword1:	153	pci_read_dword1:
154	in eax,dx	154	in eax,dx
155	jmp pci_fin_read1	155	jmp pci_fin_read1
156	pci_fin_read1:	156	pci_fin_read1:
157	; restore configuration control	157	; restore configuration control
158	xchg eax,[esp]	158	xchg eax,[esp]
159	mov dx,0xcf8	159	mov dx,0xcf8
160	out dx,eax	160	out dx,eax
161		161
162	pop eax	162	pop eax
163	pop esi	163	pop esi
164	ret	164	ret
165	pci_read_reg_2:	165	pci_read_reg_2:
166		166
167	test bh,128 ;mech#2 only supports 16 devices per bus	167	test bh,128 ;mech#2 only supports 16 devices per bus
168	jnz pci_read_reg_err	168	jnz pci_read_reg_err
169		169
170	push esi ; save register size into ESI	170	push esi ; save register size into ESI
171	mov esi,eax	171	mov esi,eax
172	and esi,3	172	and esi,3
173		173
174	push eax	174	push eax
175	;store current state of config space	175	;store current state of config space
176	mov dx,0xcf8	176	mov dx,0xcf8
177	in al,dx	177	in al,dx
178	mov ah,al	178	mov ah,al
179	mov dl,0xfa	179	mov dl,0xfa
180	in al,dx	180	in al,dx
181		181
182	xchg eax,[esp]	182	xchg eax,[esp]
183	; out 0xcfa,bus	183	; out 0xcfa,bus
184	mov al,ah	184	mov al,ah
185	out dx,al	185	out dx,al
186	; out 0xcf8,0x80	186	; out 0xcf8,0x80
187	mov dl,0xf8	187	mov dl,0xf8
188	mov al,0x80	188	mov al,0x80
189	out dx,al	189	out dx,al
190	; compute addr	190	; compute addr
191	shr bh,3 ; func is ignored in mechanism 2	191	shr bh,3 ; func is ignored in mechanism 2
192	or bh,0xc0	192	or bh,0xc0
193	mov dx,bx	193	mov dx,bx
194		194
195	or esi,esi	195	or esi,esi
196	jz pci_read_byte2	196	jz pci_read_byte2
197	cmp esi,1	197	cmp esi,1
198	jz pci_read_word2	198	jz pci_read_word2
199	cmp esi,2	199	cmp esi,2
200	jz pci_read_dword2	200	jz pci_read_dword2
201	jmp pci_fin_read2	201	jmp pci_fin_read2
202		202
203	pci_read_byte2:	203	pci_read_byte2:
204	in al,dx	204	in al,dx
205	jmp pci_fin_read2	205	jmp pci_fin_read2
206	pci_read_word2:	206	pci_read_word2:
207	in ax,dx	207	in ax,dx
208	jmp pci_fin_read2	208	jmp pci_fin_read2
209	pci_read_dword2:	209	pci_read_dword2:
210	in eax,dx	210	in eax,dx
211	; jmp pci_fin_read2	211	; jmp pci_fin_read2
212	pci_fin_read2:	212	pci_fin_read2:
213		213
214	; restore configuration space	214	; restore configuration space
215	xchg eax,[esp]	215	xchg eax,[esp]
216	mov dx,0xcfa	216	mov dx,0xcfa
217	out dx,al	217	out dx,al
218	mov dl,0xf8	218	mov dl,0xf8
219	mov al,ah	219	mov al,ah
220	out dx,al	220	out dx,al
221		221
222	pop eax	222	pop eax
223	pop esi	223	pop esi
224	ret	224	ret
225		225
226	pci_read_reg_err:	226	pci_read_reg_err:
227	xor eax,eax	227	xor eax,eax
228	dec eax	228	dec eax
229	ret	229	ret
230		230
231		231
232	;***************************************************************************	232	;***************************************************************************
233	; Function	233	; Function
234	; pci_write_reg:	234	; pci_write_reg:
235	;	235	;
236	; Description	236	; Description
237	; write a register from ECX/CX/CL into the PCI config space	237	; write a register from ECX/CX/CL into the PCI config space
238	; IN: ah=bus,device+func=bh,register address (dword aligned)=bl,	238	; IN: ah=bus,device+func=bh,register address (dword aligned)=bl,
239	; value to write in ecx	239	; value to write in ecx
240	; number of bytes to write (1,2,4) coded into AL, bits 0-1	240	; number of bytes to write (1,2,4) coded into AL, bits 0-1
241	;***************************************************************************	241	;***************************************************************************
242		242
243	align 4	243	align 4
244		244
245	pci_write_reg:	245	pci_write_reg:
246	cmp byte [0x2F0000+0x9020],2 ;what mechanism will we use?	246	cmp byte [BOOT_VAR+0x9020],2 ;what mechanism will we use?
247	je pci_write_reg_2	247	je pci_write_reg_2
248		248
249	; mechanism 1	249	; mechanism 1
250	push esi ; save register size into ESI	250	push esi ; save register size into ESI
251	mov esi,eax	251	mov esi,eax
252	and esi,3	252	and esi,3
253		253
254	call pci_make_config_cmd	254	call pci_make_config_cmd
255	mov ebx,eax	255	mov ebx,eax
256	; get current state into ecx	256	; get current state into ecx
257	mov dx,0xcf8	257	mov dx,0xcf8
258	in eax, dx	258	in eax, dx
259	push eax	259	push eax
260	; set up addressing to config data	260	; set up addressing to config data
261	mov eax,ebx	261	mov eax,ebx
262	and al,0xfc ; make address dword-aligned	262	and al,0xfc ; make address dword-aligned
263	out dx,eax	263	out dx,eax
264	; write DWORD of config data	264	; write DWORD of config data
265	mov dl,0xfc	265	mov dl,0xfc
266	and bl,3	266	and bl,3
267	or dl,bl	267	or dl,bl
268	mov eax,ecx	268	mov eax,ecx
269		269
270	or esi,esi	270	or esi,esi
271	jz pci_write_byte1	271	jz pci_write_byte1
272	cmp esi,1	272	cmp esi,1
273	jz pci_write_word1	273	jz pci_write_word1
274	cmp esi,2	274	cmp esi,2
275	jz pci_write_dword1	275	jz pci_write_dword1
276	jmp pci_fin_write1	276	jmp pci_fin_write1
277		277
278	pci_write_byte1:	278	pci_write_byte1:
279	out dx,al	279	out dx,al
280	jmp pci_fin_write1	280	jmp pci_fin_write1
281	pci_write_word1:	281	pci_write_word1:
282	out dx,ax	282	out dx,ax
283	jmp pci_fin_write1	283	jmp pci_fin_write1
284	pci_write_dword1:	284	pci_write_dword1:
285	out dx,eax	285	out dx,eax
286	jmp pci_fin_write1	286	jmp pci_fin_write1
287	pci_fin_write1:	287	pci_fin_write1:
288		288
289	; restore configuration control	289	; restore configuration control
290	pop eax	290	pop eax
291	mov dl,0xf8	291	mov dl,0xf8
292	out dx,eax	292	out dx,eax
293		293
294	xor eax,eax	294	xor eax,eax
295	pop esi	295	pop esi
296		296
297	ret	297	ret
298	pci_write_reg_2:	298	pci_write_reg_2:
299		299
300	test bh,128 ;mech#2 only supports 16 devices per bus	300	test bh,128 ;mech#2 only supports 16 devices per bus
301	jnz pci_write_reg_err	301	jnz pci_write_reg_err
302		302
303		303
304	push esi ; save register size into ESI	304	push esi ; save register size into ESI
305	mov esi,eax	305	mov esi,eax
306	and esi,3	306	and esi,3
307		307
308	push eax	308	push eax
309	;store current state of config space	309	;store current state of config space
310	mov dx,0xcf8	310	mov dx,0xcf8
311	in al,dx	311	in al,dx
312	mov ah,al	312	mov ah,al
313	mov dl,0xfa	313	mov dl,0xfa
314	in al,dx	314	in al,dx
315	xchg eax,[esp]	315	xchg eax,[esp]
316	; out 0xcfa,bus	316	; out 0xcfa,bus
317	mov al,ah	317	mov al,ah
318	out dx,al	318	out dx,al
319	; out 0xcf8,0x80	319	; out 0xcf8,0x80
320	mov dl,0xf8	320	mov dl,0xf8
321	mov al,0x80	321	mov al,0x80
322	out dx,al	322	out dx,al
323	; compute addr	323	; compute addr
324	shr bh,3 ; func is ignored in mechanism 2	324	shr bh,3 ; func is ignored in mechanism 2
325	or bh,0xc0	325	or bh,0xc0
326	mov dx,bx	326	mov dx,bx
327	; write register	327	; write register
328	mov eax,ecx	328	mov eax,ecx
329		329
330	or esi,esi	330	or esi,esi
331	jz pci_write_byte2	331	jz pci_write_byte2
332	cmp esi,1	332	cmp esi,1
333	jz pci_write_word2	333	jz pci_write_word2
334	cmp esi,2	334	cmp esi,2
335	jz pci_write_dword2	335	jz pci_write_dword2
336	jmp pci_fin_write2	336	jmp pci_fin_write2
337		337
338	pci_write_byte2:	338	pci_write_byte2:
339	out dx,al	339	out dx,al
340	jmp pci_fin_write2	340	jmp pci_fin_write2
341	pci_write_word2:	341	pci_write_word2:
342	out dx,ax	342	out dx,ax
343	jmp pci_fin_write2	343	jmp pci_fin_write2
344	pci_write_dword2:	344	pci_write_dword2:
345	out dx,eax	345	out dx,eax
346	jmp pci_fin_write2	346	jmp pci_fin_write2
347	pci_fin_write2:	347	pci_fin_write2:
348	; restore configuration space	348	; restore configuration space
349	pop eax	349	pop eax
350	mov dx,0xcfa	350	mov dx,0xcfa
351	out dx,al	351	out dx,al
352	mov dl,0xf8	352	mov dl,0xf8
353	mov al,ah	353	mov al,ah
354	out dx,al	354	out dx,al
355		355
356	xor eax,eax	356	xor eax,eax
357	pop esi	357	pop esi
358	ret	358	ret
359		359
360	pci_write_reg_err:	360	pci_write_reg_err:
361	xor eax,eax	361	xor eax,eax
362	dec eax	362	dec eax
363	ret	363	ret

Subversion Repositories Kolibri OS

(root)/kernel/trunk/bus/pci/pci32.inc – Rev 431 → 465