WebSVN – Kolibri OS – Diff – /kernel/branches/net/drivers/pcnet32.asm

 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;                                                                  ;;
-;; Copyright (C) KolibriOS team 2004-2007. All rights reserved.     ;;
+;; Copyright (C) KolibriOS team 2004-2010. All rights reserved.     ;;
 ;; Distributed under terms of the GNU General Public License        ;;
 ;;                                                                  ;;
+;;  PCnet32 driver for KolibriOS                                    ;;
+;;                                                                  ;;
+;;  Based on the PCnet32 driver for MenuetOS, by Jarek Pelczar      ;;
+;;                                                                  ;;
 ;;          GNU GENERAL PUBLIC LICENSE                              ;;
 ;;             Version 2, June 1991                                 ;;
 ;;                                                                  ;;
-;; Status: under construction                                       ;;
-;;                                                                  ;;
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; $Revision: 1514 $
 format MS COFF
+	API_VERSION		equ 0x01000100
+	DRIVER_VERSION		equ 5
-	API_VERSION		equ 0x01000100
+	MAX_DEVICES		equ 16
-	DEBUG			equ 1
-	__DEBUG__		equ 1
-	__DEBUG_LEVEL__ 	equ 1
+	DEBUG			equ 1
 	__DEBUG__		equ 1
-MAX_PCNET equ 4
+	__DEBUG_LEVEL__ 	equ 1
 MAX_ETH_FRAME_SIZE equ 1514
-include 'proc32.inc'
-include 'imports.inc'
-include 'fdo.inc'
-include 'netdrv.inc'
 include 'proc32.inc'
-OS_BASE 	equ 0
+include 'imports.inc'
 end virtual
-; PCI Bus defines
-	PCI_HEADER_TYPE 	      equ 0x0e	;8 bit
-	PCI_BASE_ADDRESS_0	      equ 0x10	;32 bit
-	PCI_BASE_ADDRESS_5	      equ 0x24	;32 bits
-	PCI_BASE_ADDRESS_SPACE_IO     equ 0x01
-	PCI_VENDOR_ID		      equ 0x00	;16 bit
-	PCI_BASE_ADDRESS_IO_MASK      equ 0xFFFFFFFC
+; PCI Bus defines
-	PCNET_PORT_AUI		      equ 0x00
+	PORT_AUI		equ 0x00
-	PCNET_PORT_10BT 	      equ 0x01
+	PORT_10BT		equ 0x01
-	PCNET_PORT_GPSI 	      equ 0x02
+	PORT_GPSI		equ 0x02
-	PCNET_PORT_MII		      equ 0x03
+	PORT_MII		equ 0x03
-	PCNET_PORT_PORTSEL	      equ 0x03
+	PORT_PORTSEL		equ 0x03
-	PCNET_PORT_ASEL 	      equ 0x04
+	PORT_ASEL		equ 0x04
-	PCNET_PORT_100		      equ 0x40
+	PORT_100		equ 0x40
-	PCNET_PORT_FD		      equ 0x80
+	PORT_FD 		equ 0x80
-	PCNET_DMA_MASK		      equ 0xffffffff
+	DMA_MASK		equ 0xffffffff
-	PCNET_LOG_TX_BUFFERS	      equ 2
+	LOG_TX_BUFFERS		equ 2
-	PCNET_LOG_RX_BUFFERS	      equ 2
+	LOG_RX_BUFFERS		equ 2
-	PCNET_TX_RING_SIZE	      equ 4
+	TX_RING_SIZE		equ 4
-	PCNET_TX_RING_MOD_MASK	      equ (PCNET_TX_RING_SIZE-1)
+	TX_RING_MOD_MASK	equ (TX_RING_SIZE-1)
-	PCNET_TX_RING_LEN_BITS	      equ (PCNET_LOG_TX_BUFFERS shl 12)
+	TX_RING_LEN_BITS	equ (LOG_TX_BUFFERS shl 12)
-	PCNET_RX_RING_SIZE	      equ 4
+	RX_RING_SIZE		equ 4
-	PCNET_RX_RING_MOD_MASK	      equ (PCNET_RX_RING_SIZE-1)
+	RX_RING_MOD_MASK	equ (RX_RING_SIZE-1)
-	PCNET_RX_RING_LEN_BITS	      equ (PCNET_LOG_RX_BUFFERS shl 4)
+	RX_RING_LEN_BITS	equ (LOG_RX_BUFFERS shl 4)
-	PCNET_PKT_BUF_SZ	      equ 1544
+	PKT_BUF_SZ		equ 1544
-	PCNET_PKT_BUF_SZ_NEG	      equ 0xf9f8
+	PKT_BUF_SZ_NEG		equ 0xf9f8
-	PCNET_WIO_RDP		      equ 0x10
+	WIO_RDP 		equ 0x10
-	PCNET_WIO_RAP		      equ 0x12
+	WIO_RAP 		equ 0x12
-	PCNET_WIO_RESET 	      equ 0x14
+	WIO_RESET		equ 0x14
-	PCNET_WIO_BDP		      equ 0x16
+	WIO_BDP 		equ 0x16
-	PCNET_DWIO_RDP		      equ 0x10
+	DWIO_RDP		equ 0x10
-	PCNET_DWIO_RAP		      equ 0x14
+	DWIO_RAP		equ 0x14
-	PCNET_DWIO_RESET	      equ 0x18
+	DWIO_RESET		equ 0x18
-	PCNET_DWIO_BDP		      equ 0x1C
+	DWIO_BDP		equ 0x1C
-	PCNET_TOTAL_SIZE	      equ 0x20
+	TOTAL_SIZE		equ 0x20
 ; CSR registers
-	PCNET_CSR_CSR		      equ 0x00
+	CSR_CSR 		equ 0x00
-	PCNET_CSR_IAB0		      equ 0x01
+	CSR_IAB0		equ 0x01
-	PCNET_CSR_IAB1		      equ 0x02
+	CSR_IAB1		equ 0x02
-	PCNET_CSR_IMR		      equ 0x03
+	CSR_IMR 		equ 0x03
-	PCNET_CSR_TFEAT 	      equ 0x04
+	CSR_TFEAT		equ 0x04
-	PCNET_CSR_EXTCTL1	      equ 0x05
+	CSR_EXTCTL1		equ 0x05
-	PCNET_CSR_DTBLLEN	      equ 0x06
+	CSR_DTBLLEN		equ 0x06
-	PCNET_CSR_EXTCTL2	      equ 0x07
+	CSR_EXTCTL2		equ 0x07
-	PCNET_CSR_MAR0		      equ 0x08
+	CSR_MAR0		equ 0x08
-	PCNET_CSR_MAR1		      equ 0x09
+	CSR_MAR1		equ 0x09
-	PCNET_CSR_MAR2		      equ 0x0A
+	CSR_MAR2		equ 0x0A
-	PCNET_CSR_MAR3		      equ 0x0B
+	CSR_MAR3		equ 0x0B
-	PCNET_CSR_PAR0		      equ 0x0C
+	CSR_PAR0		equ 0x0C
-	PCNET_CSR_PAR1		      equ 0x0D
+	CSR_PAR1		equ 0x0D
-	PCNET_CSR_PAR2		      equ 0x0E
+	CSR_PAR2		equ 0x0E
-	PCNET_CSR_MODE		      equ 0x0F
+	CSR_MODE		equ 0x0F
-	PCNET_CSR_RXADDR0	      equ 0x18
+	CSR_RXADDR0		equ 0x18
-	PCNET_CSR_RXADDR1	      equ 0x19
+	CSR_RXADDR1		equ 0x19
-	PCNET_CSR_TXADDR0	      equ 0x1E
+	CSR_TXADDR0		equ 0x1E
-	PCNET_CSR_TXADDR1	      equ 0x1F
+	CSR_TXADDR1		equ 0x1F
-	PCNET_CSR_TXPOLL	      equ 0x2F
+	CSR_TXPOLL		equ 0x2F
-	PCNET_CSR_RXPOLL	      equ 0x31
+	CSR_RXPOLL		equ 0x31
-	PCNET_CSR_RXRINGLEN	      equ 0x4C
+	CSR_RXRINGLEN		equ 0x4C
-	PCNET_CSR_TXRINGLEN	      equ 0x4E
+	CSR_TXRINGLEN		equ 0x4E
-	PCNET_CSR_DMACTL	      equ 0x50
+	CSR_DMACTL		equ 0x50
-	PCNET_CSR_BUSTIMER	      equ 0x52
+	CSR_BUSTIMER		equ 0x52
-	PCNET_CSR_MEMERRTIMEO	      equ 0x64
+	CSR_MEMERRTIMEO 	equ 0x64
-	PCNET_CSR_ONNOWMISC	      equ 0x74
+	CSR_ONNOWMISC		equ 0x74
-	PCNET_CSR_ADVFEAT	      equ 0x7A
+	CSR_ADVFEAT		equ 0x7A
-	PCNET_CSR_MACCFG	      equ 0x7D
+	CSR_MACCFG		equ 0x7D
-	PCNET_CSR_CHIPID0	      equ 0x58
+	CSR_CHIPID0		equ 0x58
-	PCNET_CSR_CHIPID1	      equ 0x59
+	CSR_CHIPID1		equ 0x59
 ; Control and Status Register (CSR0)
-	PCNET_CSR_INIT		      equ 1 shl 0
+	CSR_INIT		equ 1 shl 0
-	PCNET_CSR_START 	      equ 1 shl 1
+	CSR_START		equ 1 shl 1
-	PCNET_CSR_STOP		      equ 1 shl 2
+	CSR_STOP		equ 1 shl 2
-	PCNET_CSR_TX		      equ 1 shl 3
+	CSR_TX			equ 1 shl 3
-	PCNET_CSR_TXON		      equ 1 shl 4
+	CSR_TXON		equ 1 shl 4
-	PCNET_CSR_RXON		      equ 1 shl 5
+	CSR_RXON		equ 1 shl 5
-	PCNET_CSR_INTEN 	      equ 1 shl 6
+	CSR_INTEN		equ 1 shl 6
-	PCNET_CSR_INTR		      equ 1 shl 7
+	CSR_INTR		equ 1 shl 7
-	PCNET_CSR_IDONE 	      equ 1 shl 8
+	CSR_IDONE		equ 1 shl 8
-	PCNET_CSR_TINT		      equ 1 shl 9
+	CSR_TINT		equ 1 shl 9
-	PCNET_CSR_RINT		      equ 1 shl 10
+	CSR_RINT		equ 1 shl 10
-	PCNET_CSR_MERR		      equ 1 shl 11
+	CSR_MERR		equ 1 shl 11
-	PCNET_CSR_MISS		      equ 1 shl 12
+	CSR_MISS		equ 1 shl 12
-	PCNET_CSR_CERR		      equ 1 shl 13
+	CSR_CERR		equ 1 shl 13
 ; Interrupt masks and deferral control (CSR3)
-	PCNET_IMR_BSWAP 	      equ 0x0004
+	IMR_BSWAP		equ 0x0004
-	PCNET_IMR_ENMBA 	      equ 0x0008  ; enable modified backoff alg
+	IMR_ENMBA		equ 0x0008  ; enable modified backoff alg
-	PCNET_IMR_DXMT2PD	      equ 0x0010
+	IMR_DXMT2PD		equ 0x0010
-	PCNET_IMR_LAPPEN	      equ 0x0020  ; lookahead packet processing enb
+	IMR_LAPPEN		equ 0x0020  ; lookahead packet processing enb
-	PCNET_IMR_DXSUFLO	      equ 0x0040  ; disable TX stop on underflow
+	IMR_DXSUFLO		equ 0x0040  ; disable TX stop on underflow
-	PCNET_IMR_IDONE 	      equ 0x0100
+	IMR_IDONE		equ 0x0100
-	PCNET_IMR_TINT		      equ 0x0200
+	IMR_TINT		equ 0x0200
-	PCNET_IMR_RINT		      equ 0x0400
+	IMR_RINT		equ 0x0400
-	PCNET_IMR_MERR		      equ 0x0800
+	IMR_MERR		equ 0x0800
-	PCNET_IMR_MISS		      equ 0x1000
+	IMR_MISS		equ 0x1000
-	PCNET_IMR		      equ PCNET_IMR_TINT+PCNET_IMR_RINT+PCNET_IMR_IDONE+PCNET_IMR_MERR+PCNET_IMR_MISS
+	IMR			equ IMR_TINT+IMR_RINT+IMR_IDONE+IMR_MERR+IMR_MISS
 ; Test and features control (CSR4)
-	PCNET_TFEAT_TXSTRTMASK	      equ 0x0004
+	TFEAT_TXSTRTMASK	equ 0x0004
-	PCNET_TFEAT_TXSTRT	      equ 0x0008
+	TFEAT_TXSTRT		equ 0x0008
-	PCNET_TFEAT_RXCCOFLOWM	      equ 0x0010  ; Rx collision counter oflow
+	TFEAT_RXCCOFLOWM	equ 0x0010  ; Rx collision counter oflow
-	PCNET_TFEAT_RXCCOFLOW	      equ 0x0020
+	TFEAT_RXCCOFLOW 	equ 0x0020
-	PCNET_TFEAT_UINT	      equ 0x0040
+	TFEAT_UINT		equ 0x0040
-	PCNET_TFEAT_UINTREQ	      equ 0x0080
+	TFEAT_UINTREQ		equ 0x0080
-	PCNET_TFEAT_MISSOFLOWM	      equ 0x0100
+	TFEAT_MISSOFLOWM	equ 0x0100
-	PCNET_TFEAT_MISSOFLOW	      equ 0x0200
+	TFEAT_MISSOFLOW 	equ 0x0200
-	PCNET_TFEAT_STRIP_FCS	      equ 0x0400
+	TFEAT_STRIP_FCS 	equ 0x0400
-	PCNET_TFEAT_PAD_TX	      equ 0x0800
+	TFEAT_PAD_TX		equ 0x0800
-	PCNET_TFEAT_TXDPOLL	      equ 0x1000
+	TFEAT_TXDPOLL		equ 0x1000
-	PCNET_TFEAT_DMAPLUS	      equ 0x4000
+	TFEAT_DMAPLUS		equ 0x4000
 ; Extended control and interrupt 1 (CSR5)
-	PCNET_EXTCTL1_SPND	      equ 0x0001  ; suspend
+	EXTCTL1_SPND		equ 0x0001  ; suspend
-	PCNET_EXTCTL1_MPMODE	      equ 0x0002  ; magic packet mode
+	EXTCTL1_MPMODE		equ 0x0002  ; magic packet mode
-	PCNET_EXTCTL1_MPENB	      equ 0x0004  ; magic packet enable
+	EXTCTL1_MPENB		equ 0x0004  ; magic packet enable
-	PCNET_EXTCTL1_MPINTEN	      equ 0x0008  ; magic packet interrupt enable
+	EXTCTL1_MPINTEN 	equ 0x0008  ; magic packet interrupt enable
-	PCNET_EXTCTL1_MPINT	      equ 0x0010  ; magic packet interrupt
+	EXTCTL1_MPINT		equ 0x0010  ; magic packet interrupt
-	PCNET_EXTCTL1_MPPLBA	      equ 0x0020  ; magic packet phys. logical bcast
+	EXTCTL1_MPPLBA		equ 0x0020  ; magic packet phys. logical bcast
-	PCNET_EXTCTL1_EXDEFEN	      equ 0x0040  ; excessive deferral interrupt enb.
+	EXTCTL1_EXDEFEN 	equ 0x0040  ; excessive deferral interrupt enb.
-	PCNET_EXTCTL1_EXDEF	      equ 0x0080  ; excessive deferral interrupt
+	EXTCTL1_EXDEF		equ 0x0080  ; excessive deferral interrupt
-	PCNET_EXTCTL1_SINTEN	      equ 0x0400  ; system interrupt enable
+	EXTCTL1_SINTEN		equ 0x0400  ; system interrupt enable
-	PCNET_EXTCTL1_SINT	      equ 0x0800  ; system interrupt
+	EXTCTL1_SINT		equ 0x0800  ; system interrupt
-	PCNET_EXTCTL1_LTINTEN	      equ 0x4000  ; last TX interrupt enb
+	EXTCTL1_LTINTEN 	equ 0x4000  ; last TX interrupt enb
-	PCNET_EXTCTL1_TXOKINTD	      equ 0x8000  ; TX OK interrupt disable
+	EXTCTL1_TXOKINTD	equ 0x8000  ; TX OK interrupt disable
 ; RX/TX descriptor len (CSR6)
-	PCNET_DTBLLEN_RLEN	      equ 0x0F00
+	DTBLLEN_RLEN		equ 0x0F00
-	PCNET_DTBLLEN_TLEN	      equ 0xF000
+	DTBLLEN_TLEN		equ 0xF000
 ; Extended control and interrupt 2 (CSR7)
-	PCNET_EXTCTL2_MIIPDTINTE      equ 0x0001
+	EXTCTL2_MIIPDTINTE	equ 0x0001
-	PCNET_EXTCTL2_MIIPDTINT       equ 0x0002
+	EXTCTL2_MIIPDTINT	equ 0x0002
-	PCNET_EXTCTL2_MCCIINTE	      equ 0x0004
+	EXTCTL2_MCCIINTE	equ 0x0004
-	PCNET_EXTCTL2_MCCIINT	      equ 0x0008
+	EXTCTL2_MCCIINT 	equ 0x0008
-	PCNET_EXTCTL2_MCCINTE	      equ 0x0010
+	EXTCTL2_MCCINTE 	equ 0x0010
-	PCNET_EXTCTL2_MCCINT	      equ 0x0020
+	EXTCTL2_MCCINT		equ 0x0020
-	PCNET_EXTCTL2_MAPINTE	      equ 0x0040
+	EXTCTL2_MAPINTE 	equ 0x0040
-	PCNET_EXTCTL2_MAPINT	      equ 0x0080
+	EXTCTL2_MAPINT		equ 0x0080
-	PCNET_EXTCTL2_MREINTE	      equ 0x0100
+	EXTCTL2_MREINTE 	equ 0x0100
-	PCNET_EXTCTL2_MREINT	      equ 0x0200
+	EXTCTL2_MREINT		equ 0x0200
-	PCNET_EXTCTL2_STINTE	      equ 0x0400
+	EXTCTL2_STINTE		equ 0x0400
-	PCNET_EXTCTL2_STINT	      equ 0x0800
+	EXTCTL2_STINT		equ 0x0800
-	PCNET_EXTCTL2_RXDPOLL	      equ 0x1000
+	EXTCTL2_RXDPOLL 	equ 0x1000
-	PCNET_EXTCTL2_RDMD	      equ 0x2000
+	EXTCTL2_RDMD		equ 0x2000
-	PCNET_EXTCTL2_RXFRTG	      equ 0x4000
+	EXTCTL2_RXFRTG		equ 0x4000
-	PCNET_EXTCTL2_FASTSPNDE       equ 0x8000
+	EXTCTL2_FASTSPNDE	equ 0x8000
 ; Mode (CSR15)
-	PCNET_MODE_RXD		      equ 0x0001  ; RX disable
+	MODE_RXD		equ 0x0001  ; RX disable
-	PCNET_MODE_TXD		      equ 0x0002  ; TX disable
+	MODE_TXD		equ 0x0002  ; TX disable
-	PCNET_MODE_LOOP 	      equ 0x0004  ; loopback enable
+	MODE_LOOP		equ 0x0004  ; loopback enable
-	PCNET_MODE_TXCRCD	      equ 0x0008
+	MODE_TXCRCD		equ 0x0008
-	PCNET_MODE_FORCECOLL	      equ 0x0010
+	MODE_FORCECOLL		equ 0x0010
-	PCNET_MODE_RETRYD	      equ 0x0020
+	MODE_RETRYD		equ 0x0020
-	PCNET_MODE_INTLOOP	      equ 0x0040
+	MODE_INTLOOP		equ 0x0040
-	PCNET_MODE_PORTSEL	      equ 0x0180
+	MODE_PORTSEL		equ 0x0180
-	PCNET_MODE_RXVPAD	      equ 0x2000
+	MODE_RXVPAD		equ 0x2000
-	PCNET_MODE_RXNOBROAD	      equ 0x4000
+	MODE_RXNOBROAD		equ 0x4000
-	PCNET_MODE_PROMISC	      equ 0x8000
+	MODE_PROMISC		equ 0x8000
 ; BCR (Bus Control Registers)
-	PCNET_BCR_MMRA		      equ 0x00	  ; Master Mode Read Active
+	BCR_MMRA		equ 0x00    ; Master Mode Read Active
-	PCNET_BCR_MMW		      equ 0x01	  ; Master Mode Write Active
+	BCR_MMW 		equ 0x01    ; Master Mode Write Active
-	PCNET_BCR_MISCCFG	      equ 0x02
+	BCR_MISCCFG		equ 0x02
-	PCNET_BCR_LED0		      equ 0x04
+	BCR_LED0		equ 0x04
-	PCNET_BCR_LED1		      equ 0x05
+	BCR_LED1		equ 0x05
-	PCNET_BCR_LED2		      equ 0x06
+	BCR_LED2		equ 0x06
-	PCNET_BCR_LED3		      equ 0x07
+	BCR_LED3		equ 0x07
-	PCNET_BCR_DUPLEX	      equ 0x09
+	BCR_DUPLEX		equ 0x09
-	PCNET_BCR_BUSCTL	      equ 0x12
+	BCR_BUSCTL		equ 0x12
-	PCNET_BCR_EECTL 	      equ 0x13
+	BCR_EECTL		equ 0x13
-	PCNET_BCR_SSTYLE	      equ 0x14
+	BCR_SSTYLE		equ 0x14
-	PCNET_BCR_PCILAT	      equ 0x16
+	BCR_PCILAT		equ 0x16
-	PCNET_BCR_PCISUBVENID	      equ 0x17
+	BCR_PCISUBVENID 	equ 0x17
-	PCNET_BCR_PCISUBSYSID	      equ 0x18
+	BCR_PCISUBSYSID 	equ 0x18
-	PCNET_BCR_SRAMSIZE	      equ 0x19
+	BCR_SRAMSIZE		equ 0x19
-	PCNET_BCR_SRAMBOUND	      equ 0x1A
+	BCR_SRAMBOUND		equ 0x1A
-	PCNET_BCR_SRAMCTL	      equ 0x1B
+	BCR_SRAMCTL		equ 0x1B
-	PCNET_BCR_MIICTL	      equ 0x20
+	BCR_MIICTL		equ 0x20
-	PCNET_BCR_MIIADDR	      equ 0x21
+	BCR_MIIADDR		equ 0x21
-	PCNET_BCR_MIIDATA	      equ 0x22
+	BCR_MIIDATA		equ 0x22
-	PCNET_BCR_PCIVENID	      equ 0x23
+	BCR_PCIVENID		equ 0x23
-	PCNET_BCR_PCIPCAP	      equ 0x24
+	BCR_PCIPCAP		equ 0x24
-	PCNET_BCR_DATA0 	      equ 0x25
+	BCR_DATA0		equ 0x25
-	PCNET_BCR_DATA1 	      equ 0x26
+	BCR_DATA1		equ 0x26
-	PCNET_BCR_DATA2 	      equ 0x27
+	BCR_DATA2		equ 0x27
-	PCNET_BCR_DATA3 	      equ 0x28
+	BCR_DATA3		equ 0x28
-	PCNET_BCR_DATA4 	      equ 0x29
+	BCR_DATA4		equ 0x29
-	PCNET_BCR_DATA5 	      equ 0x2A
+	BCR_DATA5		equ 0x2A
-	PCNET_BCR_DATA6 	      equ 0x2B
+	BCR_DATA6		equ 0x2B
-	PCNET_BCR_DATA7 	      equ 0x2C
+	BCR_DATA7		equ 0x2C
-	PCNET_BCR_ONNOWPAT0	      equ 0x2D
+	BCR_ONNOWPAT0		equ 0x2D
-	PCNET_BCR_ONNOWPAT1	      equ 0x2E
+	BCR_ONNOWPAT1		equ 0x2E
-	PCNET_BCR_ONNOWPAT2	      equ 0x2F
+	BCR_ONNOWPAT2		equ 0x2F
-	PCNET_BCR_PHYSEL	      equ 0x31
+	BCR_PHYSEL		equ 0x31
 ; RX status register
-	PCNET_RXSTAT_BPE	      equ 0x0080  ; bus parity error
+	RXSTAT_BPE		equ 0x0080  ; bus parity error
-	PCNET_RXSTAT_ENP	      equ 0x0100  ; end of packet
+	RXSTAT_ENP		equ 0x0100  ; end of packet
-	PCNET_RXSTAT_STP	      equ 0x0200  ; start of packet
+	RXSTAT_STP		equ 0x0200  ; start of packet
-	PCNET_RXSTAT_BUFF	      equ 0x0400  ; buffer error
+	RXSTAT_BUFF		equ 0x0400  ; buffer error
-	PCNET_RXSTAT_CRC	      equ 0x0800  ; CRC error
+	RXSTAT_CRC		equ 0x0800  ; CRC error
-	PCNET_RXSTAT_OFLOW	      equ 0x1000  ; rx overrun
+	RXSTAT_OFLOW		equ 0x1000  ; rx overrun
-	PCNET_RXSTAT_FRAM	      equ 0x2000  ; framing error
+	RXSTAT_FRAM		equ 0x2000  ; framing error
-	PCNET_RXSTAT_ERR	      equ 0x4000  ; error summary
+	RXSTAT_ERR		equ 0x4000  ; error summary
 	cmp	byte [eax], 1				; 1 means device number and bus number (pci) are given
 	jne	.fail					; other types arent supported for this card yet
 ; check if the device is already listed
-	mov	ecx, [PCNET_DEV]
+	mov	ecx, [devices]
 	test	ecx, ecx
 	jz	.firstdevice
-	mov	esi, PCNET_LIST
+	mov	esi, device_list
 ;        mov     eax, [IOCTL.input]                      ; get the pci bus and device numbers
 	mov	ax , [eax+1]				;
 	loop	.nextdevice
 ; This device doesnt have its own eth_device structure yet, lets create one
   .firstdevice:
-	cmp	[PCNET_DEV], MAX_PCNET			; First check if the driver can handle one more card
+	cmp	[devices], MAX_DEVICES			; First check if the driver can handle one more card
 	jge	.fail
 	find_irq [device.pci_bus], [device.pci_dev], [device.irq_line]
 	DEBUGF	1,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\
 	[device.pci_dev]:1,[device.pci_bus]:1,[device.irq_line]:1,[device.io_addr]:4
-	allocate_and_clear [device.tx_buffer], (PCNET_RX_RING_SIZE * PCNET_PKT_BUF_SZ), .err
+;;;        allocate_and_clear [device.tx_buffer], (RX_RING_SIZE * PKT_BUF_SZ), .err
-	allocate_and_clear [device.rx_buffer], (PCNET_TX_RING_SIZE * PCNET_PKT_BUF_SZ), .err
+	allocate_and_clear [device.rx_buffer], (TX_RING_SIZE * PKT_BUF_SZ), .err
-	allocate_and_clear [device.rx_ring], (PCNET_RX_RING_SIZE * buf_head.size), .err
+	allocate_and_clear [device.rx_ring], (RX_RING_SIZE * buf_head.size), .err
 	mov	eax, [device.rx_ring]
 	call	GetPgAddr
 	mov	[device.rx_ring_phys], eax
-	allocate_and_clear [device.tx_ring], (PCNET_TX_RING_SIZE * buf_head.size), .err
+	allocate_and_clear [device.tx_ring], (TX_RING_SIZE * buf_head.size), .err
 	mov	eax, [device.tx_ring]
 	call	GetPgAddr
 	mov	[device.tx_ring_phys], eax
 ; Ok, the eth_device structure is ready, let's probe the device
 ; Because initialization fires IRQ, IRQ handler must be aware of this device
 ; If an error occured, remove all allocated data and exit (returning -1 in eax)
   .destroy:
 	; todo: reset device into virgin state
-	dec	[PCNET_DEV]
+	dec	[devices]
   .err:
 	DEBUGF	1,"Error, removing all data !\n"
 	stdcall KernelFree, [device.rx_buffer]
-	stdcall KernelFree, [device.tx_buffer]
+;;;        stdcall KernelFree, [device.tx_buffer]
 	stdcall KernelFree, ebx
 	make_bus_master [device.pci_bus], [device.pci_dev]
 ; first, fill in some of the structure variables
 	mov	edi, [device.rx_ring]
-	mov	ecx, PCNET_RX_RING_SIZE
+	mov	ecx, RX_RING_SIZE
 	mov	eax, [device.rx_buffer]
 	call	GetPgAddr
   .rx_init:
 	mov	[edi + buf_head.base], eax
-	mov	[edi + buf_head.length], PCNET_PKT_BUF_SZ_NEG
+	mov	[edi + buf_head.length], PKT_BUF_SZ_NEG
 	mov	[edi + buf_head.status], 0x8000
 	and	dword [edi + buf_head.msg_length], 0
 	and	dword [edi + buf_head.reserved], 0
-	add	eax, PCNET_PKT_BUF_SZ
+	add	eax, PKT_BUF_SZ
 ;        inc     eax
 	add	 edi, buf_head.size
 	loop	 .rx_init
 	mov	edi, [device.tx_ring]
-	mov	ecx, PCNET_TX_RING_SIZE
+	mov	ecx, TX_RING_SIZE
 	mov	eax, [device.tx_buffer]
 	call	GetPgAddr
   .tx_init:
 	mov	[edi + buf_head.base], eax
 	and	dword [edi + buf_head.length], 0
 	and	dword [edi + buf_head.msg_length], 0
 	and	dword [edi + buf_head.reserved], 0
-	add	eax, PCNET_PKT_BUF_SZ
+	add	eax, PKT_BUF_SZ
 	add	edi, buf_head.size
 	loop	.tx_init
-	mov	[device.tlen_rlen], (PCNET_TX_RING_LEN_BITS or PCNET_RX_RING_LEN_BITS)
+	mov	[device.tlen_rlen], (TX_RING_LEN_BITS or RX_RING_LEN_BITS)
 	cmp	eax, 4
 	jne	.try_dwio
 	; Try Word I/O
 	mov	ax , 88
-	add	edx, PCNET_WIO_RAP
+	add	edx, WIO_RAP
 	out	dx , ax
 	nop
 	nop
 	in	ax , dx
-	sub	edx, PCNET_WIO_RAP
+	sub	edx, WIO_RAP
 	cmp	ax , 88
 	jne	.try_dwio
 	call	dwio_read_csr
 	cmp	eax, 4
 	jne	.no_dev
 	; Try Dword I/O
-	set_io	PCNET_DWIO_RAP
+	set_io	DWIO_RAP
 	mov	eax, 88
 	out	dx , eax
 	nop
 	nop
 	DEBUGF 1,"PCnet device not found!\n"
 	mov	eax, 1
 	ret
   .L1:
-	mov	ecx, PCNET_CSR_CHIPID0
+	mov	ecx, CSR_CHIPID0
 	call	[device.access_read_csr]
 	mov	esi, eax
-	mov	ecx, PCNET_CSR_CHIPID1
+	mov	ecx, CSR_CHIPID1
 	call	[device.access_read_csr]
 	shl	eax, 16
 	mov	[device.mii], 1
 	jmp	.L10
   .L8:
 	mov	[device.name], device_l8
 ;        mov     [device.fdx], 1
-	mov	ecx, PCNET_CSR_RXPOLL
+	mov	ecx, CSR_RXPOLL
 	call	[device.access_read_bcr]
 	call	[device.access_write_bcr]
 	jmp	.L10
   .L9:
 	mov	[device.name], device_l9
   .L10:
 	DEBUGF 1,"device name: %s\n",[device.name]
 	cmp	[device.fset], 1
 	jne	.L11
-	mov	ecx, PCNET_BCR_BUSCTL
+	mov	ecx, BCR_BUSCTL
 	call	[device.access_read_bcr]
 	or	eax, 0x800
 	call	[device.access_write_bcr]
-	mov	ecx, PCNET_CSR_DMACTL
+	mov	ecx, CSR_DMACTL
 	call	[device.access_read_csr]
 ;        and     eax, 0xc00
 ;        or      eax, 0xc00
 	mov	[device.dxsuflo],1
 	mov	[device.ltint],1
   .L11:
 	DEBUGF 1,"PCI done\n"
-	mov	eax, PCNET_PORT_ASEL
+	mov	eax, PORT_ASEL
 	mov	[device.options], eax
 	mov	[device.mode_], word 0x0003
-	mov	[device.tlen_rlen], word (PCNET_TX_RING_LEN_BITS or PCNET_RX_RING_LEN_BITS)
+	mov	[device.tlen_rlen], word (TX_RING_LEN_BITS or RX_RING_LEN_BITS)
 	mov	dword [device.filter], 0
 	mov	dword [device.filter+4], 0
 ; Switch to dword operations
 	DEBUGF 1,"Switching to 32-bit mode\n"
-	mov	ecx, PCNET_DWIO_RDP
+	mov	ecx, DWIO_RDP
 	mov	eax, 0
 	call	wio_write_csr
 	call	switch_to_dwio
 ; Lets find out if we are really in 32-bit mode now..
 	set_io	0
 	call	[device.access_reset]
   .yes_dwio:
 	; set/reset autoselect bit
-	mov	ecx, PCNET_BCR_MISCCFG
+	mov	ecx, BCR_MISCCFG
 	call	[device.access_read_bcr]
 	and	eax,not 2
-	test	[device.options], PCNET_PORT_ASEL
+	test	[device.options], PORT_ASEL
 	jz	.L1
 	or	eax, 2
   .L1:
 	call	[device.access_write_bcr]
 	; Handle full duplex setting
 	cmp	byte [device.full_duplex], 0
 	je	.L2
-	mov	ecx, PCNET_BCR_DUPLEX
+	mov	ecx, BCR_DUPLEX
 	call	[device.access_read_bcr]
 	and	eax, not 3
-	test	[device.options], PCNET_PORT_FD
+	test	[device.options], PORT_FD
 	jz	.L3
 	or	eax, 1
-	cmp	[device.options], PCNET_PORT_FD or PCNET_PORT_AUI
+	cmp	[device.options], PORT_FD or PORT_AUI
 	jne	.L4
 	or	eax, 2
 	jmp	.L4
   .L3:
-	test	[device.options], PCNET_PORT_ASEL
+	test	[device.options], PORT_ASEL
 	jz	.L4
 	cmp	[device.chip_version], 0x2627
 	jne	.L4
 	or	eax, 3
   .L4:
-	mov	ecx, PCNET_BCR_DUPLEX
+	mov	ecx, BCR_DUPLEX
 	call	[device.access_write_bcr]
   .L2:
 	; set/reset GPSI bit in test register
 	mov	ecx, 124
 	call	[device.access_read_csr]
 	mov	ecx, [device.options]
-	and	ecx, PCNET_PORT_PORTSEL
+	and	ecx, PORT_PORTSEL
-	cmp	ecx, PCNET_PORT_GPSI
+	cmp	ecx, PORT_GPSI
 	jne	.L5
 	or	eax, 0x10
   .L5:
 	call	[device.access_write_csr]
 	cmp	[device.mii], 0
 	je	.L6
-	test	[device.options], PCNET_PORT_ASEL
+	test	[device.options], PORT_ASEL
 	jnz	.L6
-	mov	ecx, PCNET_BCR_MIICTL
+	mov	ecx, BCR_MIICTL
 	call	[device.access_read_bcr]
 	and	eax,not 0x38
-	test	[device.options], PCNET_PORT_FD
+	test	[device.options], PORT_FD
 	jz	.L7
 	or	eax, 0x10
   .L7:
-	test	[device.options], PCNET_PORT_100
+	test	[device.options], PORT_100
 	jz	.L8
 	or	eax, 0x08
   .L8:
 	call	[device.access_write_bcr]
 	jmp	.L9
 .L6:
-	test	[device.options], PCNET_PORT_ASEL
+	test	[device.options], PORT_ASEL
 	jz	.L9
 	call	[device.access_read_csr]
 	or	eax,(1 shl 14)
 	call	[device.access_write_csr]
 .L10:
 	mov	eax, [device.options]
-	and	eax, PCNET_PORT_PORTSEL
+	and	eax, PORT_PORTSEL
 	shl	eax, 7
 	mov	[device.mode_], ax
 	mov	dword [device.filter], -1
 	mov	dword [device.filter+4], -1
 	xor	ecx, ecx
 	call	[device.access_read_csr]
 	xor	ecx, ecx
-	mov	eax, PCNET_CSR_INTEN or PCNET_CSR_START
+	mov	eax, CSR_INTEN or CSR_START
 	call	[device.access_write_csr]
 	DEBUGF 1,"PCNET reset complete\n"
 	xor	eax, eax
 ; clear packet/byte counters
+	lea	edi, [device.bytes_tx]
+	mov	ecx, 6
+	rep	stosd
 	lea	edi, [device.bytes_tx]
 	cmp	dword [esp+8], 60
 	jl	.finish 			; packet is too short
 ; check descriptor
 	movzx	eax, [device.cur_tx]
-	imul	edi, eax, PCNET_PKT_BUF_SZ
+	imul	edi, eax, PKT_BUF_SZ
 	shl	eax, 4
 	add	edi, [device.tx_buffer]
 	add	eax, [device.tx_ring]
 	test	byte [eax + buf_head.status + 1], 80h
+	jnz	.nospace
 	jnz	.nospace
 ; descriptor is free, copy data
 	mov	esi, [esp+4]
 	mov	ecx, [esp+8]
 	mov	edx, ecx
 	shr	ecx, 2
 	and	edx, 3
 	rep	movsd
 	mov	ecx, edx
+	rep	movsb
 	rep	movsb
 ; set length
 	mov	ecx, [esp+8]
 	neg	ecx
 	mov	[eax + buf_head.length], cx
 ; put to transfer queue
 	mov	[eax + buf_head.status], 0x8300
 ; trigger an immediate send
 	xor	ecx, ecx	 ; CSR0
 	call	[device.access_read_csr]
-	or	eax, PCNET_CSR_TX
+	or	eax, CSR_TX
 	call	[device.access_write_csr]
 	mov	ecx, [esp+8]
 	add	dword [device.bytes_tx], ecx
 	adc	dword [device.bytes_tx + 4], 0
+	DEBUGF	2," - Done!\n"
+	call	Kernelfree
-	DEBUGF	2," - Done!\n"
+	add	esp, 4
 	ret
 .nospace:
+	DEBUGF	1, 'ERROR: no free transmit descriptors\n'
+; todo: maybe somehow notify the kernel about the error?
-	DEBUGF	1, 'ERROR: no free transmit descriptors\n'
+	call	Kernelfree
-; todo: maybe somehow notify the kernel about the error?
+	add	esp, 4
 	DEBUGF	1,"IRQ %x ", eax:2		; no, you cant replace 'eax:2' with 'al', this must be a bug in FDO
 ; find pointer of device wich made IRQ occur
-	mov	esi, PCNET_LIST
+	mov	esi, device_list
-	mov	ecx, [PCNET_DEV]
+	mov	ecx, [devices]
 	test	ecx, ecx
 	jz	.abort
 ; to two or more reasons in one IRQ.
 	xor	ecx, ecx
 	call	[device.access_write_csr]
 ; Received packet ok?
-	test	ax, PCNET_CSR_RINT
+	test	ax, CSR_RINT
 	jz	@f
 .receiver_test_loop:
 	movzx	eax, [device.cur_rx]
-;        and     eax, PCNET_RX_RING_MOD_MASK
+;        and     eax, RX_RING_MOD_MASK
 	mov	edi, eax
-	imul	esi, eax, PCNET_PKT_BUF_SZ	;
+	imul	esi, eax, PKT_BUF_SZ	  ;
 	add	esi, [device.rx_buffer] 	; esi now points to rx buffer
 	shl	edi, 4				; desc * 16 (16 is size of one ring entry)
 	add	edi, [device.rx_ring]		; edi now points to current rx ring entry
 	mov	cx , [edi + buf_head.status]
-	test	cx , PCNET_RXSTAT_OWN		; If this bit is set, the controller OWN's the packet, if not, we do
+	test	cx , RXSTAT_OWN 	  ; If this bit is set, the controller OWN's the packet, if not, we do
 	jnz	.abort
 	jnc	.nw
 	movsw
   .nw:
 	rep	movsd
-;       mov     word [eax + buf_head.length], PCNET_PKT_BUF_SZ_NEG
+;       mov     word [eax + buf_head.length], PKT_BUF_SZ_NEG
-	mov	word [eax + buf_head.status], PCNET_RXSTAT_OWN	    ; Set OWN bit back to 1 (controller may write to tx-buffer again now)
+	mov	word [eax + buf_head.status], RXSTAT_OWN      ; Set OWN bit back to 1 (controller may write to tx-buffer again now)
 	inc	[device.cur_rx] 	  ; update descriptor
 	mov	edx, [device.io_addr]
 	add	edx, 2
 	xor	eax, eax
-	mov	ecx, PCNET_CSR_PAR0
+	mov	ecx, CSR_PAR0
        @@:
 	pop	ax
 	call	[device.access_write_csr]
 	DEBUGF	1,"."
 	inc	ecx
-	cmp	ecx, PCNET_CSR_PAR2
+	cmp	ecx, CSR_PAR2
 	jl	@r
 ; ecx - index
 ; return:
 ; eax - data
 wio_read_csr:
-	add	edx, PCNET_WIO_RAP
+	add	edx, WIO_RAP
 	mov	ax , cx
 	out	dx , ax
-	add	edx, PCNET_WIO_RDP - PCNET_WIO_RAP
+	add	edx, WIO_RDP - WIO_RAP
 	in	ax , dx
 	and	eax, 0xffff
-	sub	edx, PCNET_WIO_RDP
+	sub	edx, WIO_RDP
 	ret
 ; eax - data
 ; ecx - index
 wio_write_csr:
-	add	edx, PCNET_WIO_RAP
+	add	edx, WIO_RAP
 	xchg	eax, ecx
 	out	dx , ax
 	xchg	eax, ecx
-	add	edx, PCNET_WIO_RDP - PCNET_WIO_RAP
+	add	edx, WIO_RDP - WIO_RAP
 	out	dx , ax
-	sub	edx, PCNET_WIO_RDP
+	sub	edx, WIO_RDP
 	ret
 ; ecx - index
 ; return:
 ; eax - data
 wio_read_bcr:
-	add	edx, PCNET_WIO_RAP
+	add	edx, WIO_RAP
 	mov	ax , cx
 	out	dx , ax
-	add	edx, PCNET_WIO_BDP - PCNET_WIO_RAP
+	add	edx, WIO_BDP - WIO_RAP
 	in	ax , dx
 	and	eax, 0xffff
-	sub	edx, PCNET_WIO_BDP
+	sub	edx, WIO_BDP
 	ret
 ; eax - data
 ; ecx - index
 wio_write_bcr:
-	add	edx, PCNET_WIO_RAP
+	add	edx, WIO_RAP
 	xchg	eax, ecx
 	out	dx , ax
 	xchg	eax, ecx
-	add	edx, PCNET_WIO_BDP - PCNET_WIO_RAP
+	add	edx, WIO_BDP - WIO_RAP
 	out	dx , ax
-	sub	edx, PCNET_WIO_BDP
+	sub	edx, WIO_BDP
 	ret
 wio_read_rap:
-	add	edx, PCNET_WIO_RAP
+	add	edx, WIO_RAP
 	in	ax , dx
 	and	eax, 0xffff
-	sub	edx, PCNET_WIO_RAP
+	sub	edx, WIO_RAP
 	ret
 ; eax - val
 wio_write_rap:
-	add	edx, PCNET_WIO_RAP
+	add	edx, WIO_RAP
 	out	dx , ax
-	sub	edx, PCNET_WIO_RAP
+	sub	edx, WIO_RAP
 	ret
 wio_reset:
 	push	eax
-	add	edx, PCNET_WIO_RESET
+	add	edx, WIO_RESET
 	in	ax , dx
 	pop	eax
-	sub	edx, PCNET_WIO_RESET
+	sub	edx, WIO_RESET
 	ret
 ; ecx - index
 ; return:
 ; eax - data
 dwio_read_csr:
-	add	edx, PCNET_DWIO_RAP
+	add	edx, DWIO_RAP
 	mov	eax, ecx
 	out	dx , eax
-	add	edx, PCNET_DWIO_RDP - PCNET_DWIO_RAP
+	add	edx, DWIO_RDP - DWIO_RAP
 	in	eax, dx
 	and	eax, 0xffff
-	sub	edx, PCNET_DWIO_RDP
+	sub	edx, DWIO_RDP
 	ret
 ; ecx - index
 ; eax - data
 dwio_write_csr:
-	add	edx, PCNET_DWIO_RAP
+	add	edx, DWIO_RAP
 	xchg	eax, ecx
 	out	dx , eax
-	add	edx, PCNET_DWIO_RDP - PCNET_DWIO_RAP
+	add	edx, DWIO_RDP - DWIO_RAP
 	xchg	eax, ecx
 	out	dx , eax
-	sub	edx, PCNET_DWIO_RDP
+	sub	edx, DWIO_RDP
 	ret
 ; ecx - index
 ; return:
 ; eax - data
 dwio_read_bcr:
-	add	edx, PCNET_DWIO_RAP
+	add	edx, DWIO_RAP
 	mov	eax, ecx
 	out	dx , eax
-	add	edx, PCNET_DWIO_BDP - PCNET_DWIO_RAP
+	add	edx, DWIO_BDP - DWIO_RAP
 	in	eax, dx
-	and	eax, 0xffff
-	sub	edx, PCNET_DWIO_BDP
+	and	eax, 0xffff
+	sub	edx, DWIO_BDP
-	ret
+	ret
 ; ecx - index
-; eax - data
+; ecx - index
-dwio_write_bcr:
+; eax - data
 dwio_write_bcr:
 	add	edx, PCNET_DWIO_RAP
-	xchg	eax, ecx
+	add	edx, DWIO_RAP
-	out	dx , eax
+	xchg	eax, ecx
-	add	edx, PCNET_DWIO_BDP - PCNET_DWIO_RAP
+	out	dx , eax
-	xchg	eax, ecx
+	add	edx, DWIO_BDP - DWIO_RAP
-	out	dx , eax
+	xchg	eax, ecx
-	sub	edx, PCNET_DWIO_BDP
+	out	dx , eax
+	sub	edx, DWIO_BDP
-	ret
+	ret
-dwio_read_rap:
+dwio_read_rap:
-	add	edx, PCNET_DWIO_RAP
-	in	eax, dx
+	add	edx, DWIO_RAP
-	and	eax, 0xffff
+	in	eax, dx
-	sub	edx, PCNET_DWIO_RAP
+	and	eax, 0xffff
+	sub	edx, DWIO_RAP
-	ret
 	ret
-; eax - val

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(root)/kernel/branches/net/drivers/pcnet32.asm – Rev 1514 → 1519