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| Rev 3155 | Rev 3201 | ||
|---|---|---|---|
| Line 21... | Line 21... | ||
| 21 | API_VERSION = 0x01000100 |
21 | API_VERSION = 0x01000100 |
| 22 | DRIVER_VERSION = 5 |
22 | DRIVER_VERSION = 5 |
| Line 23... | Line 23... | ||
| 23 | 23 | ||
| Line -... | Line 24... | ||
| - | 24 | MAX_DEVICES = 16 |
|
| - | 25 | ||
| - | 26 | RX_DES_COUNT = 4 ; no of RX descriptors, must be power of 2 |
|
| - | 27 | RX_BUFF_SIZE = 2048 ; size of buffer for each descriptor, must be multiple of 4 and <= 2048 TDES1_TBS1_MASK |
|
| - | 28 | ||
| - | 29 | TX_DES_COUNT = 4 ; no of TX descriptors, must be power of 2 |
|
| - | 30 | TX_BUFF_SIZE = 2048 ; size of buffer for each descriptor, used for memory allocation only |
|
| 24 | MAX_DEVICES = 16 |
31 | |
| 25 | 32 | ||
| 26 | DEBUG = 1 |
33 | DEBUG = 1 |
| Line 27... | Line 34... | ||
| 27 | __DEBUG__ = 1 |
34 | __DEBUG__ = 1 |
| Line 81... | Line 88... | ||
| 81 | CSR15 = 0x78 ; Watchdog timer |
88 | CSR15 = 0x78 ; Watchdog timer |
| Line 82... | Line 89... | ||
| 82 | 89 | ||
| 83 | ;--------bits/commands of CSR0------------------- |
90 | ;--------bits/commands of CSR0------------------- |
| Line 84... | Line 91... | ||
| 84 | CSR0_RESET = 1b |
91 | CSR0_RESET = 1b |
| 85 | 92 | ||
| 86 | CSR0_WIE = 1 SHL 24 ; Write and Invalidate Enable |
93 | CSR0_WIE = 1 shl 24 ; Write and Invalidate Enable |
| 87 | CSR0_RLE = 1 SHL 23 ; PCI Read Line Enable |
94 | CSR0_RLE = 1 shl 23 ; PCI Read Line Enable |
| 88 | CSR0_RML = 1 SHL 21 ; PCI Read Multiple |
95 | CSR0_RML = 1 shl 21 ; PCI Read Multiple |
| 89 | 96 | ||
| 90 | CSR0_CACHEALIGN_NONE = 00b SHL 14 |
97 | CSR0_CACHEALIGN_NONE = 00b shl 14 |
| 91 | CSR0_CACHEALIGN_32 = 01b SHL 14 |
98 | CSR0_CACHEALIGN_32 = 01b shl 14 |
| Line 92... | Line 99... | ||
| 92 | CSR0_CACHEALIGN_64 = 10b SHL 14 |
99 | CSR0_CACHEALIGN_64 = 10b shl 14 |
| 93 | CSR0_CACHEALIGN_128 = 11b SHL 14 |
100 | CSR0_CACHEALIGN_128 = 11b shl 14 |
| Line 94... | Line 101... | ||
| 94 | 101 | ||
| 95 | ; using values from linux driver.. :P |
102 | ; using values from linux driver.. |
| 96 | CSR0_DEFAULT = CSR0_WIE+CSR0_RLE+CSR0_RML+CSR0_CACHEALIGN_NONE ;32 |
103 | CSR0_DEFAULT = CSR0_WIE + CSR0_RLE + CSR0_RML + CSR0_CACHEALIGN_NONE |
| 97 | 104 | ||
| 98 | ;------- CSR5 -STATUS- bits -------------------------------- |
105 | ;------- CSR5 -STATUS- bits -------------------------------- |
| 99 | CSR5_TI = 1 SHL 0 ; Transmit interupt - frame transmition completed |
106 | CSR5_TI = 1 shl 0 ; Transmit interupt - frame transmition completed |
| 100 | CSR5_TPS = 1 SHL 1 ; Transmit process stopped |
107 | CSR5_TPS = 1 shl 1 ; Transmit process stopped |
| 101 | CSR5_TU = 1 SHL 2 ; Transmit Buffer unavailable |
108 | CSR5_TU = 1 shl 2 ; Transmit Buffer unavailable |
| 102 | CSR5_TJT = 1 SHL 3 ; Transmit Jabber Timeout (transmitter had been excessively active) |
109 | CSR5_TJT = 1 shl 3 ; Transmit Jabber Timeout (transmitter had been excessively active) |
| 103 | CSR5_UNF = 1 SHL 5 ; Transmit underflow - FIFO underflow |
110 | CSR5_UNF = 1 shl 5 ; Transmit underflow - FIFO underflow |
| 104 | CSR5_RI = 1 SHL 6 ; Receive Interrupt |
111 | CSR5_RI = 1 shl 6 ; Receive Interrupt |
| 105 | CSR5_RU = 1 SHL 7 ; Receive Buffer unavailable |
112 | CSR5_RU = 1 shl 7 ; Receive Buffer unavailable |
| 106 | CSR5_RPS = 1 SHL 8 ; Receive Process stopped |
113 | CSR5_RPS = 1 shl 8 ; Receive Process stopped |
| 107 | CSR5_RWT = 1 SHL 9 ; Receive Watchdow Timeout |
114 | CSR5_RWT = 1 shl 9 ; Receive Watchdow Timeout |
| 108 | CSR5_ETI = 1 SHL 10 ; Early transmit Interrupt |
115 | CSR5_ETI = 1 shl 10 ; Early transmit Interrupt |
| 109 | CSR5_GTE = 1 SHL 11 ; General Purpose Timer Expired |
116 | CSR5_GTE = 1 shl 11 ; General Purpose Timer Expired |
| 110 | CSR5_FBE = 1 SHL 13 ; Fatal bus error |
117 | CSR5_FBE = 1 shl 13 ; Fatal bus error |
| 111 | CSR5_ERI = 1 SHL 14 ; Early receive Interrupt |
118 | CSR5_ERI = 1 shl 14 ; Early receive Interrupt |
| 112 | CSR5_AIS = 1 SHL 15 ; Abnormal interrupt summary |
119 | CSR5_AIS = 1 shl 15 ; Abnormal interrupt summary |
| 113 | CSR5_NIS = 1 SHL 16 ; normal interrupt summary |
120 | CSR5_NIS = 1 shl 16 ; normal interrupt summary |
| 114 | CSR5_RS_SH = 1 SHL 17 ; Receive process state -shift |
121 | CSR5_RS_SH = 17 ; Receive process state -shift |
| 115 | CSR5_RS_MASK = 111b ; -mask |
122 | CSR5_RS_MASK = 111b ; -mask |
| Line 116... | Line 123... | ||
| 116 | CSR5_TS_SH = 1 SHL 20 ; Transmit process state -shift |
123 | CSR5_TS_SH = 20 ; Transmit process state -shift |
| 117 | CSR5_TS_MASK = 111b ; -mask |
124 | CSR5_TS_MASK = 111b ; -mask |
| 118 | CSR5_EB_SH = 1 SHL 23 ; Error bits -shift |
125 | CSR5_EB_SH = 23 ; Error bits -shift |
| Line 126... | Line 133... | ||
| 126 | CSR5_TS_RUNNING_SETUP_PCKT = 101b |
133 | CSR5_TS_RUNNING_SETUP_PCKT = 101b |
| 127 | CSR5_TS_SUSPENDED = 110b |
134 | CSR5_TS_SUSPENDED = 110b |
| 128 | CSR5_TS_RUNNING_CLOSING_DESC = 111b |
135 | CSR5_TS_RUNNING_CLOSING_DESC = 111b |
| Line 129... | Line 136... | ||
| 129 | 136 | ||
| 130 | ;------- CSR6 -OPERATION MODE- bits -------------------------------- |
137 | ;------- CSR6 -OPERATION MODE- bits -------------------------------- |
| 131 | CSR6_HP = 1 SHL 0 ; Hash/Perfect Receive Filtering mode |
138 | CSR6_HP = 1 shl 0 ; Hash/Perfect Receive Filtering mode |
| 132 | CSR6_SR = 1 SHL 1 ; Start/Stop receive |
139 | CSR6_SR = 1 shl 1 ; Start/Stop receive |
| 133 | CSR6_HO = 1 SHL 2 ; Hash only Filtering mode |
140 | CSR6_HO = 1 shl 2 ; Hash only Filtering mode |
| 134 | CSR6_PB = 1 SHL 3 ; Pass bad frames |
141 | CSR6_PB = 1 shl 3 ; Pass bad frames |
| 135 | CSR6_IF = 1 SHL 4 ; Inverse filtering |
142 | CSR6_IF = 1 shl 4 ; Inverse filtering |
| 136 | CSR6_SB = 1 SHL 5 ; Start/Stop backoff counter |
143 | CSR6_SB = 1 shl 5 ; Start/Stop backoff counter |
| 137 | CSR6_PR = 1 SHL 6 ; Promiscuos mode -default after reset |
144 | CSR6_PR = 1 shl 6 ; Promiscuos mode -default after reset |
| 138 | CSR6_PM = 1 SHL 7 ; Pass all multicast |
145 | CSR6_PM = 1 shl 7 ; Pass all multicast |
| 139 | CSR6_F = 1 SHL 9 ; Full Duplex mode |
146 | CSR6_F = 1 shl 9 ; Full Duplex mode |
| 140 | CSR6_OM_SH = 1 SHL 10 ; Operating Mode -shift |
147 | CSR6_OM_SH = 10 ; Operating Mode -shift |
| 141 | CSR6_OM_MASK = 11b ; -mask |
148 | CSR6_OM_MASK = 11b ; -mask |
| 142 | CSR6_FC = 1 SHL 12 ; Force Collision Mode |
149 | CSR6_FC = 1 shl 12 ; Force Collision Mode |
| 143 | CSR6_ST = 1 SHL 13 ; Start/Stop Transmission Command |
150 | CSR6_ST = 1 shl 13 ; Start/Stop Transmission Command |
| 144 | CSR6_TR_SH = 1 SHL 14 ; Threshold Control -shift |
151 | CSR6_TR_SH = 14 ; Threshold Control -shift |
| 145 | CSR6_TR_MASK = 11b ; -mask |
152 | CSR6_TR_MASK = 11b ; -mask |
| 146 | CSR6_CA = 1 SHL 17 ; Capture Effect Enable |
153 | CSR6_CA = 1 shl 17 ; Capture Effect Enable |
| 147 | CSR6_PS = 1 SHL 18 ; Port select SRL / MII/SYM |
154 | CSR6_PS = 1 shl 18 ; Port select SRL / MII/SYM |
| 148 | CSR6_HBD = 1 SHL 19 ; Heartbeat Disable |
155 | CSR6_HBD = 1 shl 19 ; Heartbeat Disable |
| 149 | CSR6_SF = 1 SHL 21 ; Store and Forward -transmit full packet only |
156 | CSR6_SF = 1 shl 21 ; Store and Forward -transmit full packet only |
| 150 | CSR6_TTM = 1 SHL 22 ; Transmit Threshold Mode - |
157 | CSR6_TTM = 1 shl 22 ; Transmit Threshold Mode - |
| 151 | CSR6_PCS = 1 SHL 23 ; PCS active and MII/SYM port operates in symbol mode |
158 | CSR6_PCS = 1 shl 23 ; PCS active and MII/SYM port operates in symbol mode |
| 152 | CSR6_SCR = 1 SHL 24 ; Scrambler Mode |
159 | CSR6_SCR = 1 shl 24 ; Scrambler Mode |
| 153 | CSR6_MBO = 1 SHL 25 ; Must Be One |
160 | CSR6_MBO = 1 shl 25 ; Must Be One |
| 154 | CSR6_RA = 1 SHL 30 ; Receive All |
161 | CSR6_RA = 1 shl 30 ; Receive All |
| Line 155... | Line 162... | ||
| 155 | CSR6_SC = 1 SHL 31 ; Special Capture Effect Enable |
162 | CSR6_SC = 1 shl 31 ; Special Capture Effect Enable |
| 156 | 163 | ||
| 157 | 164 | ||
| 158 | ;------- CSR7 -INTERRUPT ENABLE- bits -------------------------------- |
165 | ;------- CSR7 -INTERRUPT ENABLE- bits -------------------------------- |
| 159 | CSR7_TI = 1 SHL 0 ; transmit Interrupt Enable (set with CSR7<16> & CSR5<0> ) |
166 | CSR7_TI = 1 shl 0 ; transmit Interrupt Enable (set with CSR7<16> & CSR5<0> ) |
| 160 | CSR7_TS = 1 SHL 1 ; transmit Stopped Enable (set with CSR7<15> & CSR5<1> ) |
167 | CSR7_TS = 1 shl 1 ; transmit Stopped Enable (set with CSR7<15> & CSR5<1> ) |
| 161 | CSR7_TU = 1 SHL 2 ; transmit buffer underrun Enable (set with CSR7<16> & CSR5<2> ) |
168 | CSR7_TU = 1 shl 2 ; transmit buffer underrun Enable (set with CSR7<16> & CSR5<2> ) |
| 162 | CSR7_TJ = 1 SHL 3 ; transmit jabber timeout enable (set with CSR7<15> & CSR5<3> ) |
169 | CSR7_TJ = 1 shl 3 ; transmit jabber timeout enable (set with CSR7<15> & CSR5<3> ) |
| 163 | CSR7_UN = 1 SHL 5 ; underflow Interrupt enable (set with CSR7<15> & CSR5<5> ) |
170 | CSR7_UN = 1 shl 5 ; underflow Interrupt enable (set with CSR7<15> & CSR5<5> ) |
| 164 | CSR7_RI = 1 SHL 6 ; receive Interrupt enable (set with CSR7<16> & CSR5<5> ) |
171 | CSR7_RI = 1 shl 6 ; receive Interrupt enable (set with CSR7<16> & CSR5<5> ) |
| 165 | CSR7_RU = 1 SHL 7 ; receive buffer unavailable enable (set with CSR7<15> & CSR5<7> ) |
172 | CSR7_RU = 1 shl 7 ; receive buffer unavailable enable (set with CSR7<15> & CSR5<7> ) |
| 166 | CSR7_RS = 1 SHL 8 ; Receive stopped enable (set with CSR7<15> & CSR5<8> ) |
173 | CSR7_RS = 1 shl 8 ; Receive stopped enable (set with CSR7<15> & CSR5<8> ) |
| 167 | CSR7_RW = 1 SHL 9 ; receive watchdog timeout enable (set with CSR7<15> & CSR5<9> ) |
174 | CSR7_RW = 1 shl 9 ; receive watchdog timeout enable (set with CSR7<15> & CSR5<9> ) |
| 168 | CSR7_ETE = 1 SHL 10 ; Early transmit Interrupt enable (set with CSR7<15> & CSR5<10> ) |
175 | CSR7_ETE = 1 shl 10 ; Early transmit Interrupt enable (set with CSR7<15> & CSR5<10> ) |
| 169 | CSR7_GPT = 1 SHL 11 ; general purpose timer enable (set with CSR7<15> & CSR5<11> ) |
176 | CSR7_GPT = 1 shl 11 ; general purpose timer enable (set with CSR7<15> & CSR5<11> ) |
| 170 | CSR7_FBE = 1 SHL 13 ; Fatal bus error enable (set with CSR7<15> & CSR5<13> ) |
177 | CSR7_FBE = 1 shl 13 ; Fatal bus error enable (set with CSR7<15> & CSR5<13> ) |
| - | 178 | CSR7_ERE = 1 shl 14 ; Early receive enable (set with CSR7<16> & CSR5<14> ) |
|
| 171 | CSR7_ERE = 1 SHL 14 ; Early receive enable (set with CSR7<16> & CSR5<14> ) |
179 | CSR7_AI = 1 shl 15 ; Abnormal Interrupt Summary Enable (enables CSR5<0,3,7,8,9,10,13>) |
| 172 | CSR7_AI = 1 SHL 15 ; Abnormal Interrupt Summary Enable (enables CSR5<0,3,7,8,9,10,13>) |
180 | CSR7_NI = 1 shl 16 ; Normal Interrup Enable (enables CSR5<0,2,6,11,14>) |
| Line 173... | Line 181... | ||
| 173 | CSR7_NI = 1 SHL 16 ; Normal Interrup Enable (enables CSR5<0,2,6,11,14>) |
181 | |
| 174 | CSR7_DEFAULT = CSR7_TI+CSR7_TS+CSR7_RI+CSR7_RS+CSR7_TU+CSR7_TJ+CSR7_UN+\ |
182 | CSR7_DEFAULT = CSR7_TI + CSR7_TS + CSR7_RI + CSR7_RS + CSR7_TU + CSR7_TJ + CSR7_UN + \ |
| 175 | CSR7_RU+CSR7_RW+CSR7_FBE+CSR7_AI+CSR7_NI |
183 | CSR7_RU + CSR7_RW + CSR7_FBE + CSR7_AI + CSR7_NI |
| 176 | 184 | ||
| 177 | ;----------- descriptor structure --------------------- |
185 | ;----------- descriptor structure --------------------- |
| 178 | struc DES { |
186 | struc DES { |
| 179 | .DES0 DD ? ; bit 31 is 'own' and rest is 'status' |
187 | .status dd ? ; bit 31 is 'own' and rest is 'status' |
| 180 | .DES1 DD ? ; control bits + bytes-count buffer 1 + bytes-count buffer 2 |
188 | .length dd ? ; control bits + bytes-count buffer 1 + bytes-count buffer 2 |
| 181 | .DES2 DD ? ; pointer to buffer1 |
189 | .buffer1 dd ? ; pointer to buffer1 |
| Line 182... | Line 190... | ||
| 182 | .DES3 DD ? ; pointer to buffer2 or in this case to next descriptor, as we use a chained structure |
190 | .buffer2 dd ? ; pointer to buffer2 or in this case to next descriptor, as we use a chained structure |
| 183 | .realaddr dd ? |
191 | .virtaddr dd ? |
| 184 | .size = 64 |
192 | .size = 64 ; 64, for alignment purposes |
| Line 185... | Line 193... | ||
| 185 | } |
193 | } |
| 186 | 194 | ||
| Line 187... | Line 195... | ||
| 187 | virtual at 0 |
195 | virtual at 0 |
| 188 | DES DES |
196 | DES DES |
| 189 | end virtual |
197 | end virtual |
| 190 | 198 | ||
| 191 | ;common to Rx and Tx |
199 | ;common to Rx and Tx |
| 192 | DES0_OWN = 1 SHL 31 ; if set, the NIC controls the descriptor, otherwise driver 'owns' the descriptors |
200 | DES0_OWN = 1 shl 31 ; if set, the NIC controls the descriptor, otherwise driver 'owns' the descriptors |
| 193 | 201 | ||
| 194 | ;receive |
202 | ;receive |
| 195 | RDES0_ZER = 1 SHL 0 ; must be 0 if legal length :D |
203 | RDES0_ZER = 1 shl 0 ; must be 0 if legal length :D |
| 196 | RDES0_CE = 1 SHL 1 ; CRC error, valid only on last desc (RDES0<8>=1) |
204 | RDES0_CE = 1 shl 1 ; CRC error, valid only on last desc (RDES0<8>=1) |
| 197 | RDES0_DB = 1 SHL 2 ; dribbling bit - not multiple of 8 bits, valid only on last desc (RDES0<8>=1) |
205 | RDES0_DB = 1 shl 2 ; dribbling bit - not multiple of 8 bits, valid only on last desc (RDES0<8>=1) |
| 198 | RDES0_RE = 1 SHL 3 ; Report on MII error.. i dont realy know what this means :P |
206 | RDES0_RE = 1 shl 3 ; Report on MII error.. i dont realy know what this means :P |
| 199 | RDES0_RW = 1 SHL 4 ; received watchdog timer expiration - must set CSR5<9>, valid only on last desc (RDES0<8>=1) |
207 | RDES0_RW = 1 shl 4 ; received watchdog timer expiration - must set CSR5<9>, valid only on last desc (RDES0<8>=1) |
| 200 | RDES0_FT = 1 SHL 5 ; frame type: 0->IEEE802.0 (len<1500) 1-> ETHERNET frame (len>1500), valid only on last desc (RDES0<8>=1) |
208 | RDES0_FT = 1 shl 5 ; frame type: 0->IEEE802.0 (len<1500) 1-> ETHERNET frame (len>1500), valid only on last desc (RDES0<8>=1) |
| 201 | RDES0_CS = 1 SHL 6 ; Collision seen, valid only on last desc (RDES0<8>=1) |
209 | RDES0_CS = 1 shl 6 ; Collision seen, valid only on last desc (RDES0<8>=1) |
| 202 | RDES0_TL = 1 SHL 7 ; Too long(>1518)-NOT AN ERROR, valid only on last desc (RDES0<8>=1) |
210 | RDES0_TL = 1 shl 7 ; Too long(>1518)-NOT AN ERROR, valid only on last desc (RDES0<8>=1) |
| 203 | RDES0_LS = 1 SHL 8 ; Last descriptor of current frame |
211 | RDES0_LS = 1 shl 8 ; Last descriptor of current frame |
| 204 | RDES0_FS = 1 SHL 9 ; First descriptor of current frame |
212 | RDES0_FS = 1 shl 9 ; First descriptor of current frame |
| 205 | RDES0_MF = 1 SHL 10 ; Multicast frame, valid only on last desc (RDES0<8>=1) |
213 | RDES0_MF = 1 shl 10 ; Multicast frame, valid only on last desc (RDES0<8>=1) |
| 206 | RDES0_RF = 1 SHL 11 ; Runt frame, valid only on last desc (RDES0<8>=1) and id overflow |
214 | RDES0_RF = 1 shl 11 ; Runt frame, valid only on last desc (RDES0<8>=1) and id overflow |
| 207 | RDES0_DT_SERIAL = 00b SHL 12 ; Data type-Serial recv frame, valid only on last desc (RDES0<8>=1) |
215 | RDES0_DT_SERIAL = 00b shl 12 ; Data type-Serial recv frame, valid only on last desc (RDES0<8>=1) |
| Line 208... | Line 216... | ||
| 208 | RDES0_DT_INTERNAL = 01b SHL 12 ; Data type-Internal loopback recv frame, valid only on last desc (RDES0<8>=1) |
216 | RDES0_DT_INTERNAL = 01b shl 12 ; Data type-Internal loopback recv frame, valid only on last desc (RDES0<8>=1) |
| 209 | RDES0_DT_EXTERNAL = 11b SHL 12 ; Data type-External loopback recv frame, valid only on last desc (RDES0<8>=1) |
217 | RDES0_DT_EXTERNAL = 11b shl 12 ; Data type-External loopback recv frame, valid only on last desc (RDES0<8>=1) |
| 210 | RDES0_DE = 1 SHL 14 ; Descriptor error - cant own a new desc and frame doesnt fit, valid only on last desc (RDES0<8>=1) |
218 | RDES0_DE = 1 shl 14 ; Descriptor error - cant own a new desc and frame doesnt fit, valid only on last desc (RDES0<8>=1) |
| 211 | RDES0_ES = 1 SHL 15 ; Error Summmary - bits 1+6+11+14, valid only on last desc (RDES0<8>=1) |
219 | RDES0_ES = 1 shl 15 ; Error Summmary - bits 1+6+11+14, valid only on last desc (RDES0<8>=1) |
| 212 | RDES0_FL_SH = 16 ; Field length shift, valid only on last desc (RDES0<8>=1) |
220 | RDES0_FL_SH = 16 ; Field length shift, valid only on last desc (RDES0<8>=1) |
| Line 213... | Line 221... | ||
| 213 | RDES0_FL_MASK = 11111111111111b ; Field length mask (+CRC), valid only on last desc (RDES0<8>=1) |
221 | RDES0_FL_MASK = 11111111111111b ; Field length mask (+CRC), valid only on last desc (RDES0<8>=1) |
| 214 | RDES0_FF = 1 SHL 30 ; Filtering fail-frame failed address recognition test(must CSR6<30>=1), valid only on last desc (RDES0<8>=1) |
222 | RDES0_FF = 1 shl 30 ; Filtering fail-frame failed address recognition test(must CSR6<30>=1), valid only on last desc (RDES0<8>=1) |
| 215 | 223 | ||
| 216 | RDES1_RBS1_MASK = 11111111111b ; firsd buffer size MASK |
224 | RDES1_RBS1_MASK = 11111111111b ; first buffer size MASK |
| 217 | RDES1_RBS2_SH = 1 SHL 11 ; second buffer size SHIFT |
225 | RDES1_RBS2_SH = 11 ; second buffer size SHIFT |
| 218 | RDES1_RBS2_MASK = 11111111111b ; second buffer size MASK |
226 | RDES1_RBS2_MASK = 11111111111b ; second buffer size MASK |
| 219 | RDES1_RCH = 1 SHL 24 ; Second address chained - second address (buffer) is next desc address |
227 | RDES1_RCH = 1 shl 24 ; Second address chained - second address (buffer) is next desc address |
| 220 | RDES1_RER = 1 SHL 25 ; Receive End of Ring - final descriptor, NIC must return to first desc |
228 | RDES1_RER = 1 shl 25 ; Receive End of Ring - final descriptor, NIC must return to first desc |
| 221 | 229 | ||
| 222 | ;transmition |
230 | ;transmition |
| 223 | TDES0_DE = 1 SHL 0 ; Deffered |
231 | TDES0_DE = 1 shl 0 ; Deffered |
| 224 | TDES0_UF = 1 SHL 1 ; Underflow error |
232 | TDES0_UF = 1 shl 1 ; Underflow error |
| 225 | TDES0_LF = 1 SHL 2 ; Link fail report (only if CSR6<23>=1) |
233 | TDES0_LF = 1 shl 2 ; Link fail report (only if CSR6<23>=1) |
| Line 226... | Line 234... | ||
| 226 | TDES0_CC_SH = 3 ; Collision Count shift - no of collision before transmition |
234 | TDES0_CC_SH = 3 ; Collision Count shift - no of collision before transmition |
| 227 | TDES0_CC_MASK = 1111b ; Collision Count mask |
235 | TDES0_CC_MASK = 1111b ; Collision Count mask |
| 228 | TDES0_HF = 1 SHL 7 ; Heartbeat fail |
236 | TDES0_HF = 1 shl 7 ; Heartbeat fail |
| 229 | TDES0_EC = 1 SHL 8 ; Excessive Collisions - >16 collisions |
237 | TDES0_EC = 1 shl 8 ; Excessive Collisions - >16 collisions |
| 230 | TDES0_LC = 1 SHL 9 ; Late collision |
238 | TDES0_LC = 1 shl 9 ; Late collision |
| 231 | TDES0_NC = 1 SHL 10 ; No carrier |
239 | TDES0_NC = 1 shl 10 ; No carrier |
| 232 | TDES0_LO = 1 SHL 11 ; Loss of carrier |
240 | TDES0_LO = 1 shl 11 ; Loss of carrier |
| 233 | TDES0_TO = 1 SHL 14 ; Transmit Jabber Timeout |
241 | TDES0_TO = 1 shl 14 ; Transmit Jabber Timeout |
| 234 | TDES0_ES = 1 SHL 15 ; Error summary TDES0<1+8+9+10+11+14>=1 |
242 | TDES0_ES = 1 shl 15 ; Error summary TDES0<1+8+9+10+11+14>=1 |
| 235 | 243 | ||
| 236 | TDES1_TBS1_MASK = 11111111111b ; Buffer 1 size mask |
244 | TDES1_TBS1_MASK = 11111111111b ; Buffer 1 size mask |
| 237 | TDES1_TBS2_SH = 11 ; Buffer 2 size shift |
245 | TDES1_TBS2_SH = 11 ; Buffer 2 size shift |
| 238 | TDES1_TBS2_MASK = 11111111111b ; Buffer 2 size mask |
246 | TDES1_TBS2_MASK = 11111111111b ; Buffer 2 size mask |
| Line 239... | Line 247... | ||
| 239 | TDES1_FT0 = 1 SHL 22 ; Filtering type 0 |
247 | TDES1_FT0 = 1 shl 22 ; Filtering type 0 |
| Line 240... | Line -... | ||
| 240 | TDES1_DPD = 1 SHL 23 ; Disabled padding for packets <64bytes, no padding |
- | |
| 241 | TDES1_TCH = 1 SHL 24 ; Second address chained - second buffer pointer is to next desc |
- | |
| 242 | TDES1_TER = 1 SHL 25 ; Transmit end of ring - final descriptor |
- | |
| 243 | TDES1_AC = 1 SHL 26 ; Add CRC disable -pretty obvious |
- | |
| 244 | TDES1_SET = 1 SHL 27 ; Setup packet |
- | |
| 245 | TDES1_FT1 = 1 SHL 28 ; Filtering type 1 |
248 | TDES1_DPD = 1 shl 23 ; Disabled padding for packets <64bytes, no padding |
| 246 | TDES1_FS = 1 SHL 29 ; First segment - buffer is first segment of frame |
249 | TDES1_TCH = 1 shl 24 ; Second address chained - second buffer pointer is to next desc |
| Line 247... | Line 250... | ||
| 247 | TDES1_LS = 1 SHL 30 ; Last segment |
250 | TDES1_TER = 1 shl 25 ; Transmit end of ring - final descriptor |
| 248 | TDES1_IC = 1 SHL 31 ; Interupt on completion (CSR5<0>=1) valid when TDES1<30>=1 |
251 | TDES1_AC = 1 shl 26 ; Add CRC disable -pretty obvious |
| 249 | 252 | TDES1_SET = 1 shl 27 ; Setup packet |
|
| 250 | MAX_ETH_FRAME_SIZE = 1514 |
253 | TDES1_FT1 = 1 shl 28 ; Filtering type 1 |
| 251 | 254 | TDES1_FS = 1 shl 29 ; First segment - buffer is first segment of frame |
|
| 252 | RX_DES_COUNT = 4 ; no of RX descriptors, must be power of 2 |
255 | TDES1_LS = 1 shl 30 ; Last segment |
| 253 | RX_BUFF_SIZE = 2048 ; size of buffer for each descriptor, must be multiple of 4 and <= 2048 TDES1_TBS1_MASK |
256 | TDES1_IC = 1 shl 31 ; Interupt on completion (CSR5<0>=1) valid when TDES1<30>=1 |
| 254 | TX_DES_COUNT = 4 ; no of TX descriptors, must be power of 2 |
257 | |
| 255 | TX_BUFF_SIZE = 2048 ; size of buffer for each descriptor, used for memory allocation only |
258 | MAX_ETH_FRAME_SIZE = 1514 |
| Line 256... | Line 259... | ||
| 256 | 259 | ||
| 257 | RX_MEM_TOTAL_SIZE = RX_DES_COUNT*(DES.size+RX_BUFF_SIZE) |
260 | RX_MEM_TOTAL_SIZE = RX_DES_COUNT*(DES.size+RX_BUFF_SIZE) |
| 258 | TX_MEM_TOTAL_SIZE = TX_DES_COUNT*(DES.size+TX_BUFF_SIZE) |
261 | TX_MEM_TOTAL_SIZE = TX_DES_COUNT*(DES.size+TX_BUFF_SIZE) |
| 259 | 262 | ||
| Line 296... | Line 299... | ||
| 296 | out dx , eax |
299 | out dx , eax |
| 297 | } |
300 | } |
| Line 298... | Line 301... | ||
| 298 | 301 | ||
| 299 | macro Bit_Clear a_bit { |
302 | macro Bit_Clear a_bit { |
| 300 | in eax, dx |
303 | in eax, dx |
| 301 | and eax, NOT (a_bit) |
304 | and eax, not (a_bit) |
| 302 | out dx , eax |
305 | out dx, eax |
| Line 303... | Line 306... | ||
| 303 | } |
306 | } |
| Line 525... | Line 528... | ||
| 525 | make_bus_master [device.pci_bus], [device.pci_dev] |
528 | make_bus_master [device.pci_bus], [device.pci_dev] |
| Line 526... | Line 529... | ||
| 526 | 529 | ||
| 527 | movzx eax, [device.pci_bus] |
530 | movzx eax, [device.pci_bus] |
| 528 | movzx ecx, [device.pci_dev] |
531 | movzx ecx, [device.pci_dev] |
| 529 | stdcall PciRead32, eax ,ecx ,0 ; get device/vendor id |
- | |
| 530 | 532 | stdcall PciRead32, eax ,ecx ,0 ; get device/vendor id |
|
| Line 531... | Line 533... | ||
| 531 | DEBUGF 1,"Vendor id: 0x%x\n", ax |
533 | DEBUGF 1,"Vendor id: 0x%x\n", ax |
| 532 | 534 | ||
| 533 | cmp ax, 0x1011 |
535 | cmp ax, 0x1011 |
| 534 | jne .notfound |
- | |
| 535 | shr eax, 16 |
536 | jne .notfound |
| Line 536... | Line 537... | ||
| 536 | 537 | shr eax, 16 |
|
| 537 | DEBUGF 1,"Vendor ok!, device id: 0x%x\n", ax ; TODO: use another method to detect chip! |
538 | DEBUGF 1,"Vendor ok!, device id: 0x%x\n", ax ; TODO: use another method to detect chip! |
| Line 618... | Line 619... | ||
| 618 | @@: |
619 | @@: |
| Line 619... | Line 620... | ||
| 619 | 620 | ||
| 620 | set_io 0 |
621 | set_io 0 |
| Line 621... | Line -... | ||
| 621 | status |
- | |
| 622 | - | ||
| 623 | ;------------------------------------------ |
- | |
| 624 | ; Setup RX descriptors (use chained method) |
- | |
| 625 | - | ||
| 626 | mov eax, [device.rx_p_des] |
- | |
| 627 | call GetPgAddr |
- | |
| 628 | mov edx, eax |
- | |
| 629 | lea esi, [eax + RX_DES_COUNT*(DES.size)] ; jump over RX descriptors |
- | |
| 630 | - | ||
| 631 | mov eax, [device.rx_p_des] |
- | |
| 632 | add eax, RX_DES_COUNT*(DES.size) ; jump over RX descriptors |
- | |
| 633 | - | ||
| 634 | mov edi, [device.rx_p_des] |
- | |
| 635 | mov ecx, RX_DES_COUNT |
- | |
| 636 | - | ||
| 637 | push edx ;; |
- | |
| 638 | .loop_rx_des: |
- | |
| 639 | add edx, DES.size |
- | |
| 640 | mov [edi + DES.DES0], DES0_OWN ; hardware owns buffer |
- | |
| 641 | mov [edi + DES.DES1], 1984 + RDES1_RCH ; only size of first buffer, chained buffers |
- | |
| 642 | mov [edi + DES.DES2], esi ; hw buffer address |
- | |
| 643 | mov [edi + DES.DES3], edx ; pointer to next descriptor |
- | |
| 644 | mov [edi + DES.realaddr], eax ; virtual buffer address |
- | |
| 645 | - | ||
| 646 | DEBUGF 1,"RX desc %u, buff addr: %x, next desc: %x, real buff addr: %x, real descr addr: %x \n", ecx, esi, edx, eax, edi |
- | |
| 647 | - | ||
| 648 | add esi, RX_BUFF_SIZE |
- | |
| 649 | add eax, RX_BUFF_SIZE |
- | |
| 650 | add edi, DES.size |
- | |
| 651 | dec ecx |
- | |
| 652 | jnz .loop_rx_des |
- | |
| 653 | - | ||
| 654 | ; set last descriptor as LAST |
- | |
| 655 | sub edi, DES.size |
- | |
| 656 | or [edi + DES.DES1], RDES1_RER ; EndOfRing |
- | |
| 657 | pop edx |
- | |
| 658 | mov [edi + DES.DES3], edx |
- | |
| 659 | - | ||
| 660 | ;--------------------- |
- | |
| 661 | ; Setup TX descriptors |
- | |
| 662 | 622 | status |
|
| 663 | mov eax, [device.tx_p_des] |
- | |
| 664 | call GetPgAddr |
- | |
| 665 | mov edx, eax |
- | |
| 666 | lea esi, [eax + TX_DES_COUNT*(DES.size)] ; jump over TX descriptors |
- | |
| 667 | - | ||
| 668 | mov eax, [device.tx_p_des] |
- | |
| 669 | add eax, TX_DES_COUNT*(DES.size) ; jump over TX descriptors |
- | |
| 670 | - | ||
| 671 | mov edi, [device.tx_p_des] |
- | |
| 672 | mov ecx, TX_DES_COUNT |
- | |
| 673 | - | ||
| 674 | push edx |
- | |
| 675 | .loop_tx_des: |
- | |
| 676 | add edx, DES.size |
- | |
| 677 | mov [edi + DES.DES0], 0 ; owned by driver |
- | |
| 678 | mov [edi + DES.DES1], TDES1_TCH ; chained method |
- | |
| 679 | mov [edi + DES.DES2], esi ; pointer to buffer |
- | |
| 680 | mov [edi + DES.DES3], edx ; pointer to next descr |
- | |
| 681 | mov [edi + DES.realaddr], eax |
- | |
| 682 | - | ||
| 683 | DEBUGF 1,"TX desc %u, buff addr: %x, next desc: %x, real buff addr: %x, real descr addr: %x \n", ecx, esi, edx, eax, edi |
- | |
| 684 | - | ||
| 685 | add esi, TX_BUFF_SIZE |
- | |
| 686 | add eax, TX_BUFF_SIZE |
- | |
| 687 | add edi, DES.size |
- | |
| 688 | dec ecx |
- | |
| 689 | jnz .loop_tx_des |
- | |
| 690 | - | ||
| 691 | ; set last descriptor as LAST |
- | |
| 692 | sub edi, DES.size |
- | |
| 693 | or [edi + DES.DES1], TDES1_TER ; EndOfRing |
- | |
| 694 | pop edx |
- | |
| 695 | mov [edi + DES.DES3], edx |
- | |
| 696 | - | ||
| 697 | ;------------------ |
- | |
| 698 | ; Reset descriptors |
- | |
| 699 | - | ||
| 700 | mov [device.tx_wr_des], 0 |
- | |
| 701 | mov [device.tx_rd_des], 0 |
- | |
| Line 702... | Line 623... | ||
| 702 | mov [device.rx_crt_des], 0 |
623 | |
| 703 | mov [device.tx_free_des], TX_DES_COUNT |
624 | call init_ring |
| Line 704... | Line 625... | ||
| 704 | 625 | ||
| 705 | ;-------------------------------------------- |
626 | ;-------------------------------------------- |
| 706 | ; setup CSR3 & CSR4 (pointers to descriptors) |
627 | ; setup CSR3 & CSR4 (pointers to descriptors) |
| 707 | 628 | ||
| 708 | set_io 0 |
629 | set_io 0 |
| 709 | status |
630 | status |
| 710 | set_io CSR3 |
631 | set_io CSR3 |
| Line 711... | Line 632... | ||
| 711 | mov eax, [device.rx_p_des] |
632 | mov eax, [device.rx_p_des] |
| 712 | call GetPgAddr |
633 | GetRealAddr |
| 713 | DEBUGF 1,"RX descriptor base address: %x\n", eax |
634 | DEBUGF 1,"RX descriptor base address: %x\n", eax |
| 714 | out dx , eax |
635 | out dx, eax |
| 715 | 636 | ||
| Line 716... | Line 637... | ||
| 716 | set_io CSR4 |
637 | set_io CSR4 |
| 717 | mov eax, [device.tx_p_des] |
638 | mov eax, [device.tx_p_des] |
| Line 742... | Line 663... | ||
| 742 | 663 | ||
| Line 743... | Line 664... | ||
| 743 | status |
664 | status |
| Line 744... | Line -... | ||
| 744 | - | ||
| 745 | call start_link |
665 | |
| 746 | 666 | call start_link |
|
| 747 | 667 | ||
| Line 748... | Line 668... | ||
| 748 | ; wait a bit |
668 | ; wait a bit |
| Line 767... | Line 687... | ||
| 767 | DEBUGF 1,"Reset done\n" |
687 | DEBUGF 1,"Reset done\n" |
| Line 768... | Line 688... | ||
| 768 | 688 | ||
| Line -... | Line 689... | ||
| - | 689 | ret |
|
| - | 690 | ||
| - | 691 | ||
| - | 692 | ||
| - | 693 | align 4 |
|
| - | 694 | init_ring: |
|
| - | 695 | ||
| - | 696 | ;------------------------------------------ |
|
| - | 697 | ; Setup RX descriptors (use chained method) |
|
| - | 698 | ||
| - | 699 | mov eax, [device.rx_p_des] |
|
| - | 700 | GetRealAddr |
|
| - | 701 | mov edx, eax |
|
| - | 702 | push eax |
|
| - | 703 | lea esi, [eax + RX_DES_COUNT*(DES.size)] ; jump over RX descriptors |
|
| - | 704 | mov eax, [device.rx_p_des] |
|
| - | 705 | add eax, RX_DES_COUNT*(DES.size) ; jump over RX descriptors |
|
| - | 706 | mov edi, [device.rx_p_des] |
|
| - | 707 | mov ecx, RX_DES_COUNT |
|
| - | 708 | .loop_rx_des: |
|
| - | 709 | add edx, DES.size |
|
| - | 710 | mov [edi + DES.status], DES0_OWN ; hardware owns buffer |
|
| - | 711 | mov [edi + DES.length], 1984 + RDES1_RCH ; only size of first buffer, chained buffers |
|
| - | 712 | mov [edi + DES.buffer1], esi ; hw buffer address |
|
| - | 713 | mov [edi + DES.buffer2], edx ; pointer to next descriptor |
|
| - | 714 | mov [edi + DES.virtaddr], eax ; virtual buffer address |
|
| - | 715 | DEBUGF 1,"RX desc: buff addr: %x, next desc: %x, real buff addr: %x, real descr addr: %x \n", esi, edx, eax, edi |
|
| - | 716 | ||
| - | 717 | add esi, RX_BUFF_SIZE |
|
| - | 718 | add eax, RX_BUFF_SIZE |
|
| - | 719 | add edi, DES.size |
|
| - | 720 | dec ecx |
|
| - | 721 | jnz .loop_rx_des |
|
| - | 722 | ||
| - | 723 | ; set last descriptor as LAST |
|
| - | 724 | sub edi, DES.size |
|
| - | 725 | or [edi + DES.length], RDES1_RER ; EndOfRing |
|
| - | 726 | pop [edi + DES.buffer2] ; point it to the first descriptor |
|
| - | 727 | ||
| - | 728 | ;--------------------- |
|
| - | 729 | ; Setup TX descriptors |
|
| - | 730 | ||
| - | 731 | mov eax, [device.tx_p_des] |
|
| - | 732 | GetRealAddr |
|
| - | 733 | mov edx, eax |
|
| - | 734 | push eax |
|
| - | 735 | lea esi, [eax + TX_DES_COUNT*(DES.size)] ; jump over TX descriptors |
|
| - | 736 | mov eax, [device.tx_p_des] |
|
| - | 737 | add eax, TX_DES_COUNT*(DES.size) ; jump over TX descriptors |
|
| - | 738 | mov edi, [device.tx_p_des] |
|
| - | 739 | mov ecx, TX_DES_COUNT |
|
| - | 740 | .loop_tx_des: |
|
| - | 741 | add edx, DES.size |
|
| - | 742 | mov [edi + DES.status], 0 ; owned by driver |
|
| - | 743 | mov [edi + DES.length], TDES1_TCH ; chained method |
|
| - | 744 | mov [edi + DES.buffer1], esi ; pointer to buffer |
|
| - | 745 | mov [edi + DES.buffer2], edx ; pointer to next descr |
|
| - | 746 | mov [edi + DES.virtaddr], eax |
|
| - | 747 | DEBUGF 1,"TX desc: buff addr: %x, next desc: %x, virt buff addr: %x, virt descr addr: %x \n", esi, edx, eax, edi |
|
| - | 748 | ||
| - | 749 | add esi, TX_BUFF_SIZE |
|
| - | 750 | add eax, TX_BUFF_SIZE |
|
| - | 751 | add edi, DES.size |
|
| - | 752 | dec ecx |
|
| - | 753 | jnz .loop_tx_des |
|
| - | 754 | ||
| - | 755 | ; set last descriptor as LAST |
|
| - | 756 | sub edi, DES.size |
|
| - | 757 | or [edi + DES.length], TDES1_TER ; EndOfRing |
|
| - | 758 | pop [edi + DES.buffer2] ; point it to the first descriptor |
|
| - | 759 | ||
| - | 760 | ;------------------ |
|
| - | 761 | ; Reset descriptors |
|
| - | 762 | ||
| - | 763 | mov [device.tx_wr_des], 0 |
|
| - | 764 | mov [device.tx_rd_des], 0 |
|
| - | 765 | mov [device.rx_crt_des], 0 |
|
| - | 766 | mov [device.tx_free_des], TX_DES_COUNT |
|
| - | 767 | ||
| 769 | ret |
768 | ret |
| 770 | 769 | ||
| Line 771... | Line 770... | ||
| 771 | 770 | ||
| Line 811... | Line 810... | ||
| 811 | 810 | ||
| 812 | ; if NOT sending FIRST setup packet, must set current descriptor to 0 size for both buffers, |
811 | ; if NOT sending FIRST setup packet, must set current descriptor to 0 size for both buffers, |
| Line 813... | Line 812... | ||
| 813 | ; and go to next descriptor for real setup packet... ;; TODO: check if 2 descriptors are available |
812 | ; and go to next descriptor for real setup packet... ;; TODO: check if 2 descriptors are available |
| 814 | 813 | ||
| 815 | ; cmp [device.tx_packets], 0 |
814 | ; cmp [device.tx_packets], 0 |
| 816 | ; je .not_first |
815 | ; je .first |
| 817 | ; |
816 | ; |
| 818 | ; and [edi+DES.des1], 0 |
817 | ; and [edi+DES.des1], 0 |
| 819 | ; mov [edi+DES.des0], DES0_OWN |
818 | ; mov [edi+DES.des0], DES0_OWN |
| Line 833... | Line 832... | ||
| 833 | ; mov eax, [device.tx_wr_des] |
832 | ; mov eax, [device.tx_wr_des] |
| 834 | ; mov edx, DES.size |
833 | ; mov edx, DES.size |
| 835 | ; mul edx |
834 | ; mul edx |
| 836 | ; add edi, eax |
835 | ; add edi, eax |
| Line 837... | Line 836... | ||
| 837 | 836 | ||
| Line 838... | Line 837... | ||
| 838 | .not_first: |
837 | .first: |
| 839 | 838 | ||
| 840 | push edi |
839 | push edi |
| 841 | ; copy setup packet to current descriptor |
840 | ; copy setup packet to current descriptor |
| 842 | mov edi, [edi+DES.realaddr] |
841 | mov edi, [edi + DES.virtaddr] |
| 843 | ; copy once the address |
842 | ; copy the address once |
| 844 | lea esi, [device.mac] |
843 | lea esi, [device.mac] |
| 845 | DEBUGF 1,"copying packet to %x from %x\n", edi, esi |
844 | DEBUGF 1,"copying packet to %x from %x\n", edi, esi |
| 846 | mov ecx, 3 ; mac is 6 bytes thus 3 words |
845 | mov ecx, 3 ; mac is 6 bytes thus 3 words |
| 847 | .loop: |
846 | .loop: |
| 848 | DEBUGF 1,"%x ", [esi]:4 |
847 | DEBUGF 1,"%x ", [esi]:4 |
| 849 | movsw |
848 | movsw |
| 850 | dec esi |
- | |
| 851 | dec esi |
849 | inc edi |
| 852 | movsw |
850 | inc edi |
| Line 853... | Line 851... | ||
| 853 | dec ecx |
851 | dec ecx |
| Line 862... | Line 860... | ||
| 862 | 860 | ||
| Line 863... | Line 861... | ||
| 863 | pop edi |
861 | pop edi |
| 864 | 862 | ||
| 865 | ; setup descriptor |
863 | ; setup descriptor |
| 866 | DEBUGF 1,"setting up descriptor\n" |
864 | DEBUGF 1,"setting up descriptor\n" |
| Line 867... | Line 865... | ||
| 867 | mov [edi + DES.DES1], TDES1_IC + TDES1_SET + TDES1_TCH + 192 ; size must be EXACTLY 192 bytes |
865 | mov [edi + DES.length], TDES1_IC + TDES1_SET + TDES1_TCH + 192 ; size must be EXACTLY 192 bytes |
| 868 | mov [edi + DES.DES0], DES0_OWN |
866 | mov [edi + DES.status], DES0_OWN |
| 869 | 867 | ||
| 870 | DEBUGF 1,"TDES0: %x\n", [edi + DES.DES0]:8 |
868 | DEBUGF 1,"status: %x\n", [edi + DES.status]:8 |
| Line 871... | Line 869... | ||
| 871 | DEBUGF 1,"TDES1: %x\n", [edi + DES.DES1]:8 |
869 | DEBUGF 1,"length: %x\n", [edi + DES.length]:8 |
| 872 | DEBUGF 1,"TDES2: %x\n", [edi + DES.DES2]:8 |
870 | DEBUGF 1,"buffer1: %x\n", [edi + DES.buffer1]:8 |
| 873 | DEBUGF 1,"TDES3: %x\n", [edi + DES.DES3]:8 |
871 | DEBUGF 1,"buffer2: %x\n", [edi + DES.buffer2]:8 |
| Line 893... | Line 891... | ||
| 893 | DEBUGF 1,"Starting TX\n" |
891 | DEBUGF 1,"Starting TX\n" |
| 894 | jmp .do_it |
892 | jmp .do_it |
| 895 | .already_started: |
893 | .already_started: |
| 896 | ; if already started, issue a Transmit Poll command |
894 | ; if already started, issue a Transmit Poll command |
| 897 | set_io CSR1 |
895 | set_io CSR1 |
| 898 | mov eax, 0 |
896 | xor eax, eax |
| 899 | DEBUGF 1,"Issuing transmit poll command\n" |
897 | DEBUGF 1,"Issuing transmit poll command\n" |
| 900 | .do_it: |
898 | .do_it: |
| 901 | out dx , eax |
899 | out dx, eax |
| 902 | status |
900 | status |
| Line 938... | Line 936... | ||
| 938 | 936 | ||
| 939 | mov eax, [device.tx_wr_des] |
937 | mov eax, [device.tx_wr_des] |
| 940 | mov edx, DES.size |
938 | mov edx, DES.size |
| 941 | mul edx |
939 | mul edx |
| 942 | add eax, [device.tx_p_des] |
940 | add eax, [device.tx_p_des] |
| 943 | mov edi, [eax+DES.realaddr] ; pointer to buffer |
941 | mov edi, [eax + DES.virtaddr] ; pointer to buffer |
| 944 | mov esi, [esp+4] |
942 | mov esi, [esp+4] |
| 945 | mov ecx, [esp+8] |
943 | mov ecx, [esp+8] |
| 946 | DEBUGF 1,"copying %u bytes from %x to %x\n", ecx, esi, edi |
944 | DEBUGF 1,"copying %u bytes from %x to %x\n", ecx, esi, edi |
| Line 947... | Line 945... | ||
| 947 | rep movsb |
945 | rep movsb |
| 948 | 946 | ||
| 949 | ; set packet size |
947 | ; set packet size |
| 950 | mov ecx, [eax+DES.DES1] |
948 | mov ecx, [eax+DES.length] |
| 951 | and ecx, TDES1_TER ; preserve 'End of Ring' bit |
949 | and ecx, TDES1_TER ; preserve 'End of Ring' bit |
| 952 | or ecx, [esp+8] ; set size |
950 | or ecx, [esp+8] ; set size |
| Line 953... | Line 951... | ||
| 953 | or ecx, TDES1_FS or TDES1_LS or TDES1_IC or TDES1_TCH ; first descr, last descr, interrupt on complete, chained modus |
951 | or ecx, TDES1_FS or TDES1_LS or TDES1_IC or TDES1_TCH ; first descr, last descr, interrupt on complete, chained modus |
| 954 | mov [eax+DES.DES1], ecx |
952 | mov [eax+DES.length], ecx |
| Line 955... | Line 953... | ||
| 955 | 953 | ||
| 956 | ; set descriptor info |
954 | ; set descriptor info |
| 957 | mov [eax+DES.DES0], DES0_OWN ; say it is now owned by the 21x4x |
955 | mov [eax+DES.status], DES0_OWN ; say it is now owned by the 21x4x |
| 958 | 956 | ||
| Line 1041... | Line 1039... | ||
| 1041 | DEBUGF 1,"Device: %x CSR5: %x ", ebx, ax |
1039 | DEBUGF 1,"Device: %x CSR5: %x ", ebx, ax |
| Line 1042... | Line 1040... | ||
| 1042 | 1040 | ||
| 1043 | ;---------------------------------- |
1041 | ;---------------------------------- |
| Line 1044... | Line 1042... | ||
| 1044 | ; TX ok? |
1042 | ; TX ok? |
| 1045 | 1043 | ||
| 1046 | test eax, CSR5_TI |
1044 | test ax, CSR5_TI |
| Line 1047... | Line 1045... | ||
| 1047 | jz .not_tx |
1045 | jz .not_tx |
| Line 1061... | Line 1059... | ||
| 1061 | 1059 | ||
| 1062 | ; done if all desc are free |
1060 | ; done if all desc are free |
| 1063 | cmp [device.tx_free_des], TX_DES_COUNT |
1061 | cmp [device.tx_free_des], TX_DES_COUNT |
| Line 1064... | Line 1062... | ||
| 1064 | jz .end_tx |
1062 | jz .end_tx |
| Line 1065... | Line 1063... | ||
| 1065 | 1063 | ||
| 1066 | mov eax, [edi+DES.DES0] |
1064 | mov eax, [edi+DES.status] |
| 1067 | 1065 | ||
| Line 1099... | Line 1097... | ||
| 1099 | pop ecx esi ax |
1097 | pop ecx esi ax |
| Line 1100... | Line 1098... | ||
| 1100 | 1098 | ||
| 1101 | ;---------------------------------- |
1099 | ;---------------------------------- |
| 1102 | ; RX irq |
1100 | ; RX irq |
| 1103 | .not_tx: |
1101 | .not_tx: |
| 1104 | test eax, CSR5_RI |
1102 | test ax, CSR5_RI |
| 1105 | jz .not_rx |
1103 | jz .not_rx |
| Line 1106... | Line 1104... | ||
| 1106 | push ax esi ecx |
1104 | push ax esi ecx |
| Line 1107... | Line 1105... | ||
| 1107 | 1105 | ||
| - | 1106 | DEBUGF 1,"RX ok!\n" |
|
| 1108 | DEBUGF 1,"RX ok!\n" |
1107 | |
| Line -... | Line 1108... | ||
| - | 1108 | push ebx |
|
| - | 1109 | .rx_loop: |
|
| 1109 | 1110 | pop ebx |
|
| 1110 | ;go to current descriptor |
1111 | |
| 1111 | mov edi, [device.rx_p_des] |
1112 | ; get current descriptor |
| 1112 | 1113 | mov edi, [device.rx_p_des] |
|
| Line 1113... | Line 1114... | ||
| 1113 | mov eax, [device.rx_crt_des] |
1114 | mov eax, [device.rx_crt_des] |
| 1114 | mov edx, DES.size |
1115 | mov edx, DES.size |
| Line 1115... | Line 1116... | ||
| 1115 | mul edx |
1116 | mul edx |
| 1116 | add edi, eax |
1117 | add edi, eax |
| Line 1117... | Line 1118... | ||
| 1117 | 1118 | ||
| 1118 | .loop_rx_start_of_packet: |
1119 | ; now check status |
| Line 1119... | Line 1120... | ||
| 1119 | mov eax, [edi+DES.DES0] |
1120 | mov eax, [edi + DES.status] |
| 1120 | 1121 | ||
| Line 1121... | Line -... | ||
| 1121 | test eax, DES0_OWN |
- | |
| 1122 | jnz .end_rx ; current desc is busy, nothing to do |
- | |
| 1123 | - | ||
| 1124 | test eax, RDES0_FS |
- | |
| 1125 | jz .end_rx ; current desc is NOT first packet, ERROR! |
- | |
| 1126 | 1122 | test eax, DES0_OWN |
|
| 1127 | test eax, RDES0_LS ; if not last desc of packet, error for now |
1123 | jnz .end_rx ; current desc is busy, nothing to do |
| Line 1128... | Line -... | ||
| 1128 | jz .end_rx |
- | |
| 1129 | - | ||
| 1130 | ; .IF ZERO? |
- | |
| 1131 | ; ODS2 <"Net_Interrupt: packet > 1 descriptor, not supported yet :P"> |
- | |
| 1132 | ; jmp @@end_rx |
- | |
| 1133 | ; .ENDIF |
1124 | |
| 1134 | 1125 | test eax, RDES0_FS |
|
| 1135 | test eax, RDES0_ES |
1126 | jz .end_rx ; current desc is NOT first packet, ERROR! |
| 1136 | jnz .end_rx |
1127 | |
| 1137 | 1128 | test eax, RDES0_LS ; if not last desc of packet, error for now |
|
| Line 1138... | Line 1129... | ||
| 1138 | ; .IF !ZERO? |
1129 | jz .end_rx |
| Line 1139... | Line 1130... | ||
| 1139 | ; ODS2 <"Net_Interrupt: RX error"> |
1130 | |
| 1140 | ; jmp @@end_rx |
1131 | test eax, RDES0_ES |
| 1141 | ; .ENDIF |
1132 | jnz .end_rx |
| 1142 | 1133 | ||
| 1143 | mov esi, [edi+DES.realaddr] |
1134 | mov esi, [edi + DES.virtaddr] |
| Line 1144... | Line 1135... | ||
| 1144 | mov ecx, [edi+DES.DES0] |
1135 | mov ecx, [edi + DES.status] |
| 1145 | shr ecx, RDES0_FL_SH |
1136 | shr ecx, RDES0_FL_SH |
| 1146 | and ecx, RDES0_FL_MASK |
1137 | and ecx, RDES0_FL_MASK |
| 1147 | sub ecx, 4 ; crc |
1138 | sub ecx, 4 ; crc, we dont need it |
| Line 1148... | Line 1139... | ||
| 1148 | 1139 | ||
| 1149 | DEBUGF 1,"Received packet!, size=%u, addr:%x\n", ecx, esi |
1140 | DEBUGF 1,"Received packet!, size=%u, addr:%x\n", ecx, esi |
| 1150 | - | ||
| 1151 | push esi edi ecx |
1141 | |
| 1152 | stdcall KernelAlloc, ecx ; Allocate a buffer to put packet into |
1142 | push esi edi ecx |
| Line 1153... | Line 1143... | ||
| 1153 | pop ecx edi esi |
1143 | stdcall KernelAlloc, ecx ; Allocate a buffer to put packet into |
| 1154 | test eax, eax |
1144 | pop ecx edi esi |
| Line 1174... | Line 1164... | ||
| 1174 | jnc .nw |
1164 | jnc .nw |
| 1175 | movsw |
1165 | movsw |
| 1176 | .nw: |
1166 | .nw: |
| 1177 | rep movsd |
1167 | rep movsd |
| Line 1178... | Line -... | ||
| 1178 | - | ||
| 1179 | jmp Eth_input |
- | |
| 1180 | - | ||
| 1181 | .continue_rx: |
- | |
| 1182 | pop edi |
- | |
| 1183 | - | ||
| 1184 | ; free descriptor |
1168 | |
| Line 1185... | Line -... | ||
| 1185 | mov [edi+DES.DES0], DES0_OWN |
- | |
| 1186 | - | ||
| 1187 | ; next descriptor |
- | |
| 1188 | add edi, DES.size |
1169 | mov [edi + DES.status], DES0_OWN ; free descriptor |
| 1189 | 1170 | ||
| Line 1190... | Line 1171... | ||
| 1190 | inc [device.rx_crt_des] |
1171 | inc [device.rx_crt_des] ; next descriptor |
| Line 1191... | Line 1172... | ||
| 1191 | and [device.rx_crt_des], RX_DES_COUNT-1 |
1172 | and [device.rx_crt_des], RX_DES_COUNT-1 |
| 1192 | 1173 | ||
| 1193 | jmp .loop_rx_start_of_packet |
1174 | jmp Eth_input |
| 1194 | 1175 | ||