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Line 81... Line 81...
81
CSR6	equ	0x30	 ; Operation mode
81
CSR6	equ	0x30	 ; Operation mode
82
CSR7	equ	0x38	 ; Interrupt enable
82
CSR7	equ	0x38	 ; Interrupt enable
83
CSR8	equ	0x40	 ; Missed frames and overflow counter
83
CSR8	equ	0x40	 ; Missed frames and overflow counter
84
CSR9	equ	0x48	 ; Boot ROM, serial ROM, and MII management
84
CSR9	equ	0x48	 ; Boot ROM, serial ROM, and MII management
85
CSR10	equ	0x50	 ; Boot ROM programming address
85
CSR10	equ	0x50	 ; Boot ROM programming address
86
;CSR11 General-purpose timer 0x58
86
CSR11	equ	0x58	 ; General-purpose timer
87
CSR12	equ	0x60	 ; General-purpose port
87
CSR12	equ	0x60	 ; General-purpose port
88
CSR13	equ	0x68
88
CSR13	equ	0x68
89
;CSR14 Reserved 0x70
89
CSR14	equ	0x70
90
;CSR15 Watchdog timer 0x78
90
CSR15	equ	0x78	 ; Watchdog timer
Line 91... Line 91...
91
 
91
 
92
;--------bits/commands of CSR0-------------------
92
;--------bits/commands of CSR0-------------------
Line 93... Line 93...
93
CSR0_RESET		equ	1b
93
CSR0_RESET		equ	1b
Line 274... Line 274...
274
CSR9_SROM_DO		equ	1 SHL 3 	; Data Out for SROM
274
CSR9_SROM_DO		equ	1 SHL 3 	; Data Out for SROM
275
CSR9_SROM_DI		equ	1 SHL 2 	; Data In to SROM
275
CSR9_SROM_DI		equ	1 SHL 2 	; Data In to SROM
276
CSR9_SROM_CK		equ	1 SHL 1 	; clock for SROM
276
CSR9_SROM_CK		equ	1 SHL 1 	; clock for SROM
277
CSR9_SROM_CS		equ	1 SHL 0 	; chip select.. always needed
277
CSR9_SROM_CS		equ	1 SHL 0 	; chip select.. always needed
Line 278... Line 278...
278
 
278
 
279
; assume dx is CSR9 (SROM port)
279
; assume dx is CSR9
280
macro SROM_Delay {
280
macro SROM_Delay {
281
	push	eax
281
	push	eax
282
	in	eax, dx
282
	in	eax, dx
283
	in	eax, dx
283
	in	eax, dx
Line 290... Line 290...
290
	in	eax, dx
290
	in	eax, dx
291
	in	eax, dx
291
	in	eax, dx
292
	pop	eax
292
	pop	eax
293
}
293
}
Line -... Line 294...
-
 
294
 
-
 
295
; assume dx is CSR9
-
 
296
macro MDIO_Delay {
-
 
297
	push	eax
-
 
298
	in	eax, dx
-
 
299
	pop	eax
-
 
300
}
294
 
301
 
295
macro Bit_Set a_bit {
302
macro Bit_Set a_bit {
296
	in	eax, dx
303
	in	eax, dx
297
	or	eax, a_bit
304
	or	eax, a_bit
298
	out	dx , eax
305
	out	dx , eax
Line 740... Line 747...
740
	Bit_Set CSR6_SR; or CSR6_PR or CSR6_ST
747
	Bit_Set CSR6_SR; or CSR6_PR or CSR6_ST
741
	DEBUGF	1,"CSR6: %x\n", eax
748
	DEBUGF	1,"CSR6: %x\n", eax
Line 742... Line 749...
742
 
749
 
Line -... Line 750...
-
 
750
	status
-
 
751
 
Line 743... Line 752...
743
	status
752
	call	start_link
744
 
753
 
745
 
754
 
Line 746... Line 755...
746
; wait a bit
755
; wait a bit
747
	mov	esi, 3000
756
	mov	esi, 3000
Line 748... Line 757...
748
	call	Sleep
757
	call	Sleep
Line -... Line 758...
-
 
758
 
-
 
759
;----------------------------------------------------
-
 
760
; send setup packet to notify the board about the MAC
-
 
761
 
749
 
762
	call	Send_Setup_Packet
750
;----------------------------------------------------
763
 
Line 751... Line 764...
751
; send setup packet to notify the board about the MAC
764
	xor	eax, eax
-
 
765
; clear packet/byte counters
-
 
766
 
-
 
767
	lea	edi, [device.bytes_tx]
-
 
768
	mov	ecx, 6
-
 
769
	rep	stosd
752
 
770
 
-
 
771
	DEBUGF	1,"Reset done\n"
-
 
772
 
Line 753... Line 773...
753
	call	Send_Setup_Packet
773
	ret
Line 754... Line 774...
754
 
774
 
755
	set_io	0
775
 
Line 864... Line 884...
864
	cmp	[device.tx_free_des], 0
884
	cmp	[device.tx_free_des], 0
865
	jz	@f
885
	jz	@f
866
	dec	[device.tx_free_des]
886
	dec	[device.tx_free_des]
867
       @@:
887
       @@:
Line 868... Line -...
868
 
-
 
869
	wbinvd;;;
-
 
870
 
888
 
871
; start tx
889
; start tx
872
	set_io	0
890
	set_io	0
873
	status
891
	status
874
	set_io	CSR6
892
	set_io	CSR6
Line 940... Line 958...
940
	mov	[eax+DES.DES1], ecx
958
	mov	[eax+DES.DES1], ecx
Line 941... Line 959...
941
 
959
 
942
; set descriptor info
960
; set descriptor info
Line 943... Line -...
943
	mov	[eax+DES.DES0], DES0_OWN		; say it is now owned by the 21x4x
-
 
944
 
-
 
945
	DEBUGF	1,"TDES0: %x\n", [eax+DES.DES0]:8
-
 
946
	DEBUGF	1,"TDES1: %x\n", [eax+DES.DES1]:8
-
 
947
	DEBUGF	1,"TDES2: %x\n", [eax+DES.DES2]:8
-
 
948
	DEBUGF	1,"TDES3: %x\n", [eax+DES.DES3]:8
-
 
949
 
961
	mov	[eax+DES.DES0], DES0_OWN		; say it is now owned by the 21x4x
950
 
962
 
951
; start tx
963
; start tx
952
	set_io	0
964
	set_io	0
953
	status
965
	status
Line 960... Line 972...
960
	jmp	.do_it
972
	jmp	.do_it
961
  .already_started:
973
  .already_started:
962
					; if already started, issues a Transmit Poll command
974
					; if already started, issues a Transmit Poll command
963
	set_io	CSR1
975
	set_io	CSR1
964
	mov	eax, -1
976
	mov	eax, -1
965
	DEBUGF	1,"Sending transmit poll command\n"
-
 
966
  .do_it:
977
  .do_it:
967
	out	dx , eax
978
	out	dx , eax
968
	status
-
 
Line -... Line 979...
-
 
979
 
Line -... Line 980...
-
 
980
; Update stats
969
 
981
 
-
 
982
	inc	[device.packets_tx]
-
 
983
	mov	eax, [esp+8]
Line 970... Line 984...
970
 
984
	add	dword [device.bytes_tx], eax
971
	wbinvd;;;;
985
	adc	dword [device.bytes_tx + 4], 0
972
 
986
 
Line 1448... Line 1462...
1448
	DEBUGF 1,"%x\n", ax
1462
	DEBUGF 1,"%x\n", ax
Line 1449... Line 1463...
1449
 
1463
 
Line -... Line 1464...
-
 
1464
	ret
-
 
1465
 
-
 
1466
 
-
 
1467
 
-
 
1468
 
-
 
1469
 
-
 
1470
 
-
 
1471
 
-
 
1472
;<<<<<<<<<<<<<<<<<<<<<<<<<<<<
-
 
1473
 
-
 
1474
 
-
 
1475
 
-
 
1476
;*********************************************************************
-
 
1477
;* Media Descriptor Code                                             *
-
 
1478
;*********************************************************************
-
 
1479
 
-
 
1480
; MII transceiver control section.
-
 
1481
; Read and write the MII registers using software-generated serial
-
 
1482
; MDIO protocol.  See the MII specifications or DP83840A data sheet
-
 
1483
; for details.
-
 
1484
 
-
 
1485
; The maximum data clock rate is 2.5 Mhz.  The minimum timing is usually
-
 
1486
; met by back-to-back PCI I/O cycles, but we insert a delay to avoid
-
 
1487
; "overclocking" issues or future 66Mhz PCI.
-
 
1488
 
-
 
1489
; Read and write the MII registers using software-generated serial
-
 
1490
; MDIO protocol.  It is just different enough from the EEPROM protocol
-
 
1491
; to not share code.  The maxium data clock rate is 2.5 Mhz.
-
 
1492
 
-
 
1493
MDIO_SHIFT_CLK		equ	0x10000
-
 
1494
MDIO_DATA_WRITE0	equ	0x00000
-
 
1495
MDIO_DATA_WRITE1	equ	0x20000
-
 
1496
MDIO_ENB		equ	0x00000 	; Ignore the 0x02000 databook setting.
-
 
1497
MDIO_ENB_IN		equ	0x40000
-
 
1498
MDIO_DATA_READ		equ	0x80000
-
 
1499
 
-
 
1500
; MII transceiver control section.
-
 
1501
; Read and write the MII registers using software-generated serial
-
 
1502
; MDIO protocol.  See the MII specifications or DP83840A data sheet
-
 
1503
; for details.
-
 
1504
 
-
 
1505
align 4
-
 
1506
mdio_read:	; phy_id:edx, location:esi
-
 
1507
 
-
 
1508
	DEBUGF	1,"mdio read, phy=%x, location=%x", edx, esi
-
 
1509
 
-
 
1510
	shl	edx, 5
-
 
1511
	or	esi, edx
-
 
1512
	or	esi, 0xf6 shl 10
-
 
1513
 
-
 
1514
	set_io	0
-
 
1515
	set_io	CSR9
-
 
1516
 
-
 
1517
;    if (tp->chip_id == LC82C168) {
-
 
1518
;        int i = 1000;
-
 
1519
;        outl(0x60020000 + (phy_id<<23) + (location<<18), ioaddr + 0xA0);
-
 
1520
;        inl(ioaddr + 0xA0);
-
 
1521
;        inl(ioaddr + 0xA0);
-
 
1522
;        while (--i > 0)
-
 
1523
;            if ( ! ((retval = inl(ioaddr + 0xA0)) & 0x80000000))
-
 
1524
;                return retval & 0xffff;
-
 
1525
;        return 0xffff;
-
 
1526
;    }
-
 
1527
;
-
 
1528
;    if (tp->chip_id == COMET) {
-
 
1529
;        if (phy_id == 1) {
-
 
1530
;            if (location < 7)
-
 
1531
;                return inl(ioaddr + 0xB4 + (location<<2));
-
 
1532
;            else if (location == 17)
-
 
1533
;                return inl(ioaddr + 0xD0);
-
 
1534
;            else if (location >= 29 && location <= 31)
-
 
1535
;                return inl(ioaddr + 0xD4 + ((location-29)<<2));
-
 
1536
;        }
-
 
1537
;        return 0xffff;
-
 
1538
;    }
-
 
1539
 
-
 
1540
; Establish sync by sending at least 32 logic ones.
-
 
1541
 
-
 
1542
	mov	ecx, 32
-
 
1543
  .loop:
-
 
1544
	mov	eax, MDIO_ENB or MDIO_DATA_WRITE1
-
 
1545
	out	dx, eax
-
 
1546
	MDIO_Delay
-
 
1547
 
-
 
1548
	or	eax, MDIO_SHIFT_CLK
-
 
1549
	out	dx, eax
-
 
1550
	MDIO_Delay
-
 
1551
 
-
 
1552
	dec	ecx
-
 
1553
	jnz	.loop
-
 
1554
 
-
 
1555
 
-
 
1556
; Shift the read command bits out.
-
 
1557
 
-
 
1558
	mov	ecx, 1 shl 15
-
 
1559
  .loop2:
-
 
1560
	mov	eax, MDIO_ENB
-
 
1561
	test	esi, ecx
-
 
1562
	jz	@f
-
 
1563
	or	eax, MDIO_DATA_WRITE1
-
 
1564
       @@:
-
 
1565
	out	dx, eax
-
 
1566
	MDIO_Delay
-
 
1567
 
-
 
1568
	or	eax, MDIO_SHIFT_CLK
-
 
1569
	out	dx, eax
-
 
1570
	MDIO_Delay
-
 
1571
 
-
 
1572
	shr	ecx, 1
-
 
1573
	jnz	.loop2
-
 
1574
 
-
 
1575
 
-
 
1576
; Read the two transition, 16 data, and wire-idle bits.
-
 
1577
 
-
 
1578
	xor	esi, esi
-
 
1579
	mov	ecx, 19
-
 
1580
  .loop3:
-
 
1581
	mov	eax, MDIO_ENB_IN
-
 
1582
	out	dx, eax
-
 
1583
	MDIO_Delay
-
 
1584
 
-
 
1585
	shl	esi, 1
-
 
1586
	in	eax, dx
-
 
1587
	test	eax, MDIO_DATA_READ
-
 
1588
	jz	@f
-
 
1589
	inc	esi
-
 
1590
       @@:
-
 
1591
 
-
 
1592
	mov	eax, MDIO_ENB_IN or MDIO_SHIFT_CLK
-
 
1593
	out	dx, eax
-
 
1594
	MDIO_Delay
-
 
1595
 
-
 
1596
	dec	ecx
-
 
1597
	jnz	.loop3
-
 
1598
 
-
 
1599
	shr	esi, 1
-
 
1600
	movzx	eax, si
-
 
1601
 
-
 
1602
	DEBUGF	1,", data=%x\n", ax
-
 
1603
 
-
 
1604
	ret
-
 
1605
 
-
 
1606
 
-
 
1607
 
-
 
1608
 
-
 
1609
align 4
-
 
1610
mdio_write:	;int phy_id: edx, int location: edi, int value: ax)
-
 
1611
 
-
 
1612
	DEBUGF	1,"mdio write, phy=%x, location=%x, data=%x\n", edx, edi, ax
-
 
1613
 
-
 
1614
	shl	edi, 18
-
 
1615
	or	edi, 0x5002 shl 16
-
 
1616
	shl	edx, 23
-
 
1617
	or	edi, edx
-
 
1618
	mov	di, ax
-
 
1619
 
-
 
1620
	set_io	0
-
 
1621
	set_io	CSR9
-
 
1622
 
-
 
1623
;    if (tp->chip_id == LC82C168) {
-
 
1624
;        int i = 1000;
-
 
1625
;        outl(cmd, ioaddr + 0xA0);
-
 
1626
;        do
-
 
1627
;            if ( ! (inl(ioaddr + 0xA0) & 0x80000000))
-
 
1628
;                break;
-
 
1629
;        while (--i > 0);
-
 
1630
;        return;
-
 
1631
;    }
-
 
1632
 
-
 
1633
;    if (tp->chip_id == COMET) {
-
 
1634
;        if (phy_id != 1)
-
 
1635
;            return;
-
 
1636
;        if (location < 7)
-
 
1637
;            outl(value, ioaddr + 0xB4 + (location<<2));
-
 
1638
;        else if (location == 17)
-
 
1639
;            outl(value, ioaddr + 0xD0);
-
 
1640
;        else if (location >= 29 && location <= 31)
-
 
1641
;            outl(value, ioaddr + 0xD4 + ((location-29)<<2));
-
 
1642
;        return;
-
 
1643
;    }
-
 
1644
 
-
 
1645
 
-
 
1646
; Establish sync by sending at least 32 logic ones.
-
 
1647
 
-
 
1648
	mov	ecx, 32
-
 
1649
  .loop:
-
 
1650
	mov	eax, MDIO_ENB or MDIO_DATA_WRITE1
-
 
1651
	out	dx, eax
-
 
1652
	MDIO_Delay
-
 
1653
 
-
 
1654
	or	eax, MDIO_SHIFT_CLK
-
 
1655
	out	dx, eax
-
 
1656
	MDIO_Delay
-
 
1657
 
-
 
1658
	dec	ecx
-
 
1659
	jnz	.loop
-
 
1660
 
-
 
1661
 
-
 
1662
; Shift the command bits out.
-
 
1663
 
-
 
1664
	mov	ecx, 1 shl 31
-
 
1665
  .loop2:
-
 
1666
	mov	eax, MDIO_ENB
-
 
1667
	test	edi, ecx
-
 
1668
	jz	@f
-
 
1669
	or	eax, MDIO_DATA_WRITE1
-
 
1670
       @@:
-
 
1671
	out	dx, eax
-
 
1672
	MDIO_Delay
-
 
1673
 
-
 
1674
	or	eax, MDIO_SHIFT_CLK
-
 
1675
	out	dx, eax
-
 
1676
	MDIO_Delay
-
 
1677
 
-
 
1678
	shr	ecx, 1
-
 
1679
	jnz	.loop2
-
 
1680
 
-
 
1681
 
-
 
1682
; Clear out extra bits.
-
 
1683
 
-
 
1684
	mov	ecx, 2
-
 
1685
  .loop3:
-
 
1686
	mov	eax, MDIO_ENB
-
 
1687
	out	dx, eax
-
 
1688
	MDIO_Delay
-
 
1689
 
-
 
1690
	or	eax, MDIO_SHIFT_CLK
-
 
1691
	out	dx, eax
-
 
1692
	MDIO_Delay
-
 
1693
 
-
 
1694
	dec	ecx
-
 
1695
	jnz	.loop3
-
 
1696
 
1450
	ret
1697
	ret
Line 1451... Line 1698...
1451
 
1698
 
Line 1452... Line 1699...
1452
 
1699