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	volatile long count;
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	volatile long count;
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} atomic_t;
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} atomic_t;
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static inline void atomic_inc(atomic_t *val) {
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static inline void atomic_inc(atomic_t *val) {
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#ifdef USE_SMP
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#ifdef USE_SMP
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  asm volatile ("lock inc %0\n" : "+m" (val->count));
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  asm volatile ("lock incl %0\n" : "+m" (val->count));
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#else
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#else
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  asm volatile ("inc %0\n" : "+m" (val->count));
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  asm volatile ("incl %0\n" : "+m" (val->count));
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#endif /* USE_SMP */
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#endif /* USE_SMP */
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}
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}
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static inline void atomic_dec(atomic_t *val) {
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static inline void atomic_dec(atomic_t *val) {
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#ifdef USE_SMP
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#ifdef USE_SMP
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  asm volatile ("lock dec %0\n" : "+m" (val->count));
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  asm volatile ("lock decl %0\n" : "+m" (val->count));
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#else
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#else
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  asm volatile ("dec %0\n" : "+m" (val->count));
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  asm volatile ("decl %0\n" : "+m" (val->count));
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#endif /* USE_SMP */
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#endif /* USE_SMP */
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}
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}
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static inline void atomic_lock_arch(atomic_t *val)
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static inline void atomic_lock_arch(atomic_t *val)
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{
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{
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  u32_t tmp;
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  u32_t tmp;
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- 
 
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//  preemption_disable();
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//  preemption_disable();
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	asm volatile (
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    asm volatile (
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    "0:\n"
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		"0:\n"
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    "pause\n\t" /* Pentium 4's HT love this instruction */
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		"pause\n" /* Pentium 4's HT love this instruction */
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    "mov %1, [%0]\n\t"
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		"mov %0, %1\n"
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    "test %1, %1\n\t"
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		"testl %1, %1\n"
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    "jnz 0b\n\t"       /* lightweight looping on locked spinlock */
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		"jnz 0b\n"       /* lightweight looping on locked spinlock */
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    "inc %1\n\t"      /* now use the atomic operation */
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		"incl %1\n"      /* now use the atomic operation */
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    "xchg [%0], %1\n\t"
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		"xchgl %0, %1\n"
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    "test %1, %1\n\t"
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		"testl %1, %1\n"
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    "jnz 0b\n\t"
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		"jnz 0b\n"
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    : "+m" (val->count), "=r"(tmp)
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    : "+m" (val->count), "=&r"(tmp)
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	);
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	/*
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	 * Prevent critical section code from bleeding out this way up.
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	 */
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  );
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 // CS_ENTER_BARRIER();
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 // CS_ENTER_BARRIER();
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}
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}
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