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Rev 1635 | Rev 2434 | ||
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Line 24... | Line 24... | ||
24 | ;; ;; |
24 | ;; ;; |
25 | ;; See file COPYING for details ;; |
25 | ;; See file COPYING for details ;; |
26 | ;; ;; |
26 | ;; ;; |
27 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
27 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
Line 28... | Line 28... | ||
28 | 28 | ||
Line 167... | Line 167... | ||
167 | RTL8169_DSB_EORbit equ 0x40000000 |
167 | RTL8169_DSB_EORbit equ 0x40000000 |
168 | RTL8169_DSB_FSbit equ 0x20000000 |
168 | RTL8169_DSB_FSbit equ 0x20000000 |
Line 169... | Line 169... | ||
169 | RTL8169_DSB_LSbit equ 0x10000000 |
169 | RTL8169_DSB_LSbit equ 0x10000000 |
170 | 170 | ||
Line 171... | Line 171... | ||
171 | ; MAC address length |
171 | ; MAC address length |
Line 172... | Line 172... | ||
172 | MAC_ADDR_LEN equ 6 |
172 | MAC_ADDR_LEN equ 6 |
173 | 173 | ||
174 | ; max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4) |
174 | ; max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4) |
175 | MAX_ETH_FRAME_SIZE equ 1536 |
175 | MAX_ETH_FRAME_SIZE equ 1536 |
176 | 176 | ||
177 | TX_FIFO_THRESH equ 256 ; In bytes |
177 | TX_FIFO_THRESH equ 256 ; In bytes |
178 | 178 | ||
179 | RX_FIFO_THRESH equ 7 ; 7 means NO threshold, Rx buffer level before first PCI xfer |
179 | RX_FIFO_THRESH equ 7 ; 7 means NO threshold, Rx buffer level before first PCI xfer |
180 | RX_DMA_BURST equ 7 ; Maximum PCI burst, '6' is 1024 |
180 | RX_DMA_BURST equ 7 ; Maximum PCI burst, '6' is 1024 |
181 | TX_DMA_BURST equ 7 ; Maximum PCI burst, '6' is 1024 |
181 | TX_DMA_BURST equ 7 ; Maximum PCI burst, '6' is 1024 |
182 | ETTh equ 0x3F ; 0x3F means NO threshold |
182 | ETTh equ 0x3F ; 0x3F means NO threshold |
183 | 183 | ||
Line 184... | Line 184... | ||
184 | EarlyTxThld equ 0x3F ; 0x3F means NO early transmit |
184 | EarlyTxThld equ 0x3F ; 0x3F means NO early transmit |
Line 185... | Line 185... | ||
185 | RxPacketMaxSize equ 0x0800 ; Maximum size supported is 16K-1 |
185 | RxPacketMaxSize equ 0x0800 ; Maximum size supported is 16K-1 |
186 | InterFrameGap equ 0x03 ; 3 means InterFrameGap = the shortest one |
186 | InterFrameGap equ 0x03 ; 3 means InterFrameGap = the shortest one |
Line 187... | Line 187... | ||
187 | 187 | ||
Line 188... | Line 188... | ||
188 | NUM_TX_DESC equ 1 ; Number of Tx descriptor registers |
188 | NUM_TX_DESC equ 1 ; Number of Tx descriptor registers |
189 | NUM_RX_DESC equ 4 ; Number of Rx descriptor registers |
189 | NUM_RX_DESC equ 4 ; Number of Rx descriptor registers |
190 | RX_BUF_SIZE equ 1536 ; Rx Buffer size |
190 | RX_BUF_SIZE equ 1536 ; Rx Buffer size |
Line 191... | Line 191... | ||
191 | 191 | ||
192 | HZ equ 1000 |
192 | HZ equ 1000 |
Line 210... | Line 210... | ||
210 | 210 | ||
211 | ;#ifdef RTL8169_USE_IO |
211 | ;#ifdef RTL8169_USE_IO |
212 | ;!!!#define RTL_W8(reg, val8) outb ((val8), ioaddr + (reg)) |
212 | ;!!!#define RTL_W8(reg, val8) outb ((val8), ioaddr + (reg)) |
213 | macro RTL_W8 reg,val8 { |
213 | macro RTL_W8 reg,val8 { |
214 | if ~reg eq dx |
214 | if ~reg eq dx |
215 | mov dx,word[rtl8169_tpc.mmio_addr] |
215 | mov dx, word[rtl8169_tpc.mmio_addr] |
216 | add dx,reg |
216 | add dx, reg |
217 | end if |
217 | end if |
218 | if ~val8 eq al |
218 | if ~val8 eq al |
219 | mov al,val8 |
219 | mov al, val8 |
220 | end if |
220 | end if |
221 | out dx,al |
221 | out dx, al |
222 | } |
222 | } |
223 | ;!!!#define RTL_W16(reg, val16) outw ((val16), ioaddr + (reg)) |
223 | ;!!!#define RTL_W16(reg, val16) outw ((val16), ioaddr + (reg)) |
224 | macro RTL_W16 reg,val16 { |
224 | macro RTL_W16 reg,val16 { |
225 | if ~reg eq dx |
225 | if ~reg eq dx |
226 | mov dx,word[rtl8169_tpc.mmio_addr] |
226 | mov dx, word[rtl8169_tpc.mmio_addr] |
227 | add dx,reg |
227 | add dx, reg |
228 | end if |
228 | end if |
229 | if ~val16 eq ax |
229 | if ~val16 eq ax |
230 | mov ax,val16 |
230 | mov ax, val16 |
231 | end if |
231 | end if |
232 | out dx,ax |
232 | out dx, ax |
233 | } |
233 | } |
234 | ;!!!#define RTL_W32(reg, val32) outl ((val32), ioaddr + (reg)) |
234 | ;!!!#define RTL_W32(reg, val32) outl ((val32), ioaddr + (reg)) |
235 | macro RTL_W32 reg,val32 { |
235 | macro RTL_W32 reg,val32 { |
236 | if ~reg eq dx |
236 | if ~reg eq dx |
237 | mov dx,word[rtl8169_tpc.mmio_addr] |
237 | mov dx, word[rtl8169_tpc.mmio_addr] |
238 | add dx,reg |
238 | add dx, reg |
239 | end if |
239 | end if |
240 | if ~val32 eq eax |
240 | if ~val32 eq eax |
241 | mov eax,val32 |
241 | mov eax, val32 |
242 | end if |
242 | end if |
243 | out dx,eax |
243 | out dx, eax |
244 | } |
244 | } |
245 | ;!!!#define RTL_R8(reg) inb (ioaddr + (reg)) |
245 | ;!!!#define RTL_R8(reg) inb (ioaddr + (reg)) |
246 | macro RTL_R8 reg { |
246 | macro RTL_R8 reg { |
247 | if ~reg eq dx |
247 | if ~reg eq dx |
248 | mov dx,word[rtl8169_tpc.mmio_addr] |
248 | mov dx, word[rtl8169_tpc.mmio_addr] |
249 | add dx,reg |
249 | add dx, reg |
250 | end if |
250 | end if |
251 | in al,dx |
251 | in al, dx |
252 | } |
252 | } |
253 | ;!!!#define RTL_R16(reg) inw (ioaddr + (reg)) |
253 | ;!!!#define RTL_R16(reg) inw (ioaddr + (reg)) |
254 | macro RTL_R16 reg { |
254 | macro RTL_R16 reg { |
255 | if ~reg eq dx |
255 | if ~reg eq dx |
256 | mov dx,word[rtl8169_tpc.mmio_addr] |
256 | mov dx, word[rtl8169_tpc.mmio_addr] |
257 | add dx,reg |
257 | add dx, reg |
258 | end if |
258 | end if |
259 | in ax,dx |
259 | in ax, dx |
260 | } |
260 | } |
261 | ;!!!#define RTL_R32(reg) ((unsigned long) inl (ioaddr + (reg))) |
261 | ;!!!#define RTL_R32(reg) ((unsigned long) inl (ioaddr + (reg))) |
262 | macro RTL_R32 reg { |
262 | macro RTL_R32 reg { |
263 | if ~reg eq dx |
263 | if ~reg eq dx |
264 | mov dx,word[rtl8169_tpc.mmio_addr] |
264 | mov dx, word[rtl8169_tpc.mmio_addr] |
265 | add dx,reg |
265 | add dx, reg |
266 | end if |
266 | end if |
267 | in eax,dx |
267 | in eax, dx |
268 | } |
268 | } |
269 | ;#else |
269 | ;#else |
270 | ; write/read MMIO register |
270 | ; write/read MMIO register |
271 | ;#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) |
271 | ;#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) |
Line 274... | Line 274... | ||
274 | ;#define RTL_R8(reg) readb (ioaddr + (reg)) |
274 | ;#define RTL_R8(reg) readb (ioaddr + (reg)) |
275 | ;#define RTL_R16(reg) readw (ioaddr + (reg)) |
275 | ;#define RTL_R16(reg) readw (ioaddr + (reg)) |
276 | ;#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) |
276 | ;#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) |
277 | ;#endif |
277 | ;#endif |
Line 278... | Line 278... | ||
278 | 278 | ||
279 | MCFG_METHOD_01 equ 0x01 |
279 | MCFG_METHOD_01 equ 0x01 |
280 | MCFG_METHOD_02 equ 0x02 |
280 | MCFG_METHOD_02 equ 0x02 |
281 | MCFG_METHOD_03 equ 0x03 |
281 | MCFG_METHOD_03 equ 0x03 |
282 | MCFG_METHOD_04 equ 0x04 |
282 | MCFG_METHOD_04 equ 0x04 |
283 | MCFG_METHOD_05 equ 0x05 |
283 | MCFG_METHOD_05 equ 0x05 |
284 | MCFG_METHOD_11 equ 0x0b |
284 | MCFG_METHOD_11 equ 0x0b |
285 | MCFG_METHOD_12 equ 0x0c |
285 | MCFG_METHOD_12 equ 0x0c |
286 | MCFG_METHOD_13 equ 0x0d |
286 | MCFG_METHOD_13 equ 0x0d |
287 | MCFG_METHOD_14 equ 0x0e |
287 | MCFG_METHOD_14 equ 0x0e |
288 | MCFG_METHOD_15 equ 0x0f |
288 | MCFG_METHOD_15 equ 0x0f |
289 | 289 | ||
290 | PCFG_METHOD_1 equ 0x01 ; PHY Reg 0x03 bit0-3 == 0x0000 |
290 | PCFG_METHOD_1 equ 0x01 ; PHY Reg 0x03 bit0-3 == 0x0000 |
291 | PCFG_METHOD_2 equ 0x02 ; PHY Reg 0x03 bit0-3 == 0x0001 |
291 | PCFG_METHOD_2 equ 0x02 ; PHY Reg 0x03 bit0-3 == 0x0001 |
292 | PCFG_METHOD_3 equ 0x03 ; PHY Reg 0x03 bit0-3 == 0x0002 |
292 | PCFG_METHOD_3 equ 0x03 ; PHY Reg 0x03 bit0-3 == 0x0002 |
293 | 293 | ||
294 | PCI_COMMAND_IO equ 0x1 ; Enable response in I/O space |
294 | PCI_COMMAND_IO equ 0x1 ; Enable response in I/O space |
295 | PCI_COMMAND_MEM equ 0x2 ; Enable response in mem space |
295 | PCI_COMMAND_MEM equ 0x2 ; Enable response in mem space |
296 | PCI_COMMAND_MASTER equ 0x4 ; Enable bus mastering |
296 | PCI_COMMAND_MASTER equ 0x4 ; Enable bus mastering |
297 | PCI_LATENCY_TIMER equ 0x0d ; 8 bits |
297 | PCI_LATENCY_TIMER equ 0x0d ; 8 bits |
298 | PCI_COMMAND_SPECIAL equ 0x8 ; Enable response to special cycles |
298 | PCI_COMMAND_SPECIAL equ 0x8 ; Enable response to special cycles |
299 | PCI_COMMAND_INVALIDATE equ 0x10 ; Use memory write and invalidate |
299 | PCI_COMMAND_INVALIDATE equ 0x10 ; Use memory write and invalidate |
300 | PCI_COMMAND_VGA_PALETTE equ 0x20 ; Enable palette snooping |
300 | PCI_COMMAND_VGA_PALETTE equ 0x20 ; Enable palette snooping |
301 | PCI_COMMAND_PARITY equ 0x40 ; Enable parity checking |
301 | PCI_COMMAND_PARITY equ 0x40 ; Enable parity checking |
302 | PCI_COMMAND_WAIT equ 0x80 ; Enable address/data stepping |
302 | PCI_COMMAND_WAIT equ 0x80 ; Enable address/data stepping |
303 | PCI_COMMAND_SERR equ 0x100 ; Enable SERR |
303 | PCI_COMMAND_SERR equ 0x100 ; Enable SERR |
Line 304... | Line 304... | ||
304 | PCI_COMMAND_FAST_BACK equ 0x200 ; Enable back-to-back writes |
304 | PCI_COMMAND_FAST_BACK equ 0x200 ; Enable back-to-back writes |
305 | 305 | ||
306 | struc rtl8169_TxDesc { |
306 | struc rtl8169_TxDesc { |
307 | .status dd ? |
307 | .status dd ? |
Line 346... | Line 346... | ||
346 | ; part of this buffer |
346 | ; part of this buffer |
347 | align 256 |
347 | align 256 |
348 | rtl8169_rxb rb NUM_RX_DESC * RX_BUF_SIZE |
348 | rtl8169_rxb rb NUM_RX_DESC * RX_BUF_SIZE |
Line 349... | Line 349... | ||
349 | 349 | ||
350 | rtl8169_tpc: |
350 | rtl8169_tpc: |
351 | .mmio_addr dd ? ; memory map physical address |
351 | .mmio_addr dd ? ; memory map physical address |
352 | .chipset dd ? |
352 | .chipset dd ? |
353 | .pcfg dd ? |
353 | .pcfg dd ? |
354 | .mcfg dd ? |
354 | .mcfg dd ? |
355 | .cur_rx dd ? ; Index into the Rx descriptor buffer of next Rx pkt |
355 | .cur_rx dd ? ; Index into the Rx descriptor buffer of next Rx pkt |
356 | .cur_tx dd ? ; Index into the Tx descriptor buffer of next Rx pkt |
356 | .cur_tx dd ? ; Index into the Tx descriptor buffer of next Rx pkt |
357 | .TxDescArrays dd ? ; Index of Tx Descriptor buffer |
357 | .TxDescArrays dd ? ; Index of Tx Descriptor buffer |
358 | .RxDescArrays dd ? ; Index of Rx Descriptor buffer |
358 | .RxDescArrays dd ? ; Index of Rx Descriptor buffer |
359 | .TxDescArray dd ? ; Index of 256-alignment Tx Descriptor buffer |
359 | .TxDescArray dd ? ; Index of 256-alignment Tx Descriptor buffer |
360 | .RxDescArray dd ? ; Index of 256-alignment Rx Descriptor buffer |
360 | .RxDescArray dd ? ; Index of 256-alignment Rx Descriptor buffer |
361 | .RxBufferRing rd NUM_RX_DESC ; Index of Rx Buffer array |
361 | .RxBufferRing rd NUM_RX_DESC ; Index of Rx Buffer array |
Line 362... | Line 362... | ||
362 | .Tx_skbuff rd NUM_TX_DESC |
362 | .Tx_skbuff rd NUM_TX_DESC |
Line 363... | Line 363... | ||
363 | 363 | ||
364 | end virtual |
364 | end virtual |
Line 381... | Line 381... | ||
381 | MCFG_METHOD_05, 0xff7e1880, \ ; RTL8169sc/8110sc |
381 | MCFG_METHOD_05, 0xff7e1880, \ ; RTL8169sc/8110sc |
382 | MCFG_METHOD_11, 0xff7e1880, \ ; RTL8168b/8111b // PCI-E |
382 | MCFG_METHOD_11, 0xff7e1880, \ ; RTL8168b/8111b // PCI-E |
383 | MCFG_METHOD_12, 0xff7e1880, \ ; RTL8168b/8111b // PCI-E |
383 | MCFG_METHOD_12, 0xff7e1880, \ ; RTL8168b/8111b // PCI-E |
384 | MCFG_METHOD_13, 0xff7e1880, \ ; RTL8101e // PCI-E 8139 |
384 | MCFG_METHOD_13, 0xff7e1880, \ ; RTL8101e // PCI-E 8139 |
385 | MCFG_METHOD_14, 0xff7e1880, \ ; RTL8100e // PCI-E 8139 |
385 | MCFG_METHOD_14, 0xff7e1880, \ ; RTL8100e // PCI-E 8139 |
386 | MCFG_METHOD_15, 0xff7e1880 ; RTL8100e // PCI-E 8139 |
386 | MCFG_METHOD_15, 0xff7e1880 ; RTL8100e // PCI-E 8139 |
Line 387... | Line 387... | ||
387 | 387 | ||
388 | mac_info dd \ |
388 | mac_info dd \ |
389 | 0x38800000, MCFG_METHOD_15, \ |
389 | 0x38800000, MCFG_METHOD_15, \ |
390 | 0x38000000, MCFG_METHOD_12, \ |
390 | 0x38000000, MCFG_METHOD_12, \ |
Line 393... | Line 393... | ||
393 | 0x30000000, MCFG_METHOD_11, \ |
393 | 0x30000000, MCFG_METHOD_11, \ |
394 | 0x18000000, MCFG_METHOD_05, \ |
394 | 0x18000000, MCFG_METHOD_05, \ |
395 | 0x10000000, MCFG_METHOD_04, \ |
395 | 0x10000000, MCFG_METHOD_04, \ |
396 | 0x04000000, MCFG_METHOD_03, \ |
396 | 0x04000000, MCFG_METHOD_03, \ |
397 | 0x00800000, MCFG_METHOD_02, \ |
397 | 0x00800000, MCFG_METHOD_02, \ |
398 | 0x00000000, MCFG_METHOD_01 ; catch-all |
398 | 0x00000000, MCFG_METHOD_01 ; catch-all |
Line 399... | Line 399... | ||
399 | 399 | ||
Line 400... | Line 400... | ||
400 | endg |
400 | endg |
401 | 401 | ||
402 | PCI_COMMAND_IO equ 0x1 ; Enable response in I/O space |
402 | PCI_COMMAND_IO equ 0x1 ; Enable response in I/O space |
403 | PCI_COMMAND_MEM equ 0x2 ; Enable response in mem space |
403 | PCI_COMMAND_MEM equ 0x2 ; Enable response in mem space |
404 | PCI_COMMAND_MASTER equ 0x4 ; Enable bus mastering |
404 | PCI_COMMAND_MASTER equ 0x4 ; Enable bus mastering |
405 | PCI_LATENCY_TIMER equ 0x0d ; 8 bits |
405 | PCI_LATENCY_TIMER equ 0x0d ; 8 bits |
406 | PCI_COMMAND_SPECIAL equ 0x8 ; Enable response to special cycles |
406 | PCI_COMMAND_SPECIAL equ 0x8 ; Enable response to special cycles |
407 | PCI_COMMAND_INVALIDATE equ 0x10 ; Use memory write and invalidate |
407 | PCI_COMMAND_INVALIDATE equ 0x10 ; Use memory write and invalidate |
408 | PCI_COMMAND_VGA_PALETTE equ 0x20 ; Enable palette snooping |
408 | PCI_COMMAND_VGA_PALETTE equ 0x20 ; Enable palette snooping |
409 | PCI_COMMAND_PARITY equ 0x40 ; Enable parity checking |
409 | PCI_COMMAND_PARITY equ 0x40 ; Enable parity checking |
410 | PCI_COMMAND_WAIT equ 0x80 ; Enable address/data stepping |
410 | PCI_COMMAND_WAIT equ 0x80 ; Enable address/data stepping |
411 | PCI_COMMAND_SERR equ 0x100 ; Enable SERR |
411 | PCI_COMMAND_SERR equ 0x100 ; Enable SERR |
412 | PCI_COMMAND_FAST_BACK equ 0x200 ; Enable back-to-back writes |
412 | PCI_COMMAND_FAST_BACK equ 0x200 ; Enable back-to-back writes |
413 | 413 | ||
414 | PCI_VENDOR_ID equ 0x00 ; 16 bits |
414 | PCI_VENDOR_ID equ 0x00 ; 16 bits |
415 | PCI_DEVICE_ID equ 0x02 ; 16 bits |
415 | PCI_DEVICE_ID equ 0x02 ; 16 bits |
416 | PCI_COMMAND equ 0x04 ; 16 bits |
416 | PCI_COMMAND equ 0x04 ; 16 bits |
417 | 417 | ||
418 | PCI_BASE_ADDRESS_0 equ 0x10 ; 32 bits |
418 | PCI_BASE_ADDRESS_0 equ 0x10 ; 32 bits |
419 | PCI_BASE_ADDRESS_1 equ 0x14 ; 32 bits |
419 | PCI_BASE_ADDRESS_1 equ 0x14 ; 32 bits |
420 | PCI_BASE_ADDRESS_2 equ 0x18 ; 32 bits |
420 | PCI_BASE_ADDRESS_2 equ 0x18 ; 32 bits |
421 | PCI_BASE_ADDRESS_3 equ 0x1c ; 32 bits |
421 | PCI_BASE_ADDRESS_3 equ 0x1c ; 32 bits |
Line 422... | Line 422... | ||
422 | PCI_BASE_ADDRESS_4 equ 0x20 ; 32 bits |
422 | PCI_BASE_ADDRESS_4 equ 0x20 ; 32 bits |
423 | PCI_BASE_ADDRESS_5 equ 0x24 ; 32 bits |
423 | PCI_BASE_ADDRESS_5 equ 0x24 ; 32 bits |
424 | 424 | ||
425 | PCI_BASE_ADDRESS_MEM_TYPE_MASK equ 0x06 |
425 | PCI_BASE_ADDRESS_MEM_TYPE_MASK equ 0x06 |
Line 426... | Line 426... | ||
426 | PCI_BASE_ADDRESS_MEM_TYPE_32 equ 0x00 ; 32 bit address |
426 | PCI_BASE_ADDRESS_MEM_TYPE_32 equ 0x00 ; 32 bit address |
427 | PCI_BASE_ADDRESS_MEM_TYPE_1M equ 0x02 ; Below 1M [obsolete] |
427 | PCI_BASE_ADDRESS_MEM_TYPE_1M equ 0x02 ; Below 1M [obsolete] |
428 | PCI_BASE_ADDRESS_MEM_TYPE_64 equ 0x04 ; 64 bit address |
428 | PCI_BASE_ADDRESS_MEM_TYPE_64 equ 0x04 ; 64 bit address |
429 | 429 | ||
Line 430... | Line 430... | ||
430 | PCI_BASE_ADDRESS_IO_MASK equ (not 0x03) |
430 | PCI_BASE_ADDRESS_IO_MASK equ (not 0x03) |
431 | PCI_BASE_ADDRESS_MEM_MASK equ (not 0x0f) |
431 | PCI_BASE_ADDRESS_MEM_MASK equ (not 0x0f) |
432 | PCI_BASE_ADDRESS_SPACE_IO equ 0x01 |
432 | PCI_BASE_ADDRESS_SPACE_IO equ 0x01 |
433 | PCI_ROM_ADDRESS equ 0x30 ; 32 bits |
433 | PCI_ROM_ADDRESS equ 0x30 ; 32 bits |
434 | 434 | ||
435 | proc CONFIG_CMD,where:byte |
435 | proc CONFIG_CMD,where:byte |
436 | movzx eax,byte[pci_bus] |
436 | movzx eax, byte[pci_bus] |
437 | shl eax,8 |
437 | shl eax, 8 |
438 | mov al,[pci_dev] |
438 | mov al, [pci_dev] |
439 | shl eax,8 |
439 | shl eax, 8 |
Line 440... | Line 440... | ||
440 | mov al,[where] |
440 | mov al, [where] |
441 | and al,not 3 |
441 | and al, not 3 |
442 | or eax,0x80000000 |
442 | or eax, 0x80000000 |
443 | ret |
443 | ret |
444 | endp |
444 | endp |
445 | 445 | ||
446 | proc pci_read_config_byte,where:dword |
446 | proc pci_read_config_byte,where:dword |
447 | push edx |
447 | push edx |
448 | stdcall CONFIG_CMD,[where] |
448 | stdcall CONFIG_CMD, [where] |
449 | mov dx,0xCF8 |
449 | mov dx, 0xCF8 |
450 | out dx,eax |
450 | out dx, eax |
451 | mov edx,[where] |
451 | mov edx, [where] |
Line 452... | Line 452... | ||
452 | and edx,3 |
452 | and edx, 3 |
453 | add edx,0xCFC |
453 | add edx, 0xCFC |
454 | in al,dx |
454 | in al, dx |
455 | pop edx |
455 | pop edx |
456 | ret |
456 | ret |
457 | endp |
457 | endp |
458 | 458 | ||
459 | proc pci_read_config_word,where:dword |
459 | proc pci_read_config_word,where:dword |
460 | push edx |
460 | push edx |
461 | stdcall CONFIG_CMD,[where] |
461 | stdcall CONFIG_CMD, [where] |
462 | mov dx,0xCF8 |
462 | mov dx, 0xCF8 |
463 | out dx,eax |
463 | out dx, eax |
Line 464... | Line 464... | ||
464 | mov edx,[where] |
464 | mov edx, [where] |
465 | and edx,2 |
465 | and edx, 2 |
466 | add edx,0xCFC |
466 | add edx, 0xCFC |
467 | in ax,dx |
467 | in ax, dx |
468 | pop edx |
468 | pop edx |
469 | ret |
469 | ret |
470 | endp |
470 | endp |
471 | 471 | ||
472 | proc pci_read_config_dword,where:dword |
472 | proc pci_read_config_dword,where:dword |
473 | push edx |
473 | push edx |
Line 474... | Line 474... | ||
474 | stdcall CONFIG_CMD,[where] |
474 | stdcall CONFIG_CMD, [where] |
475 | mov edx,0xCF8 |
475 | mov edx, 0xCF8 |
476 | out dx,eax |
476 | out dx, eax |
477 | mov edx,0xCFC |
477 | mov edx, 0xCFC |
478 | in eax,dx |
478 | in eax, dx |
479 | pop edx |
479 | pop edx |
480 | ret |
480 | ret |
481 | endp |
481 | endp |
482 | 482 | ||
483 | proc pci_write_config_byte,where:dword,value:byte |
483 | proc pci_write_config_byte,where:dword,value:byte |
484 | push edx |
484 | push edx |
485 | stdcall CONFIG_CMD,[where] |
485 | stdcall CONFIG_CMD, [where] |
486 | mov dx,0xCF8 |
486 | mov dx, 0xCF8 |
Line 487... | Line 487... | ||
487 | out dx,eax |
487 | out dx, eax |
488 | mov edx,[where] |
488 | mov edx, [where] |
489 | and edx,3 |
489 | and edx, 3 |
490 | add edx,0xCFC |
490 | add edx, 0xCFC |
491 | mov al,[value] |
491 | mov al, [value] |
492 | out dx,al |
492 | out dx, al |
493 | pop edx |
493 | pop edx |
494 | ret |
494 | ret |
495 | endp |
495 | endp |
496 | 496 | ||
497 | proc pci_write_config_word,where:dword,value:word |
497 | proc pci_write_config_word,where:dword,value:word |
498 | push edx |
498 | push edx |
499 | stdcall CONFIG_CMD,[where] |
499 | stdcall CONFIG_CMD, [where] |
Line 500... | Line 500... | ||
500 | mov dx,0xCF8 |
500 | mov dx, 0xCF8 |
501 | out dx,eax |
501 | out dx, eax |
502 | mov edx,[where] |
502 | mov edx, [where] |
503 | and edx,2 |
503 | and edx, 2 |
504 | add edx,0xCFC |
504 | add edx, 0xCFC |
505 | mov ax,[value] |
505 | mov ax, [value] |
506 | out dx,ax |
506 | out dx, ax |
507 | pop edx |
507 | pop edx |
508 | ret |
508 | ret |
509 | endp |
509 | endp |
510 | 510 | ||
Line 511... | Line 511... | ||
511 | proc pci_write_config_dword,where:dword,value:dword |
511 | proc pci_write_config_dword,where:dword,value:dword |
512 | push edx |
512 | push edx |
513 | stdcall CONFIG_CMD,[where] |
513 | stdcall CONFIG_CMD, [where] |
Line 514... | Line 514... | ||
514 | mov edx,0xCF8 |
514 | mov edx, 0xCF8 |
Line 515... | Line 515... | ||
515 | out dx,eax |
515 | out dx, eax |
516 | mov edx,0xCFC |
516 | mov edx, 0xCFC |
517 | mov eax,[value] |
517 | mov eax, [value] |
518 | out dx,eax |
518 | out dx, eax |
519 | pop edx |
519 | pop edx |
520 | ret |
520 | ret |
521 | endp |
521 | endp |
522 | 522 | ||
523 | ; Set device to be a busmaster in case BIOS neglected to do so. |
523 | ; Set device to be a busmaster in case BIOS neglected to do so. |
524 | ; Also adjust PCI latency timer to a reasonable value, 32. |
524 | ; Also adjust PCI latency timer to a reasonable value, 32. |
525 | proc adjust_pci_device |
525 | proc adjust_pci_device |
526 | 526 | ||
527 | ; DEBUGF 1,"K : adjust_pci_device\n" |
527 | ; DEBUGF 1,"K : adjust_pci_device\n" |
528 | 528 | ||
529 | stdcall pci_read_config_word,PCI_COMMAND |
529 | stdcall pci_read_config_word, PCI_COMMAND |
530 | mov bx,ax |
530 | mov bx, ax |
Line 531... | Line 531... | ||
531 | or bx,PCI_COMMAND_MASTER or PCI_COMMAND_IO |
531 | or bx, PCI_COMMAND_MASTER or PCI_COMMAND_IO |
532 | cmp ax,bx |
532 | cmp ax, bx |
533 | je @f |
533 | je @f |
534 | ; DEBUGF 1,"K : adjust_pci_device: The PCI BIOS has not enabled this device!\nK : Updating PCI command %x->%x. pci_bus %x pci_device_fn %x\n",ax,bx,[pci_bus]:2,[pci_dev]:2 |
534 | ; DEBUGF 1,"K : adjust_pci_device: The PCI BIOS has not enabled this device!\nK : Updating PCI command %x->%x. pci_bus %x pci_device_fn %x\n",ax,bx,[pci_bus]:2,[pci_dev]:2 |
535 | stdcall pci_write_config_word,PCI_COMMAND,ebx |
535 | stdcall pci_write_config_word, PCI_COMMAND, ebx |
536 | @@: |
536 | @@: |
537 | stdcall pci_read_config_byte,PCI_LATENCY_TIMER |
537 | stdcall pci_read_config_byte, PCI_LATENCY_TIMER |
- | 538 | cmp al, 32 |
|
538 | cmp al,32 |
539 | jae @f |
539 | jae @f |
540 | ; DEBUGF 1,"K : adjust_pci_device: PCI latency timer (CFLT) is unreasonably low at %d.\nK : Setting to 32 clocks.\n",al |
540 | ; DEBUGF 1,"K : adjust_pci_device: PCI latency timer (CFLT) is unreasonably low at %d.\nK : Setting to 32 clocks.\n",al |
541 | stdcall pci_write_config_byte, PCI_LATENCY_TIMER, 32 |
541 | stdcall pci_write_config_byte,PCI_LATENCY_TIMER,32 |
542 | @@: |
542 | @@: |
543 | ret |
543 | ret |
544 | endp |
544 | endp |
545 | |
545 | 546 | ; Find the start of a pci resource |
|
546 | ; Find the start of a pci resource |
547 | proc pci_bar_start,index:dword |
547 | proc pci_bar_start,index:dword |
548 | stdcall pci_read_config_dword, [index] |
548 | stdcall pci_read_config_dword,[index] |
549 | test eax, PCI_BASE_ADDRESS_SPACE_IO |
549 | test eax,PCI_BASE_ADDRESS_SPACE_IO |
550 | jz @f |
550 | jz @f |
551 | and eax, PCI_BASE_ADDRESS_IO_MASK |
551 | and eax,PCI_BASE_ADDRESS_IO_MASK |
552 | jmp .exit |
552 | jmp .exit |
553 | @@: |
553 | @@: push eax |
554 | push eax |
554 | and eax,PCI_BASE_ADDRESS_MEM_TYPE_MASK |
555 | and eax, PCI_BASE_ADDRESS_MEM_TYPE_MASK |
555 | cmp eax,PCI_BASE_ADDRESS_MEM_TYPE_64 |
556 | cmp eax, PCI_BASE_ADDRESS_MEM_TYPE_64 |
556 | jne .not64 |
557 | jne .not64 |
Line 557... | Line 558... | ||
557 | mov eax,[index] |
558 | mov eax, [index] |
Line 558... | Line 559... | ||
558 | add eax,4 |
559 | add eax, 4 |
Line 559... | Line 560... | ||
559 | stdcall pci_read_config_dword,eax |
560 | stdcall pci_read_config_dword, eax |
- | 561 | or eax, eax |
|
- | 562 | jz .not64 |
|
- | 563 | ; DEBUGF 1,"K : pci_bar_start: Unhandled 64bit BAR\n" |
|
- | 564 | add esp, 4 |
|
- | 565 | or eax, -1 |
|
Line 560... | Line -... | ||
560 | or eax,eax |
- | |
561 | jz .not64 |
- | |
562 | ; DEBUGF 1,"K : pci_bar_start: Unhandled 64bit BAR\n" |
- | |
563 | add esp,4 |
- | |
564 | or eax,-1 |
- | |
565 | ret |
566 | ret |
566 | .not64: |
567 | .not64: |
- | 568 | pop eax |
|
567 | pop eax |
569 | and eax, PCI_BASE_ADDRESS_MEM_MASK |
568 | and eax,PCI_BASE_ADDRESS_MEM_MASK |
570 | .exit: |
569 | .exit: |
571 | ret |
570 | ret |
572 | endp |
571 | endp |
573 | |
572 | 574 | proc rtl8169_init_board |
|
573 | proc rtl8169_init_board |
575 | |
574 | 576 | ; DEBUGF 1,"K : rtl8169_init_board\n" |
|
575 | ; DEBUGF 1,"K : rtl8169_init_board\n" |
577 | |
576 | 578 | call adjust_pci_device |
|
577 | call adjust_pci_device |
579 | |
- | 580 | stdcall pci_bar_start, PCI_BASE_ADDRESS_0 |
|
578 | 581 | mov [rtl8169_tpc.mmio_addr], eax |
|
579 | stdcall pci_bar_start,PCI_BASE_ADDRESS_0 |
582 | ; Soft reset the chip |
580 | mov [rtl8169_tpc.mmio_addr],eax |
583 | RTL_W8 RTL8169_REG_ChipCmd,RTL8169_CMD_Reset |
581 | ; Soft reset the chip |
584 | |
582 | RTL_W8 RTL8169_REG_ChipCmd,RTL8169_CMD_Reset |
585 | ; Check that the chip has finished the reset |
583 | 586 | mov ecx, 1000 |
|
584 | ; Check that the chip has finished the reset |
587 | @@: |
585 | mov ecx,1000 |
588 | RTL_R8 RTL8169_REG_ChipCmd |
586 | @@: RTL_R8 RTL8169_REG_ChipCmd |
589 | test al, RTL8169_CMD_Reset |
587 | test al,RTL8169_CMD_Reset |
590 | jz @f |
588 | jz @f |
591 | stdcall udelay, 10 |
589 | stdcall udelay,10 |
592 | loop @b |
590 | loop @b |
593 | @@: |
591 | @@: |
594 | ; identify config method |
592 | ; identify config method |
595 | RTL_R32 RTL8169_REG_TxConfig |
- | 596 | and eax, 0x7c800000 |
|
593 | RTL_R32 RTL8169_REG_TxConfig |
597 | ; DEBUGF 1,"K : rtl8169_init_board: TxConfig & 0x7c800000 = 0x%x\n",eax |
594 | and eax,0x7c800000 |
598 | mov esi, mac_info-8 |
595 | ; DEBUGF 1,"K : rtl8169_init_board: TxConfig & 0x7c800000 = 0x%x\n",eax |
599 | @@: |
596 | mov esi,mac_info-8 |
600 | add esi, 8 |
Line 597... | Line 601... | ||
597 | @@: add esi,8 |
601 | mov ecx, eax |
598 | mov ecx,eax |
602 | and ecx, [esi] |
599 | and ecx,[esi] |
603 | cmp ecx, [esi] |
- | 604 | jne @b |
|
600 | cmp ecx,[esi] |
605 | mov eax, [esi+4] |
601 | jne @b |
606 | mov [rtl8169_tpc.mcfg], eax |
602 | mov eax,[esi+4] |
607 | |
603 | mov [rtl8169_tpc.mcfg],eax |
608 | mov [rtl8169_tpc.pcfg], PCFG_METHOD_3 |
604 | 609 | stdcall RTL8169_READ_GMII_REG, 3 |
|
605 | mov [rtl8169_tpc.pcfg],PCFG_METHOD_3 |
610 | and al, 0x0f |
606 | stdcall RTL8169_READ_GMII_REG,3 |
611 | or al, al |
607 | and al,0x0f |
612 | jnz @f |
608 | or al,al |
613 | mov [rtl8169_tpc.pcfg], PCFG_METHOD_1 |
609 | jnz @f |
614 | jmp .pconf |
610 | mov [rtl8169_tpc.pcfg],PCFG_METHOD_1 |
615 | @@: |
Line 611... | Line 616... | ||
611 | jmp .pconf |
616 | dec al |
Line 612... | Line 617... | ||
612 | @@: dec al |
617 | jnz .pconf |
613 | jnz .pconf |
618 | mov [rtl8169_tpc.pcfg], PCFG_METHOD_2 |
614 | mov [rtl8169_tpc.pcfg],PCFG_METHOD_2 |
619 | .pconf: |
Line 615... | Line 620... | ||
615 | .pconf: |
620 | |
616 | 621 | ; identify chip attached to board |
|
617 | ; identify chip attached to board |
622 | mov ecx, 10 |
618 | mov ecx,10 |
623 | mov eax, [rtl8169_tpc.mcfg] |
Line 619... | Line 624... | ||
619 | mov eax,[rtl8169_tpc.mcfg] |
624 | @@: |
Line 620... | Line 625... | ||
620 | @@: dec ecx |
625 | dec ecx |
Line 621... | Line 626... | ||
621 | js @f |
626 | js @f |
Line 622... | Line 627... | ||
622 | cmp eax,[rtl_chip_info+ecx*8] |
627 | cmp eax, [rtl_chip_info+ecx*8] |
623 | jne @b |
628 | jne @b |
624 | mov [rtl8169_tpc.chipset],ecx |
629 | mov [rtl8169_tpc.chipset], ecx |
625 | jmp .match |
630 | jmp .match |
626 | @@: |
631 | @@: |
627 | ; if unknown chip, assume array element #0, original RTL-8169 in this case |
632 | ; if unknown chip, assume array element #0, original RTL-8169 in this case |
628 | ; DEBUGF 1,"K : rtl8169_init_board: PCI device: unknown chip version, assuming RTL-8169\n" |
633 | ; DEBUGF 1,"K : rtl8169_init_board: PCI device: unknown chip version, assuming RTL-8169\n" |
629 | RTL_R32 RTL8169_REG_TxConfig |
634 | RTL_R32 RTL8169_REG_TxConfig |
630 | ; DEBUGF 1,"K : rtl8169_init_board: PCI device: TxConfig = 0x%x\n",eax |
635 | ; DEBUGF 1,"K : rtl8169_init_board: PCI device: TxConfig = 0x%x\n",eax |
631 | 636 | ||
632 | mov [rtl8169_tpc.chipset],0 |
637 | mov [rtl8169_tpc.chipset], 0 |
633 | 638 | ||
634 | xor eax,eax |
639 | xor eax, eax |
635 | inc eax |
640 | inc eax |
636 | ret |
641 | ret |
- | 642 | ||
637 | 643 | .match: |
|
638 | .match: |
644 | xor eax, eax |
639 | xor eax,eax |
645 | ret |
640 | ret |
646 | endp |
641 | endp |
647 | |
642 | 648 | proc rtl8169_hw_PHY_config |
|
643 | proc rtl8169_hw_PHY_config |
649 | |
644 | 650 | ; DEBUGF 1,"K : rtl8169_hw_PHY_config: priv.mcfg=%d, priv.pcfg=%d\n",[rtl8169_tpc.mcfg],[rtl8169_tpc.pcfg] |
|
645 | ; DEBUGF 1,"K : rtl8169_hw_PHY_config: priv.mcfg=%d, priv.pcfg=%d\n",[rtl8169_tpc.mcfg],[rtl8169_tpc.pcfg] |
651 | |
646 | 652 | ; DBG_PRINT("priv->mcfg=%d, priv->pcfg=%d\n", tpc->mcfg, tpc->pcfg); |
|
647 | ; DBG_PRINT("priv->mcfg=%d, priv->pcfg=%d\n", tpc->mcfg, tpc->pcfg); |
653 | |
648 | 654 | cmp [rtl8169_tpc.mcfg], MCFG_METHOD_04 |
|
649 | cmp [rtl8169_tpc.mcfg],MCFG_METHOD_04 |
655 | jne .not_4 |
650 | jne .not_4 |
656 | ; stdcall RTL8169_WRITE_GMII_REG,0x1F,0x0001 |
651 | ; stdcall RTL8169_WRITE_GMII_REG,0x1F,0x0001 |
657 | ; stdcall RTL8169_WRITE_GMII_REG,0x1b,0x841e |
652 | ; stdcall RTL8169_WRITE_GMII_REG,0x1b,0x841e |
658 | ; stdcall RTL8169_WRITE_GMII_REG,0x0e,0x7bfb |
653 | ; stdcall RTL8169_WRITE_GMII_REG,0x0e,0x7bfb |
659 | ; stdcall RTL8169_WRITE_GMII_REG,0x09,0x273a |
654 | ; stdcall RTL8169_WRITE_GMII_REG,0x09,0x273a |
660 | stdcall RTL8169_WRITE_GMII_REG, 0x1F, 0x0002 |
655 | stdcall RTL8169_WRITE_GMII_REG,0x1F,0x0002 |
661 | stdcall RTL8169_WRITE_GMII_REG, 0x01, 0x90D0 |
656 | stdcall RTL8169_WRITE_GMII_REG,0x01,0x90D0 |
662 | stdcall RTL8169_WRITE_GMII_REG, 0x1F, 0x0000 |
657 | stdcall RTL8169_WRITE_GMII_REG,0x1F,0x0000 |
663 | jmp .exit |
658 | jmp .exit |
664 | .not_4: |
659 | .not_4: |
665 | cmp [rtl8169_tpc.mcfg], MCFG_METHOD_02 |
660 | cmp [rtl8169_tpc.mcfg],MCFG_METHOD_02 |
666 | je @f |
661 | je @f |
667 | cmp [rtl8169_tpc.mcfg], MCFG_METHOD_03 |
662 | cmp [rtl8169_tpc.mcfg],MCFG_METHOD_03 |
668 | jne .not_2_or_3 |
663 | jne .not_2_or_3 |
669 | @@: |
664 | @@: stdcall RTL8169_WRITE_GMII_REG,0x1F,0x0001 |
670 | stdcall RTL8169_WRITE_GMII_REG, 0x1F, 0x0001 |
665 | stdcall RTL8169_WRITE_GMII_REG,0x15,0x1000 |
671 | stdcall RTL8169_WRITE_GMII_REG, 0x15, 0x1000 |
666 | stdcall RTL8169_WRITE_GMII_REG,0x18,0x65C7 |
672 | stdcall RTL8169_WRITE_GMII_REG, 0x18, 0x65C7 |
667 | stdcall RTL8169_WRITE_GMII_REG,0x04,0x0000 |
673 | stdcall RTL8169_WRITE_GMII_REG, 0x04, 0x0000 |
668 | stdcall RTL8169_WRITE_GMII_REG,0x03,0x00A1 |
674 | stdcall RTL8169_WRITE_GMII_REG, 0x03, 0x00A1 |
669 | stdcall RTL8169_WRITE_GMII_REG,0x02,0x0008 |
675 | stdcall RTL8169_WRITE_GMII_REG, 0x02, 0x0008 |
670 | stdcall RTL8169_WRITE_GMII_REG,0x01,0x1020 |
676 | stdcall RTL8169_WRITE_GMII_REG, 0x01, 0x1020 |
671 | stdcall RTL8169_WRITE_GMII_REG,0x00,0x1000 |
677 | stdcall RTL8169_WRITE_GMII_REG, 0x00, 0x1000 |
672 | stdcall RTL8169_WRITE_GMII_REG,0x04,0x0800 |
678 | stdcall RTL8169_WRITE_GMII_REG, 0x04, 0x0800 |
673 | stdcall RTL8169_WRITE_GMII_REG,0x04,0x0000 |
679 | stdcall RTL8169_WRITE_GMII_REG, 0x04, 0x0000 |
674 | stdcall RTL8169_WRITE_GMII_REG,0x04,0x7000 |
680 | stdcall RTL8169_WRITE_GMII_REG, 0x04, 0x7000 |
675 | stdcall RTL8169_WRITE_GMII_REG,0x03,0xFF41 |
681 | stdcall RTL8169_WRITE_GMII_REG, 0x03, 0xFF41 |
676 | stdcall RTL8169_WRITE_GMII_REG,0x02,0xDE60 |
682 | stdcall RTL8169_WRITE_GMII_REG, 0x02, 0xDE60 |
677 | stdcall RTL8169_WRITE_GMII_REG,0x01,0x0140 |
683 | stdcall RTL8169_WRITE_GMII_REG, 0x01, 0x0140 |
678 | stdcall RTL8169_WRITE_GMII_REG,0x00,0x0077 |
684 | stdcall RTL8169_WRITE_GMII_REG, 0x00, 0x0077 |
679 | stdcall RTL8169_WRITE_GMII_REG,0x04,0x7800 |
685 | stdcall RTL8169_WRITE_GMII_REG, 0x04, 0x7800 |
680 | stdcall RTL8169_WRITE_GMII_REG,0x04,0x7000 |
686 | stdcall RTL8169_WRITE_GMII_REG, 0x04, 0x7000 |
681 | stdcall RTL8169_WRITE_GMII_REG,0x04,0xA000 |
687 | stdcall RTL8169_WRITE_GMII_REG, 0x04, 0xA000 |
682 | stdcall RTL8169_WRITE_GMII_REG,0x03,0xDF01 |
688 | stdcall RTL8169_WRITE_GMII_REG, 0x03, 0xDF01 |
683 | stdcall RTL8169_WRITE_GMII_REG,0x02,0xDF20 |
689 | stdcall RTL8169_WRITE_GMII_REG, 0x02, 0xDF20 |
684 | stdcall RTL8169_WRITE_GMII_REG,0x01,0xFF95 |
690 | stdcall RTL8169_WRITE_GMII_REG, 0x01, 0xFF95 |
Line 685... | Line 691... | ||
685 | stdcall RTL8169_WRITE_GMII_REG,0x00,0xFA00 |
691 | stdcall RTL8169_WRITE_GMII_REG, 0x00, 0xFA00 |
686 | stdcall RTL8169_WRITE_GMII_REG,0x04,0xA800 |
692 | stdcall RTL8169_WRITE_GMII_REG, 0x04, 0xA800 |
687 | stdcall RTL8169_WRITE_GMII_REG,0x04,0xA000 |
693 | stdcall RTL8169_WRITE_GMII_REG, 0x04, 0xA000 |
Line 688... | Line 694... | ||
688 | stdcall RTL8169_WRITE_GMII_REG,0x04,0xB000 |
694 | stdcall RTL8169_WRITE_GMII_REG, 0x04, 0xB000 |
Line 689... | Line 695... | ||
689 | stdcall RTL8169_WRITE_GMII_REG,0x03,0xFF41 |
695 | stdcall RTL8169_WRITE_GMII_REG, 0x03, 0xFF41 |
Line 690... | Line 696... | ||
690 | stdcall RTL8169_WRITE_GMII_REG,0x02,0xDE20 |
696 | stdcall RTL8169_WRITE_GMII_REG, 0x02, 0xDE20 |
691 | stdcall RTL8169_WRITE_GMII_REG,0x01,0x0140 |
697 | stdcall RTL8169_WRITE_GMII_REG, 0x01, 0x0140 |
692 | stdcall RTL8169_WRITE_GMII_REG,0x00,0x00BB |
698 | stdcall RTL8169_WRITE_GMII_REG, 0x00, 0x00BB |
693 | stdcall RTL8169_WRITE_GMII_REG,0x04,0xB800 |
699 | stdcall RTL8169_WRITE_GMII_REG, 0x04, 0xB800 |
694 | stdcall RTL8169_WRITE_GMII_REG,0x04,0xB000 |
700 | stdcall RTL8169_WRITE_GMII_REG, 0x04, 0xB000 |
695 | stdcall RTL8169_WRITE_GMII_REG,0x04,0xF000 |
701 | stdcall RTL8169_WRITE_GMII_REG, 0x04, 0xF000 |
696 | stdcall RTL8169_WRITE_GMII_REG,0x03,0xDF01 |
702 | stdcall RTL8169_WRITE_GMII_REG, 0x03, 0xDF01 |
697 | stdcall RTL8169_WRITE_GMII_REG,0x02,0xDF20 |
703 | stdcall RTL8169_WRITE_GMII_REG, 0x02, 0xDF20 |
698 | stdcall RTL8169_WRITE_GMII_REG,0x01,0xFF95 |
704 | stdcall RTL8169_WRITE_GMII_REG, 0x01, 0xFF95 |
- | 705 | stdcall RTL8169_WRITE_GMII_REG, 0x00, 0xBF00 |
|
699 | stdcall RTL8169_WRITE_GMII_REG,0x00,0xBF00 |
706 | stdcall RTL8169_WRITE_GMII_REG, 0x04, 0xF800 |
700 | stdcall RTL8169_WRITE_GMII_REG,0x04,0xF800 |
707 | stdcall RTL8169_WRITE_GMII_REG, 0x04, 0xF000 |
701 | stdcall RTL8169_WRITE_GMII_REG,0x04,0xF000 |
708 | stdcall RTL8169_WRITE_GMII_REG, 0x04, 0x0000 |
702 | stdcall RTL8169_WRITE_GMII_REG,0x04,0x0000 |
709 | stdcall RTL8169_WRITE_GMII_REG, 0x1F, 0x0000 |
703 | stdcall RTL8169_WRITE_GMII_REG,0x1F,0x0000 |
710 | stdcall RTL8169_WRITE_GMII_REG, 0x0B, 0x0000 |
704 | stdcall RTL8169_WRITE_GMII_REG,0x0B,0x0000 |
711 | jmp .exit |
705 | jmp .exit |
712 | .not_2_or_3: |
706 | .not_2_or_3: |
713 | ; DBG_PRINT("tpc->mcfg=%d. Discard hw PHY config.\n", tpc->mcfg); |
Line 707... | Line 714... | ||
707 | ; DBG_PRINT("tpc->mcfg=%d. Discard hw PHY config.\n", tpc->mcfg); |
714 | ; DEBUGF 1,"K : tpc.mcfg=%d, discard hw PHY config\n",[rtl8169_tpc.mcfg] |
Line 708... | Line 715... | ||
708 | ; DEBUGF 1,"K : tpc.mcfg=%d, discard hw PHY config\n",[rtl8169_tpc.mcfg] |
715 | .exit: |
Line 709... | Line 716... | ||
709 | .exit: |
716 | ret |
710 | ret |
717 | endp |
711 | endp |
718 | |
712 | 719 | ;proc pci_write_config_byte |
|
713 | ;proc pci_write_config_byte |
720 | ; ret |
714 | ; ret |
721 | ;endp |
Line 715... | Line 722... | ||
715 | ;endp |
722 | |
716 | 723 | proc RTL8169_WRITE_GMII_REG,RegAddr:byte,value:dword |
|
- | 724 | ||
717 | proc RTL8169_WRITE_GMII_REG,RegAddr:byte,value:dword |
725 | ;;; DEBUGF 1,"K : RTL8169_WRITE_GMII_REG: 0x%x 0x%x\n",[RegAddr]:2,[value] |
718 | 726 | ||
719 | ;;; DEBUGF 1,"K : RTL8169_WRITE_GMII_REG: 0x%x 0x%x\n",[RegAddr]:2,[value] |
727 | movzx eax, [RegAddr] |
720 | 728 | shl eax, 16 |
|
721 | movzx eax,[RegAddr] |
729 | or eax, [value] |
722 | shl eax,16 |
730 | or eax, 0x80000000 |
723 | or eax,[value] |
731 | RTL_W32 RTL8169_REG_PHYAR,eax |
724 | or eax,0x80000000 |
732 | stdcall udelay, 1 ;;;1000 |
725 | RTL_W32 RTL8169_REG_PHYAR,eax |
733 | |
726 | stdcall udelay,1 ;;;1000 |
734 | mov ecx, 2000 |
727 | 735 | ; Check if the RTL8169 has completed writing to the specified MII register |
|
728 | mov ecx,2000 |
736 | @@: |
729 | ; Check if the RTL8169 has completed writing to the specified MII register |
737 | RTL_R32 RTL8169_REG_PHYAR |
730 | @@: RTL_R32 RTL8169_REG_PHYAR |
738 | test eax, 0x80000000 |
731 | test eax,0x80000000 |
739 | jz .exit |
Line 732... | Line 740... | ||
732 | jz .exit |
740 | stdcall udelay, 1 ;;;100 |
Line 733... | Line 741... | ||
733 | stdcall udelay,1 ;;;100 |
741 | loop @b |
Line 734... | Line 742... | ||
734 | loop @b |
742 | .exit: |
735 | .exit: |
743 | ret |
736 | ret |
744 | endp |
737 | endp |
745 | |
738 | 746 | proc RTL8169_READ_GMII_REG,RegAddr:byte |
|
739 | proc RTL8169_READ_GMII_REG,RegAddr:byte |
747 | |
740 | 748 | ;;; DEBUGF 1,"K : RTL8169_READ_GMII_REG: 0x%x\n",[RegAddr]:2 |
|
741 | ;;; DEBUGF 1,"K : RTL8169_READ_GMII_REG: 0x%x\n",[RegAddr]:2 |
749 | |
742 | 750 | push ecx |
|
743 | push ecx |
751 | movzx eax, [RegAddr] |
744 | movzx eax,[RegAddr] |
752 | shl eax, 16 |
745 | shl eax,16 |
753 | ; or eax,0x0 |
746 | ; or eax,0x0 |
754 | RTL_W32 RTL8169_REG_PHYAR,eax |
Line 747... | Line 755... | ||
747 | RTL_W32 RTL8169_REG_PHYAR,eax |
755 | stdcall udelay, 1 ;;;1000 |
Line 748... | Line 756... | ||
748 | stdcall udelay,1 ;;;1000 |
756 | |
Line 749... | Line 757... | ||
749 | 757 | mov ecx, 2000 |
|
750 | mov ecx,2000 |
758 | ; Check if the RTL8169 has completed retrieving data from the specified MII register |
751 | ; Check if the RTL8169 has completed retrieving data from the specified MII register |
759 | @@: |
752 | @@: RTL_R32 RTL8169_REG_PHYAR |
760 | RTL_R32 RTL8169_REG_PHYAR |
753 | test eax,0x80000000 |
761 | test eax, 0x80000000 |
754 | jnz .exit |
762 | jnz .exit |
755 | stdcall udelay,1 ;;;100 |
763 | stdcall udelay, 1 ;;;100 |
756 | loop @b |
764 | loop @b |
757 | 765 | ||
758 | or eax,-1 |
766 | or eax, -1 |
759 | pop ecx |
767 | pop ecx |
760 | ret |
768 | ret |
761 | .exit: |
769 | .exit: |
762 | RTL_R32 RTL8169_REG_PHYAR |
770 | RTL_R32 RTL8169_REG_PHYAR |
763 | and eax,0xFFFF |
771 | and eax, 0xFFFF |
- | 772 | pop ecx |
|
764 | pop ecx |
773 | ret |
765 | ret |
774 | endp |
766 | endp |
775 | |
Line 767... | Line 776... | ||
767 | 776 | proc rtl8169_set_rx_mode |
|
768 | proc rtl8169_set_rx_mode |
777 | |
769 | 778 | ; DEBUGF 1,"K : rtl8169_set_rx_mode\n" |
|
770 | ; DEBUGF 1,"K : rtl8169_set_rx_mode\n" |
779 | |
771 | 780 | ; IFF_ALLMULTI |
|
772 | ; IFF_ALLMULTI |
781 | ; Too many to filter perfectly -- accept all multicasts |
773 | ; Too many to filter perfectly -- accept all multicasts |
782 | RTL_R32 RTL8169_REG_RxConfig |
774 | RTL_R32 RTL8169_REG_RxConfig |
783 | mov ecx, [rtl8169_tpc.chipset] |
775 | mov ecx,[rtl8169_tpc.chipset] |
784 | and eax, [rtl_chip_info + ecx * 8 + 4]; RxConfigMask |
776 | and eax,[rtl_chip_info + ecx * 8 + 4] ; RxConfigMask |
785 | or eax, rtl8169_rx_config or (RTL8169_RXM_AcceptBroadcast or RTL8169_RXM_AcceptMulticast or RTL8169_RXM_AcceptMyPhys) |
777 | or eax,rtl8169_rx_config or (RTL8169_RXM_AcceptBroadcast or RTL8169_RXM_AcceptMulticast or RTL8169_RXM_AcceptMyPhys) |
786 | RTL_W32 RTL8169_REG_RxConfig,eax |
778 | RTL_W32 RTL8169_REG_RxConfig,eax |
787 | |
- | 788 | ; Multicast hash filter |
|
779 | 789 | RTL_W32 RTL8169_REG_MAR0 + 0,0xffffffff |
|
780 | ; Multicast hash filter |
790 | RTL_W32 RTL8169_REG_MAR0 + 4,0xffffffff |
781 | RTL_W32 RTL8169_REG_MAR0 + 0,0xffffffff |
791 | ret |
782 | RTL_W32 RTL8169_REG_MAR0 + 4,0xffffffff |
792 | endp |
783 | ret |
793 | |
784 | endp |
794 | proc rtl8169_init_ring |
785 | 795 | ||
786 | proc rtl8169_init_ring |
796 | ; DEBUGF 1,"K : rtl8169_init_ring\n" |
Line 787... | Line 797... | ||
787 | 797 | ||
Line 788... | Line 798... | ||
788 | ; DEBUGF 1,"K : rtl8169_init_ring\n" |
798 | xor eax, eax |
789 | 799 | mov [rtl8169_tpc.cur_rx], eax |
|
Line 790... | Line 800... | ||
790 | xor eax,eax |
800 | mov [rtl8169_tpc.cur_tx], eax |
Line 791... | Line 801... | ||
791 | mov [rtl8169_tpc.cur_rx],eax |
801 | |
Line 792... | Line 802... | ||
792 | mov [rtl8169_tpc.cur_tx],eax |
802 | mov edi, [rtl8169_tpc.TxDescArray] |
793 | 803 | mov ecx, (NUM_TX_DESC * sizeof.rtl8169_TxDesc) / 4 |
|
794 | mov edi,[rtl8169_tpc.TxDescArray] |
804 | cld |
795 | mov ecx,(NUM_TX_DESC * sizeof.rtl8169_TxDesc) / 4 |
805 | rep stosd |
- | 806 | mov edi, [rtl8169_tpc.RxDescArray] |
|
796 | cld |
807 | mov ecx, (NUM_RX_DESC * sizeof.rtl8169_RxDesc) / 4 |
797 | rep stosd |
808 | rep stosd |
798 | mov edi,[rtl8169_tpc.RxDescArray] |
809 | |
799 | mov ecx,(NUM_RX_DESC * sizeof.rtl8169_RxDesc) / 4 |
810 | mov edi, rtl8169_tpc.Tx_skbuff |
800 | rep stosd |
811 | mov eax, rtl8169_txb |
801 | 812 | mov ecx, NUM_TX_DESC |
|
802 | mov edi,rtl8169_tpc.Tx_skbuff |
813 | @@: |
803 | mov eax,rtl8169_txb |
814 | stosd |
804 | mov ecx,NUM_TX_DESC |
815 | inc eax ; add eax,RX_BUF_SIZE ??? |
805 | @@: stosd |
816 | loop @b |
806 | inc eax ; add eax,RX_BUF_SIZE ??? |
817 | |
807 | loop @b |
818 | ;!!! for (i = 0; i < NUM_RX_DESC; i++) { |
808 | 819 | ;!!! if (i == (NUM_RX_DESC - 1)) |
|
809 | ;!!! for (i = 0; i < NUM_RX_DESC; i++) { |
820 | ;!!! tpc->RxDescArray[i].status = (OWNbit | EORbit) | RX_BUF_SIZE; |
810 | ;!!! if (i == (NUM_RX_DESC - 1)) |
821 | ;!!! else |
811 | ;!!! tpc->RxDescArray[i].status = (OWNbit | EORbit) | RX_BUF_SIZE; |
822 | ;!!! tpc->RxDescArray[i].status = OWNbit | RX_BUF_SIZE; |
812 | ;!!! else |
823 | ;!!! tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; |
813 | ;!!! tpc->RxDescArray[i].status = OWNbit | RX_BUF_SIZE; |
824 | ;!!! tpc->RxDescArray[i].buf_addr = virt_to_bus(tpc->RxBufferRing[i]); |
814 | ;!!! tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; |
825 | ;!!! } |
815 | ;!!! tpc->RxDescArray[i].buf_addr = virt_to_bus(tpc->RxBufferRing[i]); |
826 | mov esi, rtl8169_tpc.RxBufferRing |
816 | ;!!! } |
827 | mov edi, [rtl8169_tpc.RxDescArray] |
817 | mov esi,rtl8169_tpc.RxBufferRing |
828 | mov eax, rtl8169_rxb |
818 | mov edi,[rtl8169_tpc.RxDescArray] |
829 | mov ecx, NUM_RX_DESC |
819 | mov eax,rtl8169_rxb |
830 | @@: |
820 | mov ecx,NUM_RX_DESC |
831 | mov [esi], eax |
821 | @@: mov [esi],eax |
832 | mov [edi+rtl8169_RxDesc.buf_addr], eax |
822 | mov [edi+rtl8169_RxDesc.buf_addr],eax |
833 | sub [edi+rtl8169_RxDesc.buf_addr], OS_BASE ; shurf 28.09.2008 |
823 | sub [edi+rtl8169_RxDesc.buf_addr],OS_BASE ; shurf 28.09.2008 |
834 | mov [edi+rtl8169_RxDesc.status], RTL8169_DSB_OWNbit or RX_BUF_SIZE |
824 | mov [edi+rtl8169_RxDesc.status],RTL8169_DSB_OWNbit or RX_BUF_SIZE |
835 | add esi, 4 |
825 | add esi,4 |
836 | add edi, sizeof.rtl8169_RxDesc |
826 | add edi,sizeof.rtl8169_RxDesc |
837 | add eax, RX_BUF_SIZE |
827 | add eax,RX_BUF_SIZE |
838 | loop @b |
- | 839 | ||
828 | loop @b |
840 | or [edi - sizeof.rtl8169_RxDesc + rtl8169_RxDesc.status], RTL8169_DSB_EORbit |
Line 829... | Line 841... | ||
829 | 841 | ||
830 | or [edi - sizeof.rtl8169_RxDesc + rtl8169_RxDesc.status],RTL8169_DSB_EORbit |
842 | ret |
831 | 843 | endp |
|
832 | ret |
844 | |
Line 833... | Line 845... | ||
833 | endp |
845 | proc rtl8169_hw_start |
834 | 846 | ||
835 | proc rtl8169_hw_start |
847 | ; DEBUGF 1,"K : rtl8169_hw_start\n" |
836 | 848 | ||
837 | ; DEBUGF 1,"K : rtl8169_hw_start\n" |
849 | ; Soft reset the chip |
838 | 850 | RTL_W8 RTL8169_REG_ChipCmd,RTL8169_CMD_Reset |
|
839 | ; Soft reset the chip |
851 | ; Check that the chip has finished the reset |
840 | RTL_W8 RTL8169_REG_ChipCmd,RTL8169_CMD_Reset |
852 | mov ecx, 1000 |
841 | ; Check that the chip has finished the reset |
853 | @@: |
842 | mov ecx,1000 |
854 | RTL_R8 RTL8169_REG_ChipCmd |
843 | @@: RTL_R8 RTL8169_REG_ChipCmd |
855 | and al, RTL8169_CMD_Reset |
844 | and al,RTL8169_CMD_Reset |
856 | jz @f |
845 | jz @f |
857 | stdcall udelay, 10 |
846 | stdcall udelay,10 |
858 | loop @b |
847 | loop @b |
859 | @@: |
848 | @@: |
860 | RTL_W8 RTL8169_REG_Cfg9346,RTL8169_CFG_9346_Unlock |
849 | RTL_W8 RTL8169_REG_Cfg9346,RTL8169_CFG_9346_Unlock |
861 | RTL_W8 RTL8169_REG_ChipCmd,RTL8169_CMD_TxEnb or RTL8169_CMD_RxEnb |
850 | RTL_W8 RTL8169_REG_ChipCmd,RTL8169_CMD_TxEnb or RTL8169_CMD_RxEnb |
862 | RTL_W8 RTL8169_REG_ETThReg,ETTh |
851 | RTL_W8 RTL8169_REG_ETThReg,ETTh |
863 | ; For gigabit rtl8169 |
852 | ; For gigabit rtl8169 |
864 | RTL_W16 RTL8169_REG_RxMaxSize,RxPacketMaxSize |
Line 853... | Line 865... | ||
853 | RTL_W16 RTL8169_REG_RxMaxSize,RxPacketMaxSize |
865 | ; Set Rx Config register |
854 | ; Set Rx Config register |
866 | RTL_R32 RTL8169_REG_RxConfig |
855 | RTL_R32 RTL8169_REG_RxConfig |
867 | mov ecx, [rtl8169_tpc.chipset] |
856 | mov ecx,[rtl8169_tpc.chipset] |
868 | and eax, [rtl_chip_info + ecx * 8 + 4]; RxConfigMask |
857 | and eax,[rtl_chip_info + ecx * 8 + 4] ; RxConfigMask |
869 | or eax, rtl8169_rx_config |
858 | or eax,rtl8169_rx_config |
870 | RTL_W32 RTL8169_REG_RxConfig,eax |
859 | RTL_W32 RTL8169_REG_RxConfig,eax |
871 | ; Set DMA burst size and Interframe Gap Time |
Line 860... | Line 872... | ||
860 | ; Set DMA burst size and Interframe Gap Time |
872 | RTL_W32 RTL8169_REG_TxConfig,(TX_DMA_BURST shl RTL8169_TXC_DMAShift) or (InterFrameGap shl RTL8169_TXC_InterFrameGapShift) |
861 | RTL_W32 RTL8169_REG_TxConfig,(TX_DMA_BURST shl RTL8169_TXC_DMAShift) or (InterFrameGap shl RTL8169_TXC_InterFrameGapShift) |
873 | RTL_R16 RTL8169_REG_CPlusCmd |
862 | RTL_R16 RTL8169_REG_CPlusCmd |
874 | RTL_W16 RTL8169_REG_CPlusCmd,ax |
Line 920... | Line 932... | ||
920 | ;*************************************************************************** |
932 | ;*************************************************************************** |
921 | proc rtl8169_probe |
933 | proc rtl8169_probe |
Line 922... | Line 934... | ||
922 | 934 | ||
Line 923... | Line 935... | ||
923 | ; DEBUGF 1,"K : rtl8169_probe: 0x%x : 0x%x 0x%x\n",[io_addr]:8,[pci_bus]:2,[pci_dev]:2 |
935 | ; DEBUGF 1,"K : rtl8169_probe: 0x%x : 0x%x 0x%x\n",[io_addr]:8,[pci_bus]:2,[pci_dev]:2 |
Line 924... | Line 936... | ||
924 | 936 | ||
925 | call rtl8169_init_board |
937 | call rtl8169_init_board |
926 | 938 | ||
927 | mov ecx,MAC_ADDR_LEN |
939 | mov ecx, MAC_ADDR_LEN |
928 | mov edx,[rtl8169_tpc.mmio_addr] |
940 | mov edx, [rtl8169_tpc.mmio_addr] |
- | 941 | add edx, RTL8169_REG_MAC0 |
|
929 | add edx,RTL8169_REG_MAC0 |
942 | xor ebx, ebx |
930 | xor ebx,ebx |
943 | ; Get MAC address. FIXME: read EEPROM |
931 | ; Get MAC address. FIXME: read EEPROM |
944 | @@: |
932 | @@: RTL_R8 dx |
945 | RTL_R8 dx |
933 | mov [node_addr+ebx],al |
946 | mov [node_addr+ebx], al |
Line 934... | Line 947... | ||
934 | inc edx |
947 | inc edx |
Line 935... | Line 948... | ||
935 | inc ebx |
948 | inc ebx |
936 | loop @b |
949 | loop @b |
937 | 950 | ||
938 | ; DEBUGF 1,"K : rtl8169_probe: MAC = %x-%x-%x-%x-%x-%x\n",[node_addr+0]:2,[node_addr+1]:2,[node_addr+2]:2,[node_addr+3]:2,[node_addr+4]:2,[node_addr+5]:2 |
951 | ; DEBUGF 1,"K : rtl8169_probe: MAC = %x-%x-%x-%x-%x-%x\n",[node_addr+0]:2,[node_addr+1]:2,[node_addr+2]:2,[node_addr+3]:2,[node_addr+4]:2,[node_addr+5]:2 |
939 | 952 | ||
940 | ; Config PHY |
953 | ; Config PHY |
941 | stdcall rtl8169_hw_PHY_config |
954 | stdcall rtl8169_hw_PHY_config |
942 | ; DEBUGF 1,"K : Set MAC Reg C+CR Offset 0x82h = 0x01h\n" |
955 | ; DEBUGF 1,"K : Set MAC Reg C+CR Offset 0x82h = 0x01h\n" |
943 | RTL_W8 0x82,0x01 |
956 | RTL_W8 0x82,0x01 |
944 | cmp [rtl8169_tpc.mcfg],MCFG_METHOD_03 |
957 | cmp [rtl8169_tpc.mcfg], MCFG_METHOD_03 |
945 | jae @f |
958 | jae @f |
946 | ; DEBUGF 1,"K : Set PCI Latency=0x40\n" |
959 | ; DEBUGF 1,"K : Set PCI Latency=0x40\n" |
947 | ; stdcall pci_write_config_byte,PCI_LATENCY_TIMER,0x40 |
960 | ; stdcall pci_write_config_byte,PCI_LATENCY_TIMER,0x40 |
948 | @@: |
961 | @@: |
949 | cmp [rtl8169_tpc.mcfg],MCFG_METHOD_02 |
962 | cmp [rtl8169_tpc.mcfg], MCFG_METHOD_02 |
950 | jne @f |
963 | jne @f |
951 | ; DEBUGF 1,"K : Set MAC Reg C+CR Offset 0x82h = 0x01h\n" |
964 | ; DEBUGF 1,"K : Set MAC Reg C+CR Offset 0x82h = 0x01h\n" |
952 | RTL_W8 0x82,0x01 |
965 | RTL_W8 0x82,0x01 |
953 | ; DEBUGF 1,"K : Set PHY Reg 0x0bh = 0x00h\n" |
966 | ; DEBUGF 1,"K : Set PHY Reg 0x0bh = 0x00h\n" |
954 | stdcall RTL8169_WRITE_GMII_REG,0x0b,0x0000 ; w 0x0b 15 0 0 |
967 | stdcall RTL8169_WRITE_GMII_REG, 0x0b, 0x0000 ; w 0x0b 15 0 0 |
955 | @@: |
968 | @@: |
956 | ; if TBI is not enabled |
969 | ; if TBI is not enabled |
957 | RTL_R8 RTL8169_REG_PHYstatus |
970 | RTL_R8 RTL8169_REG_PHYstatus |
958 | test al,RTL8169_PHYS_TBI_Enable |
971 | test al, RTL8169_PHYS_TBI_Enable |
959 | jz .tbi_dis |
972 | jz .tbi_dis |
960 | stdcall RTL8169_READ_GMII_REG,RTL8169_PHY_AUTO_NEGO_REG |
973 | stdcall RTL8169_READ_GMII_REG, RTL8169_PHY_AUTO_NEGO_REG |
961 | ; enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged |
974 | ; enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged |
962 | and eax,0x0C1F |
975 | and eax, 0x0C1F |
963 | or eax,RTL8169_PHY_Cap_10_Half or RTL8169_PHY_Cap_10_Full or RTL8169_PHY_Cap_100_Half or RTL8169_PHY_Cap_100_Full |
976 | or eax, RTL8169_PHY_Cap_10_Half or RTL8169_PHY_Cap_10_Full or RTL8169_PHY_Cap_100_Half or RTL8169_PHY_Cap_100_Full |
964 | stdcall RTL8169_WRITE_GMII_REG,RTL8169_PHY_AUTO_NEGO_REG,eax |
977 | stdcall RTL8169_WRITE_GMII_REG, RTL8169_PHY_AUTO_NEGO_REG, eax |
965 | ; enable 1000 Full Mode |
978 | ; enable 1000 Full Mode |
966 | stdcall RTL8169_WRITE_GMII_REG,RTL8169_PHY_1000_CTRL_REG,RTL8169_PHY_Cap_1000_Full or RTL8169_PHY_Cap_1000_Half ; rtl8168 |
979 | stdcall RTL8169_WRITE_GMII_REG, RTL8169_PHY_1000_CTRL_REG, RTL8169_PHY_Cap_1000_Full or RTL8169_PHY_Cap_1000_Half; rtl8168 |
- | 980 | ; Enable auto-negotiation and restart auto-nigotiation |
|
967 | ; Enable auto-negotiation and restart auto-nigotiation |
981 | stdcall RTL8169_WRITE_GMII_REG, RTL8169_PHY_CTRL_REG, RTL8169_PHY_Enable_Auto_Nego or RTL8169_PHY_Restart_Auto_Nego |
968 | stdcall RTL8169_WRITE_GMII_REG,RTL8169_PHY_CTRL_REG,RTL8169_PHY_Enable_Auto_Nego or RTL8169_PHY_Restart_Auto_Nego |
982 | stdcall udelay, 100 |
969 | stdcall udelay,100 |
983 | mov ecx, 10000 |
970 | mov ecx,10000 |
984 | ; wait for auto-negotiation process |
971 | ; wait for auto-negotiation process |
985 | @@: |
972 | @@: dec ecx |
986 | dec ecx |
973 | jz @f |
987 | jz @f |
974 | stdcall RTL8169_READ_GMII_REG,RTL8169_PHY_STAT_REG |
988 | stdcall RTL8169_READ_GMII_REG, RTL8169_PHY_STAT_REG |
975 | stdcall udelay,100 |
989 | stdcall udelay, 100 |
976 | test eax,RTL8169_PHY_Auto_Neco_Comp |
990 | test eax, RTL8169_PHY_Auto_Neco_Comp |
977 | jz @b |
991 | jz @b |
978 | RTL_R8 RTL8169_REG_PHYstatus |
992 | RTL_R8 RTL8169_REG_PHYstatus |
979 | jmp @f |
993 | jmp @f |
980 | .tbi_dis: |
994 | .tbi_dis: |
Line 981... | Line 995... | ||
981 | stdcall udelay,100 |
995 | stdcall udelay, 100 |
982 | @@: |
996 | @@: |
983 | call rtl8169_reset |
997 | call rtl8169_reset |
Line 995... | Line 1009... | ||
995 | ;*************************************************************************** |
1009 | ;*************************************************************************** |
996 | proc rtl8169_reset |
1010 | proc rtl8169_reset |
Line 997... | Line 1011... | ||
997 | 1011 | ||
Line 998... | Line 1012... | ||
998 | ; DEBUGF 1,"K : rtl8169_reset: 0x%x : 0x%x 0x%x\n",[io_addr]:8,[pci_bus]:2,[pci_dev]:2 |
1012 | ; DEBUGF 1,"K : rtl8169_reset: 0x%x : 0x%x 0x%x\n",[io_addr]:8,[pci_bus]:2,[pci_dev]:2 |
999 | 1013 | ||
1000 | mov [rtl8169_tpc.TxDescArrays],rtl8169_tx_ring |
1014 | mov [rtl8169_tpc.TxDescArrays], rtl8169_tx_ring |
1001 | ; Tx Desscriptor needs 256 bytes alignment |
1015 | ; Tx Desscriptor needs 256 bytes alignment |
1002 | mov [rtl8169_tpc.TxDescArray],rtl8169_tx_ring |
1016 | mov [rtl8169_tpc.TxDescArray], rtl8169_tx_ring |
1003 | 1017 | ||
1004 | mov [rtl8169_tpc.RxDescArrays],rtl8169_rx_ring |
1018 | mov [rtl8169_tpc.RxDescArrays], rtl8169_rx_ring |
1005 | ; Rx Desscriptor needs 256 bytes alignment |
1019 | ; Rx Desscriptor needs 256 bytes alignment |
1006 | mov [rtl8169_tpc.RxDescArray],rtl8169_rx_ring |
1020 | mov [rtl8169_tpc.RxDescArray], rtl8169_rx_ring |
1007 | 1021 | ||
1008 | call rtl8169_init_ring |
1022 | call rtl8169_init_ring |
1009 | call rtl8169_hw_start |
1023 | call rtl8169_hw_start |
1010 | ; Construct a perfect filter frame with the mac address as first match |
1024 | ; Construct a perfect filter frame with the mac address as first match |
1011 | ; and broadcast for all others |
1025 | ; and broadcast for all others |
1012 | mov edi,rtl8169_txb |
1026 | mov edi, rtl8169_txb |
1013 | or al,-1 |
1027 | or al, -1 |
1014 | mov ecx,192 |
1028 | mov ecx, 192 |
1015 | cld |
1029 | cld |
1016 | rep stosb |
1030 | rep stosb |
1017 | 1031 | ||
1018 | mov esi,node_addr |
1032 | mov esi, node_addr |
1019 | mov edi,rtl8169_txb |
1033 | mov edi, rtl8169_txb |
1020 | movsd |
1034 | movsd |
1021 | movsw |
1035 | movsw |
1022 | 1036 | ||
1023 | mov eax,[pci_data] |
1037 | mov eax, [pci_data] |
1024 | mov [eth_status],eax |
1038 | mov [eth_status], eax |
Line 1025... | Line 1039... | ||
1025 | ret |
1039 | ret |
1026 | endp |
1040 | endp |
1027 | 1041 | ||
Line 1040... | Line 1054... | ||
1040 | ;*************************************************************************** |
1054 | ;*************************************************************************** |
1041 | proc rtl8169_transmit |
1055 | proc rtl8169_transmit |
Line 1042... | Line 1056... | ||
1042 | 1056 | ||
Line 1043... | Line 1057... | ||
1043 | ; DEBUGF 1,"K : rtl8169_transmit\n" ;: 0x%x : 0x%x 0x%x 0x%x 0x%x\n",[io_addr]:8,edi,bx,ecx,esi |
1057 | ; DEBUGF 1,"K : rtl8169_transmit\n" ;: 0x%x : 0x%x 0x%x 0x%x 0x%x\n",[io_addr]:8,edi,bx,ecx,esi |
1044 | 1058 | ||
1045 | push ecx edx esi |
1059 | push ecx edx esi |
1046 | mov eax,MAX_ETH_FRAME_SIZE |
1060 | mov eax, MAX_ETH_FRAME_SIZE |
1047 | mul [rtl8169_tpc.cur_tx] |
1061 | mul [rtl8169_tpc.cur_tx] |
1048 | mov esi,edi |
1062 | mov esi, edi |
1049 | ; point to the current txb incase multiple tx_rings are used |
1063 | ; point to the current txb incase multiple tx_rings are used |
1050 | mov edi,[rtl8169_tpc.Tx_skbuff + eax * 4] |
1064 | mov edi, [rtl8169_tpc.Tx_skbuff + eax * 4] |
1051 | mov eax,edi |
1065 | mov eax, edi |
1052 | cld |
1066 | cld |
1053 | ; copy destination address |
1067 | ; copy destination address |
1054 | movsd |
1068 | movsd |
1055 | movsw |
1069 | movsw |
1056 | ; copy source address |
1070 | ; copy source address |
1057 | mov esi,node_addr |
1071 | mov esi, node_addr |
1058 | movsd |
1072 | movsd |
1059 | movsw |
1073 | movsw |
1060 | ; copy packet type |
1074 | ; copy packet type |
1061 | mov [edi],bx |
1075 | mov [edi], bx |
1062 | add edi,2 |
1076 | add edi, 2 |
1063 | ; copy the packet data |
1077 | ; copy the packet data |
1064 | pop esi edx ecx |
1078 | pop esi edx ecx |
1065 | push ecx |
1079 | push ecx |
1066 | shr ecx,2 |
1080 | shr ecx, 2 |
1067 | rep movsd |
1081 | rep movsd |
1068 | pop ecx |
1082 | pop ecx |
1069 | push ecx |
1083 | push ecx |
Line 1070... | Line 1084... | ||
1070 | and ecx,3 |
1084 | and ecx, 3 |
1071 | rep movsb |
1085 | rep movsb |
1072 | 1086 | ||
1073 | ;!!! s += ETH_HLEN; |
1087 | ;!!! s += ETH_HLEN; |
1074 | ;!!! s &= 0x0FFF; |
1088 | ;!!! s &= 0x0FFF; |
1075 | ;!!! while (s < ETH_ZLEN) |
1089 | ;!!! while (s < ETH_ZLEN) |
1076 | ;!!! ptxb[s++] = '\0'; |
1090 | ;!!! ptxb[s++] = '\0'; |
1077 | mov edi,eax |
1091 | mov edi, eax |
1078 | pop ecx |
1092 | pop ecx |
1079 | push eax |
1093 | push eax |
1080 | add ecx,ETH_HLEN |
1094 | add ecx, ETH_HLEN |
- | 1095 | and ecx, 0x0FFF |
|
1081 | and ecx,0x0FFF |
1096 | xor al, al |
1082 | xor al,al |
1097 | add edi, ecx |
1083 | add edi,ecx |
1098 | @@: |
1084 | @@: cmp ecx,ETH_ZLEN |
1099 | cmp ecx, ETH_ZLEN |
1085 | jae @f |
- | |
1086 | stosb |
1100 | jae @f |
1087 | inc ecx |
- | |
1088 | jmp @b |
- | |
1089 | @@: pop eax |
- | |
1090 | - | ||
1091 | mov ebx,eax |
- | |
1092 | mov eax,sizeof.rtl8169_TxDesc |
- | |
1093 | mul [rtl8169_tpc.cur_tx] |
- | |
1094 | add eax,[rtl8169_tpc.TxDescArray] |
- | |
1095 | xchg eax,ebx |
- | |
1096 | mov [ebx + rtl8169_TxDesc.buf_addr],eax |
- | |
1097 | sub [ebx + rtl8169_TxDesc.buf_addr],OS_BASE ; shurf 28.09.2008 |
- | |
1098 | 1101 | stosb |
|
1099 | mov eax,ecx |
1102 | inc ecx |
1100 | cmp eax,ETH_ZLEN |
- | |
1101 | jae @f |
- | |
1102 | mov eax,ETH_ZLEN |
- | |
1103 | @@: or eax,RTL8169_DSB_OWNbit or RTL8169_DSB_FSbit or RTL8169_DSB_LSbit |
- | |
1104 | cmp [rtl8169_tpc.cur_tx],NUM_TX_DESC - 1 |
- | |
Line -... | Line 1103... | ||
- | 1103 | jmp @b |
|
- | 1104 | @@: |
|
- | 1105 | pop eax |
|
- | 1106 | ||
- | 1107 | mov ebx, eax |
|
- | 1108 | mov eax, sizeof.rtl8169_TxDesc |
|
- | 1109 | mul [rtl8169_tpc.cur_tx] |
|
- | 1110 | add eax, [rtl8169_tpc.TxDescArray] |
|
- | 1111 | xchg eax, ebx |
|
- | 1112 | mov [ebx + rtl8169_TxDesc.buf_addr], eax |
|
- | 1113 | sub [ebx + rtl8169_TxDesc.buf_addr], OS_BASE ; shurf 28.09.2008 |
|
- | 1114 | ||
- | 1115 | mov eax, ecx |
|
- | 1116 | cmp eax, ETH_ZLEN |
|
- | 1117 | jae @f |
|
- | 1118 | mov eax, ETH_ZLEN |
|
- | 1119 | @@: |
|
- | 1120 | or eax, RTL8169_DSB_OWNbit or RTL8169_DSB_FSbit or RTL8169_DSB_LSbit |
|
- | 1121 | cmp [rtl8169_tpc.cur_tx], NUM_TX_DESC - 1 |
|
- | 1122 | jne @f |
|
1105 | jne @f |
1123 | or eax, RTL8169_DSB_EORbit |
Line 1106... | Line 1124... | ||
1106 | or eax,RTL8169_DSB_EORbit |
1124 | @@: |
1107 | @@: mov [ebx + rtl8169_TxDesc.status],eax |
1125 | mov [ebx + rtl8169_TxDesc.status], eax |
Line 1108... | Line 1126... | ||
1108 | 1126 | ||
1109 | RTL_W8 RTL8169_REG_TxPoll,0x40 ; set polling bit |
1127 | RTL_W8 RTL8169_REG_TxPoll,0x40 ; set polling bit |
1110 | 1128 | ||
- | 1129 | inc [rtl8169_tpc.cur_tx] |
|
1111 | inc [rtl8169_tpc.cur_tx] |
1130 | and [rtl8169_tpc.cur_tx], NUM_TX_DESC - 1 |
1112 | and [rtl8169_tpc.cur_tx],NUM_TX_DESC - 1 |
1131 | |
1113 | 1132 | ;!!! to = currticks() + TX_TIMEOUT; |
|
1114 | ;!!! to = currticks() + TX_TIMEOUT; |
1133 | ;!!! while ((tpc->TxDescArray[entry].status & OWNbit) && (currticks() < to)); /* wait */ |
1115 | ;!!! while ((tpc->TxDescArray[entry].status & OWNbit) && (currticks() < to)); /* wait */ |
1134 | mov ecx, TX_TIMEOUT / 10 |
1116 | mov ecx,TX_TIMEOUT / 10 |
1135 | @@: |
Line 1117... | Line 1136... | ||
1117 | @@: test [ebx + rtl8169_TxDesc.status],RTL8169_DSB_OWNbit |
1136 | test [ebx + rtl8169_TxDesc.status], RTL8169_DSB_OWNbit |
1118 | jnz @f |
1137 | jnz @f |
Line 1119... | Line 1138... | ||
1119 | stdcall udelay,10 |
1138 | stdcall udelay, 10 |
1120 | loop @b |
1139 | loop @b |
1121 | ; DEBUGF 1,"K : rtl8169_transmit: TX Time Out\n" |
1140 | ; DEBUGF 1,"K : rtl8169_transmit: TX Time Out\n" |
Line 1137... | Line 1156... | ||
1137 | ;*************************************************************************** |
1156 | ;*************************************************************************** |
1138 | proc rtl8169_poll |
1157 | proc rtl8169_poll |
Line 1139... | Line 1158... | ||
1139 | 1158 | ||
Line 1140... | Line 1159... | ||
1140 | ; DEBUGF 1,"K : rtl8169_poll\n" ;: 0x%x : none\n",[io_addr]:8 |
1159 | ; DEBUGF 1,"K : rtl8169_poll\n" ;: 0x%x : none\n",[io_addr]:8 |
Line 1141... | Line 1160... | ||
1141 | 1160 | ||
1142 | mov word[eth_rx_data_len],0 |
1161 | mov word[eth_rx_data_len], 0 |
1143 | 1162 | ||
1144 | mov eax,sizeof.rtl8169_RxDesc |
1163 | mov eax, sizeof.rtl8169_RxDesc |
Line 1145... | Line 1164... | ||
1145 | mul [rtl8169_tpc.cur_rx] |
1164 | mul [rtl8169_tpc.cur_rx] |
Line 1146... | Line 1165... | ||
1146 | add eax,[rtl8169_tpc.RxDescArray] |
1165 | add eax, [rtl8169_tpc.RxDescArray] |
1147 | mov ebx,eax |
1166 | mov ebx, eax |
Line 1148... | Line 1167... | ||
1148 | 1167 | ||
Line 1149... | Line 1168... | ||
1149 | ; DEBUGF 1,"K : rtl8169_RxDesc.status = 0x%x\n",[ebx + rtl8169_RxDesc.status] |
1168 | ; DEBUGF 1,"K : rtl8169_RxDesc.status = 0x%x\n",[ebx + rtl8169_RxDesc.status] |
1150 | 1169 | ||
Line 1151... | Line 1170... | ||
1151 | test [ebx + rtl8169_RxDesc.status],RTL8169_DSB_OWNbit ; 0x80000600 |
1170 | test [ebx + rtl8169_RxDesc.status], RTL8169_DSB_OWNbit; 0x80000600 |
Line 1152... | Line 1171... | ||
1152 | jnz .exit |
1171 | jnz .exit |
1153 | 1172 | ||
Line 1154... | Line 1173... | ||
1154 | ; DEBUGF 1,"K : rtl8169_tpc.cur_rx = %u\n",[rtl8169_tpc.cur_rx] |
1173 | ; DEBUGF 1,"K : rtl8169_tpc.cur_rx = %u\n",[rtl8169_tpc.cur_rx] |
1155 | 1174 | ||
1156 | ; h/w no longer present (hotplug?) or major error, bail |
1175 | ; h/w no longer present (hotplug?) or major error, bail |
Line 1157... | Line 1176... | ||
1157 | RTL_R16 RTL8169_REG_IntrStatus |
1176 | RTL_R16 RTL8169_REG_IntrStatus |
Line 1158... | Line 1177... | ||
1158 | 1177 | ||
Line 1159... | Line 1178... | ||
1159 | ; DEBUGF 1,"K : IntrStatus = 0x%x\n",ax |
1178 | ; DEBUGF 1,"K : IntrStatus = 0x%x\n",ax |
1160 | 1179 | ||
1161 | cmp ax,0xFFFF |
1180 | cmp ax, 0xFFFF |
1162 | je .exit |
1181 | je .exit |
1163 | 1182 | ||
1164 | push eax |
1183 | push eax |
Line 1165... | Line 1184... | ||
1165 | and ax,not (RTL8169_ISB_RxFIFOOver or RTL8169_ISB_RxOverflow or RTL8169_ISB_RxOK) |
1184 | and ax, not (RTL8169_ISB_RxFIFOOver or RTL8169_ISB_RxOverflow or RTL8169_ISB_RxOK) |
Line 1166... | Line 1185... | ||
1166 | RTL_W16 RTL8169_REG_IntrStatus,ax |
1185 | RTL_W16 RTL8169_REG_IntrStatus,ax |
1167 | 1186 | ||
1168 | mov eax,[ebx + rtl8169_RxDesc.status] |
1187 | mov eax, [ebx + rtl8169_RxDesc.status] |
1169 | 1188 | ||
1170 | ; DEBUGF 1,"K : RxDesc.status = 0x%x\n",eax |
1189 | ; DEBUGF 1,"K : RxDesc.status = 0x%x\n",eax |
1171 | 1190 | ||
1172 | test eax,RTL8169_SD_RxRES |
1191 | test eax, RTL8169_SD_RxRES |
1173 | jnz .else |
1192 | jnz .else |
1174 | and eax,0x00001FFF |
1193 | and eax, 0x00001FFF |
1175 | ; jz .exit.pop |
1194 | ; jz .exit.pop |
1176 | add eax,-4 |
1195 | add eax, -4 |
1177 | mov [eth_rx_data_len],ax |
1196 | mov [eth_rx_data_len], ax |
1178 | 1197 | ||
1179 | ; DEBUGF 1,"K : rtl8169_poll: data length = %u\n",ax |
1198 | ; DEBUGF 1,"K : rtl8169_poll: data length = %u\n",ax |
1180 | 1199 | ||
1181 | push eax |
1200 | push eax |
1182 | mov ecx,eax |
1201 | mov ecx, eax |
- | 1202 | shr ecx, 2 |
|
1183 | shr ecx,2 |
1203 | mov eax, [rtl8169_tpc.cur_rx] |
1184 | mov eax,[rtl8169_tpc.cur_rx] |
1204 | mov edx, [rtl8169_tpc.RxBufferRing + eax * 4] |
1185 | mov edx,[rtl8169_tpc.RxBufferRing + eax * 4] |
1205 | mov esi, edx |
1186 | mov esi,edx |
1206 | mov edi, Ether_buffer |
1187 | mov edi,Ether_buffer |
1207 | cld |
1188 | cld |
1208 | rep movsd |
1189 | rep movsd |
1209 | pop ecx |
1190 | pop ecx |
1210 | and ecx, 3 |
1191 | and ecx,3 |
1211 | rep movsb |
1192 | rep movsb |
1212 | |
1193 | 1213 | mov eax, RTL8169_DSB_OWNbit or RX_BUF_SIZE |
|
1194 | mov eax,RTL8169_DSB_OWNbit or RX_BUF_SIZE |
1214 | cmp [rtl8169_tpc.cur_rx], NUM_RX_DESC - 1 |
1195 | cmp [rtl8169_tpc.cur_rx],NUM_RX_DESC - 1 |
1215 | jne @f |
1196 | jne @f |
1216 | or eax, RTL8169_DSB_EORbit |
1197 | or eax,RTL8169_DSB_EORbit |
1217 | @@: |
1198 | @@: mov [ebx + rtl8169_RxDesc.status],eax |
1218 | mov [ebx + rtl8169_RxDesc.status], eax |
1199 | 1219 | ||
1200 | mov [ebx + rtl8169_RxDesc.buf_addr],edx |
1220 | mov [ebx + rtl8169_RxDesc.buf_addr], edx |
Line 1201... | Line 1221... | ||
1201 | sub [ebx + rtl8169_RxDesc.buf_addr],OS_BASE ; shurf 28.09.2008 |
1221 | sub [ebx + rtl8169_RxDesc.buf_addr], OS_BASE ; shurf 28.09.2008 |
1202 | jmp @f |
1222 | jmp @f |
1203 | .else: |
1223 | .else: |