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Rev 1508 | Rev 1551 | ||
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Line 26... | Line 26... | ||
26 | ; 2) direct HT-detection (no ACPI or BIOS service used) |
26 | ; 2) direct HT-detection (no ACPI or BIOS service used) |
27 | ; 3) Only AMD/HT processors currently supported |
27 | ; 3) Only AMD/HT processors currently supported |
28 | ; |
28 | ; |
29 | ;*************************************************************************** |
29 | ;*************************************************************************** |
Line -... | Line 30... | ||
- | 30 | ||
30 | 31 | align 4 |
|
31 | mmio_pcie_cfg_addr dd 0x00000000 ; pcie space may be defined here |
32 | mmio_pcie_cfg_addr dd 0x00000000 ; pcie space may be defined here |
- | 33 | mmio_pcie_cfg_lim dd 0x000FFFFF ; upper pcie space address |
|
- | 34 | mmio_pcie_cfg_pdes dw 0 ; number of PDEs to map the space |
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Line 32... | Line 35... | ||
32 | mmio_pcie_cfg_lim dd 0x000FFFFF ; upper pcie space address |
35 | PCIe_bus_range dw 0 ; the Bus range: power-of-2 Megabytes |
33 | - | ||
34 | 36 | ||
35 | align 4 |
37 | |
36 | 38 | align 4 |
|
37 | pci_ext_config: |
39 | pci_ext_config: |
38 | mov ebx, [mmio_pcie_cfg_addr] |
40 | mov ebx, [mmio_pcie_cfg_addr] |
Line 58... | Line 60... | ||
58 | sub bl, 4 |
60 | sub bl, 4 |
59 | and al, 0x80 ; check the NP bit |
61 | and al, 0x80 ; check the NP bit |
60 | jz .no_pcie_cfg |
62 | jz .no_pcie_cfg |
61 | shl eax, 8 ; bus:[27..20], dev:[19:15] |
63 | shl eax, 8 ; bus:[27..20], dev:[19:15] |
62 | or eax, 0x00007FFC ; fun:[14..12], reg:[11:2] |
64 | or eax, 0x00007FFC ; fun:[14..12], reg:[11:2] |
63 | mov [mmio_pcie_cfg_lim], eax |
65 | ; mov [mmio_pcie_cfg_lim], eax |
64 | mov cl, bl |
66 | mov cl, bl |
65 | mov ax, 0x0002 ; bus = 0, 1dword to read |
67 | mov ax, 0x0002 ; bus = 0, 1dword to read |
66 | call pci_read_reg |
68 | call pci_read_reg |
67 | mov bx, cx |
69 | mov bx, cx |
68 | test al, 0x03 ; MMIO Base RW enabled? |
70 | test al, 0x03 ; MMIO Base RW enabled? |
Line 72... | Line 74... | ||
72 | xor al, al |
74 | xor al, al |
73 | shl eax, 8 |
75 | shl eax, 8 |
74 | test eax, 0x000F0000 ; MMIO Base must be bus0-aligned |
76 | test eax, 0x000F0000 ; MMIO Base must be bus0-aligned |
75 | jnz .no_pcie_cfg |
77 | jnz .no_pcie_cfg |
76 | mov [mmio_pcie_cfg_addr], eax |
78 | mov [mmio_pcie_cfg_addr], eax |
77 | add eax, 0x000FFFFC |
79 | ; add eax, 0x000FFFFC |
78 | sub eax,[mmio_pcie_cfg_lim] ; MMIO must cover at least one bus |
80 | ; sub eax,[mmio_pcie_cfg_lim] ; MMIO must cover at least one bus |
79 | ja .no_pcie_cfg |
81 | ; ja .no_pcie_cfg |
Line 80... | Line 82... | ||
80 | 82 | ||
81 | ; -- it looks like a true PCIe config space; |
- | |
82 | mov eax,[mmio_pcie_cfg_addr] ; physical address |
- | |
83 | or eax, (PG_SHARED + PG_LARGE + PG_USER) |
- | |
84 | mov ebx, PCIe_CONFIG_SPACE ; linear address |
- | |
85 | mov ecx, ebx |
- | |
86 | shr ebx, 20 |
- | |
87 | add ebx, sys_pgdir ; PgDir entry @ |
- | |
88 | @@: |
- | |
89 | mov dword[ebx], eax ; map 4 buses |
- | |
90 | invlpg [ecx] |
- | |
91 | cmp bl, 4 |
- | |
92 | jz .pcie_cfg_mapped ; fix it later |
- | |
93 | add bl, 4 ; next PgDir entry |
- | |
94 | add eax, 0x400000 ; eax += 4M |
- | |
95 | add ecx, 0x400000 |
- | |
Line 96... | Line 83... | ||
96 | jmp @b |
83 | ; -- it looks like a true PCIe config space; |
Line 97... | Line -... | ||
97 | - | ||
98 | .pcie_cfg_mapped: |
84 | |
99 | 85 | .pcie_cfg_mapped: |
|
100 | ; -- glad to have the extended PCIe config field found |
86 | |
Line 101... | Line 87... | ||
101 | mov esi, boot_pcie_ok |
87 | mov esi, boot_pcie_ok |