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Rev 2014 Rev 3519
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; ---- common mapping procedure ----
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; ---- common mapping procedure ----
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; (eax = phys. address of PCIe conf.space)
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; (eax = phys. address of PCIe conf.space)
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;
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;
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map_pcie_pages:
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map_pcie_pages:
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	or	eax, (PG_NOCACHE + PG_SHARED + PG_LARGE + PG_UW)  ;  UW is unsafe, fix it!
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	or	eax, (PG_NOCACHE + PG_SHARED + PG_LARGE + PG_UW)  ;  UW is unsafe!
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	mov	ecx, PCIe_CONFIG_SPACE			; linear address
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	mov	ecx, PCIe_CONFIG_SPACE			; linear address
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	mov	ebx, ecx
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	mov	ebx, ecx
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	shr	ebx, 20
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	shr	ebx, 20
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	add	ebx, (sys_pgdir - OS_BASE)		; PgDir entry @
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	add	ebx, (sys_pgdir - OS_BASE)		; PgDir entry @
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	mov	dword[ebx], eax 		; map 4 buses
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	mov	dword[ebx], eax 		; map 4 buses
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	add	bx,  4				; new PDE
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	add	bx,  4				; new PDE
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	add	eax, 0x400000			; +4M phys.
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	add	eax, 0x400000			; +4M phys.
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	add	ecx, 0x400000			; +4M lin.
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	add	ecx, 0x400000			; +4M lin.
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	cmp	dl, byte[mmio_pcie_cfg_pdes-OS_BASE]
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	cmp	dl, byte[mmio_pcie_cfg_pdes-OS_BASE]
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	jae	.pcie_cfg_mapped
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	jae	pcie_cfg_mapped
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	inc	dl
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	inc	dl
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	jmp	.write_pde
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	jmp	.write_pde
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;        mov     eax, cr3
 - 
 
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;        mov     cr3, eax                        ; flush TLB
 - 
 
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.pcie_cfg_mapped:
 - 
 
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	ret	; <<< OK >>>
 - 
 
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; ---- stepping 10h CPUs and Fusion APUs: the configspace is stored in MSR_C001_0058 ----
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; ---- stepping 10h CPUs and Fusion APUs: the configspace is stored in MSR_C001_0058 ----
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align 4
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align 4
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fusion_pcie_init:
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fusion_pcie_init:
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	shl	edx, 22
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	shl	edx, 22
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	dec	edx
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	dec	edx
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	add	edx, eax			; the upper configspace limit
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	add	edx, eax			; the upper configspace limit
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	mov	dword[mmio_pcie_cfg_lim-OS_BASE], edx
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	mov	dword[mmio_pcie_cfg_lim-OS_BASE], edx
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pcie_cfg_mapped:
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- 
 
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create_mmio_pte:
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- 
 
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	mov	ecx, mmio_pte                           ; physical address
- 
 
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	or	ecx, (PG_NOCACHE + PG_SHARED)
- 
 
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	mov	ebx, FUSION_MMIO			; linear address
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	shr	ebx, 20
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	add	ebx, (sys_pgdir - OS_BASE)		; PgDir entry @
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        mov     dword[ebx], ecx                         ; Fusion MMIO tables
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- 
 
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map_apic_mmio:
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        mov     ecx, 0x01B      ; APIC BAR
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        rdmsr
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        and     eax, 0xFFFFF000                         ; physical address
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	or	eax, (PG_NOCACHE + PG_SHARED + PG_UW)   ;  UW is unsafe!
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        mov     dword[mmio_pte + 0], eax
- 
 
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	jmp	map_pcie_pages
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	ret	; <<< OK >>>
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