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Rev 1683 Rev 1928
Line 134... Line 134...
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	call	rs7xx_nbconfig_read_pci
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	call	rs7xx_nbconfig_read_pci
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	mov	ebx, eax
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	mov	ebx, eax
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	call	rs7xx_nbconfig_flush_pci
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	call	rs7xx_nbconfig_flush_pci
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	mov	eax, ebx
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	mov	eax, ebx
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	and	eax, 0xFFE00000 		; valid bits [31..21]
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	and	eax, 0xFFE00000 		; valid bits [31..21]
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	jz	$				; NB BAR3 may be invisible!
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	jz	$				; invalid map!
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.addr_found:
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.addr_found:
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	mov	dword[mmio_pcie_cfg_addr-OS_BASE], eax	; physical address (lower 32 bits)
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	mov	dword[mmio_pcie_cfg_addr-OS_BASE], eax	; physical address (lower 32 bits)
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	add	dword[mmio_pcie_cfg_lim-OS_BASE],  eax
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	add	dword[mmio_pcie_cfg_lim-OS_BASE],  eax
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; ---- common mapping procedure ----
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; (eax = phys. address of PCIe conf.space)
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;
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map_pcie_pages:
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	or	eax, (PG_NOCACHE + PG_SHARED + PG_LARGE + PG_UW)  ;  by the way, UW is unsafe!
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	or	eax, (PG_NOCACHE + PG_SHARED + PG_LARGE + PG_UW)  ;  UW is unsafe, fix it!
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	mov	ecx, PCIe_CONFIG_SPACE			; linear address
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	mov	ecx, PCIe_CONFIG_SPACE			; linear address
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	mov	ebx, ecx
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	mov	ebx, ecx
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	shr	ebx, 20
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	shr	ebx, 20
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	add	ebx, (sys_pgdir - OS_BASE)		; PgDir entry @
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	add	ebx, (sys_pgdir - OS_BASE)		; PgDir entry @
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;        mov     eax, cr3
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;        mov     eax, cr3
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;        mov     cr3, eax                        ; flush TLB
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;        mov     cr3, eax                        ; flush TLB
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.pcie_cfg_mapped:
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.pcie_cfg_mapped:
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	ret	; <<< OK >>>
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	ret	; <<< OK >>>
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; ---- stepping 10h CPUs and Fusion APUs: the configspace is stored in MSR_C001_0058 ----
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align 4
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fusion_pcie_init:
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        mov     ecx, 0xC0010058
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        rdmsr
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        or      edx, edx
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        jnz     $                               ; PCIe is in the upper memory. Stop.
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        xchg    dl, al
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	mov	dword[mmio_pcie_cfg_addr-OS_BASE], eax	; store the physical address
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        mov     ecx, edx
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        and     dl, 1
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        jz      $                               ; bit[0] = 1 means no PCIe mapping allowed. Stop.
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        shr     cl, 2                           ; ecx = log2(number of buses)
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	mov	word[PCIe_bus_range-OS_BASE], cx
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        sub     cl, 2
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        jae     @f
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        xor     cl, cl
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@@:
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        shl     edx, cl                         ; edx = number of 4M pages to map
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	mov	word[mmio_pcie_cfg_pdes-OS_BASE], dx
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        shl     edx, 22
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        dec     edx
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        add     edx, eax                        ; the upper configspace limit
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	mov	dword[mmio_pcie_cfg_lim-OS_BASE], edx
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        jmp     map_pcie_pages
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	xor	eax,   eax
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	xor	eax,   eax
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	mov	[edx], eax
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	mov	[edx], eax
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	pop	edx
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	pop	edx
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	ret
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	ret
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;------------------------------------------------
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align 4
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sys_rdmsr:
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;  in: [esp+8] = MSR#
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; out: [esp+8] = MSR[63:32]
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;        [eax] = MSR[31: 0]
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;------------------------------------------------
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        push    ecx edx
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        mov     ecx, [esp+16]
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        rdmsr
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        mov     [esp+16], edx
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        pop     edx ecx